Source Code Documentation

Sniper Multi-Core Simulator
Generated by Doxygen 1.8.13

Contents
1 Namespace Index 1
1.1 Namespace List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Hierarchical Index 3
2.1 Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Class Index 5
3.1 Class List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 File Index 7
4.1 File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Namespace Documentation 9
5.1 ParametricDramDirectoryMSI Namespace Reference . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.2 Typedef Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2.1 CacheCntlrMap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2.2 CacheDirectoryWaiterMap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2.3 CoreComponentType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2.4 Mshr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.3 Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.3.1 CStateString() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.3.2 make_mshr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.3.3 ReasonString() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ii CONTENTS
6 Class Documentation 13
6.1 ATD Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.1 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1.1 ATD() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1.2 ATD() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.2 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.2.1 access() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.2.2 isSampledSet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3.1 load_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3.2 loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.3 loads_constructive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.4 loads_destructive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.5 m_cache_base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.6 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.7 m_sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.8 store_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.9 stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3.10 stores_constructive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.3.11 stores_destructive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Cache Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.1.1 Cache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2.1.2 Cache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.2.1 accessSingleLine() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.2.2 disable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.2.3 enable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.2.4 getSetLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.2.5 insertSingleLine() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Generated by Doxygen
CONTENTS iii
6.2.2.6 invalidateSingleLine() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.2.7 peekBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2.2.8 peekSingleLine() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.2.9 updateCounters() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2.10 updateHits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.3.1 m_cache_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.3.2 m_enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.3.3 m_fault_injector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3.4 m_num_accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3.5 m_num_hits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3.6 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3.7 m_sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 CacheBase Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Member Enumeration Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.2.1 access_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.2.2 cache_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2.3 hash_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2.4 ReplacementPolicy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.3.1 CacheBase() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.3.2 CacheBase() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.4.1 getAssociativity() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.4.2 getName() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.4.3 getNumSets() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.4.4 parseAddressHash() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.4.5 splitAddress() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3.4.6 splitAddress() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
iv CONTENTS
6.3.4.7 tagToAddress() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5.1 m_ahl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5.2 m_associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5.3 m_blocksize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5.4 m_cache_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.5.5 m_hash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.5.6 m_log_blocksize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.5.7 m_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.5.8 m_num_sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 CacheBlockInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4.1 Member Typedef Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.1.1 BitsUsedType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2.1 option_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.3.1 CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3.2 CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.4.1 clearOption() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.4.2 clone() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4.4.3 create() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4.4.4 getCState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.4.5 getOptionName() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.4.6 getOwner() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.4.7 getTag() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.4.4.8 getUsage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.4.4.9 hasOption() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.4.4.10 invalidate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.4.4.11 isValid() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CONTENTS v
6.4.4.12 setCState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4.4.13 setOption() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4.4.14 setOwner() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4.4.15 setTag() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4.4.16 updateUsage() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4.4.17 updateUsage() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4.5.1 BitsUsedOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4.5.2 m_cstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4.5.3 m_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4.5.4 m_owner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4.5.5 m_tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4.5.6 m_used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4.5.7 option_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5 CacheCntlr Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5.1.1 incrementQBSLookupCost() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.1.2 isInLowerLevelCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6 ParametricDramDirectoryMSI::CacheCntlr Class Reference . . . . . . . . . . . . . . . . . . . . . 51
6.6.1.1 CacheCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.6.1.2 CacheCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.6.2.1 __walkUsageBits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.6.2.2 accessCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.6.2.3 accessDRAM() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.6.2.4 acquireLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.6.2.5 acquireStackLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.6.2.6 cleanupMshr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.6.2.7 copyDataFromNextLevel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
vi CONTENTS
6.6.2.8 createSetLocks() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.6.2.9 disable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.6.2.10 doPrefetch() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.6.2.11 enable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.6.2.12 getCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.6.2.13 getCacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.6.2.14 getCacheBlockSize() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.6.2.15 getCacheState() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.6.2.16 getCacheState() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.6.2.17 getHome() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.6.2.18 getLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.2.19 getMemoryManager() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.2.20 getNetworkThreadSemaphore() . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.2.21 getShmemPerfModel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6.2.22 getUserThreadSemaphore() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6.2.23 handleMsgFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6.2.24 incrementQBSLookupCost() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.6.2.25 initiateDirectoryAccess() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.6.2.26 insertCacheBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.6.2.27 invalidateCacheBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.6.2.28 isFirstLevel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.6.2.29 isInLowerLevelCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.6.2.30 isLastLevel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.6.2.31 isMasterCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.6.2.32 isShared() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.6.2.33 lastLevelCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.6.2.34 notifyPrevLevelEvict() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.6.2.35 notifyPrevLevelInsert() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6.2.36 operationPermissibleinCache() . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6.2.37 Prefetch() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
CONTENTS vii
6.6.2.38 processExRepFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . . . 77
6.6.2.39 processExReqToDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.6.2.40 processFlushReqFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . 79
6.6.2.41 processInvReqFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . . 79
6.6.2.42 processMemOpFromCore() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.6.2.43 processShmemReqFromPrevCache() . . . . . . . . . . . . . . . . . . . . . . . 82
6.6.2.44 processShRepFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.2.45 processShReqToDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.6.2.46 processUpgradeRepFromDramDirectory() . . . . . . . . . . . . . . . . . . . . 84
6.6.2.47 processUpgradeReqToDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.6.2.48 processWbReqFromDramDirectory() . . . . . . . . . . . . . . . . . . . . . . . 85
6.6.2.49 releaseLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6.2.50 releaseStackLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.6.2.51 retrieveCacheBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.6.2.52 setCacheState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.6.2.53 setDRAMDirectAccess() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6.2.54 setNextCacheCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6.2.55 setPrevCacheCntlrs() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6.2.56 trainPrefetcher() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.2.57 transition() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.2.58 updateCacheBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2.59 updateCounters() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2.60 updateHits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6.2.61 updateUncoreStatistics() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6.2.62 updateUsageBits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6.2.63 waitForNetworkThread() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6.2.64 waitForUserThread() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.6.2.65 wakeUpNetworkThread() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.6.2.66 wakeUpUserThread() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.6.2.67 walkUsageBits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
viii CONTENTS
6.6.2.68 writeCacheBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.6.3 Friends And Related Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.3.1 CacheCntlrList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.3.2 MemoryManager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.4.1 backinval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.4.2 coherency_downgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.4.3 coherency_invalidates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.6.4.4 coherency_upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.5 coherency_writebacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.6 evict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.7 evict_prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.8 evict_warmup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.9 hits_prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.10 hits_warmup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.11 invalidate_prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6.4.12 invalidate_warmup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.13 load_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.14 load_misses_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.15 load_overlapping_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.16 loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.17 loads_prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.18 loads_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.6.4.19 loads_where . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.20 m_cache_block_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.21 m_cache_writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.22 m_coherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.23 m_core_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.24 m_core_id_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.25 m_l1_mshr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
CONTENTS ix
6.6.4.26 m_last_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.6.4.27 m_last_remote_hit_where . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.28 m_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.29 m_mem_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.30 m_memory_manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.31 m_network_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.32 m_next_cache_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.33 m_next_level_read_bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6.4.34 m_passthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.35 m_perfect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.36 m_prefetch_on_prefetch_hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.37 m_shared_cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.38 m_shmem_perf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.39 m_shmem_perf_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.40 m_shmem_perf_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.41 m_shmem_perf_numrequests . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.6.4.42 m_shmem_perf_totaltime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.43 m_shmem_req_source_map . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.44 m_tag_directory_home_lookup . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.45 m_user_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.46 m_writeback_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.47 mshr_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.48 prefetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.6.4.49 qbs_query_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.50 snoop_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.51 stats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.52 store_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.53 store_misses_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.54 store_overlapping_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.4.55 stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
x CONTENTS
6.6.4.56 stores_prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.6.4.57 stores_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.6.4.58 stores_where . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.6.4.59 total_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.7 ParametricDramDirectoryMSI::CacheCntlrList Class Reference . . . . . . . . . . . . . . . . . . . 104
6.8 ParametricDramDirectoryMSI::CacheDirectoryWaiter Class Reference . . . . . . . . . . . . . . . 105
6.8.1.1 CacheDirectoryWaiter() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8.2.1 cache_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8.2.2 exclusive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8.2.3 isPrefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8.2.4 t_issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.9 ParametricDramDirectoryMSI::CacheMasterCntlr Class Reference . . . . . . . . . . . . . . . . . 108
6.9.1.1 CacheMasterCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.1.2 CacheMasterCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.2.1 accessATDs() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.9.2.2 createATDs() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.9.2.3 createSetLocks() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.9.2.4 getSetLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.9.3 Friends And Related Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . 111
6.9.3.1 CacheCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.9.4.1 m_atds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.2 m_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.3 m_cache_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.4 m_directory_waiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.5 m_dram_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
CONTENTS xi
6.9.4.6 m_dram_outstanding_writebacks . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.7 m_evicting_address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.9.4.8 m_evicting_buf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.9 m_l1_mshr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.10 m_log_blocksize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.11 m_next_level_read_bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.12 m_num_sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.13 m_prefetch_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.14 m_prefetch_next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.9.4.15 m_prefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.9.4.16 m_prev_cache_cntlrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.9.4.17 m_setlocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.9.4.18 m_smt_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.9.4.19 mshr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.10 ParametricDramDirectoryMSI::CacheParameters Class Reference . . . . . . . . . . . . . . . . . 115
6.10.1.1 CacheParameters() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.10.1.2 CacheParameters() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.10.2.1 associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.10.2.2 coherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.3 configName . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.4 data_access_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.5 hash_function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.6 next_level_read_bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.7 num_sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.8 outstanding_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10.2.9 perf_model_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.10 perfect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.11 prefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
xii CONTENTS
6.10.2.12 replacement_policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.13 shared_cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.14 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.15 tags_access_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.16 writeback_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10.2.17 writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.11 CacheSet Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.11.2.1 ew_access_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.11.3.1 CacheSet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.11.3.2 CacheSet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.11.4.1 createCacheSet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.11.4.2 createCacheSetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.11.4.3 find() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.11.4.4 getAssociativity() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.11.4.5 getBlockSize() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.11.4.6 getBlockSize() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.11.4.7 getDataPtr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.11.4.8 getLock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.11.4.9 getNumQBSAttempts() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.11.4.10 getReplacementIndex() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.11.4.11 insert() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.11.4.12 invalidate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.11.4.13 isValidReplacement() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.11.4.14 parsePolicyType() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.11.4.15 peekBlock() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.11.4.16 read_line() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CONTENTS xiii
6.11.4.17 updateReplacementIndex() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.11.4.18 write_line() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.11.5.1 m_associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.11.5.2 m_block_op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.11.5.3 m_blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.11.5.4 m_blocksize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.11.5.5 m_cache_block_info_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.11.5.6 m_coming_EW_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.11.5.7 m_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.12 CacheSetEWLRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.12.2.1 CacheSetEWLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.12.2.2 CacheSetEWLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.12.3.1 evictEW() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.12.3.3 moveToMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.12.3.4 updateEW() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.12.4.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.12.4.2 m_lru_R_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.12.4.3 m_lru_RW_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.12.4.4 m_lru_W_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.12.4.5 m_num_attempts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.12.4.6 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.12.4.7 m_stored_EW_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.13 CacheSetEWSRRIP Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
xiv CONTENTS
6.13.2.1 CacheSetEWSRRIP() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.13.2.2 CacheSetEWSRRIP() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.13.3.1 evictEW() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.13.3.3 updateEW() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.13.4.1 m_num_attempts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.13.4.2 m_replacement_pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.13.4.3 m_rrip_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.4 m_rrip_flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.5 m_rrip_insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.6 m_rrip_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.7 m_rrip_numbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.8 m_rrip_R_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.9 m_rrip_RW_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.13.4.10 m_rrip_W_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.13.4.11 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.14 CacheSetInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.14.1.1 CacheSetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.15 CacheSetInfoLRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.15.1.1 CacheSetInfoLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.15.1.2 CacheSetInfoLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.15.2.1 increment() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
CONTENTS xv
6.15.2.2 incrementAttempt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.15.3.1 m_access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.15.3.2 m_associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.15.3.3 m_attempts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.16 CacheSetLRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.16.1.1 CacheSetLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.16.1.2 CacheSetLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.16.2.2 moveToMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.16.3.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.16.3.2 m_num_attempts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.16.3.3 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.17 CacheSetMRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.17.1.1 CacheSetMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.17.1.2 CacheSetMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.17.3.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.18 CacheSetMRUT Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.18.2.1 CacheSetMRUT() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
xvi CONTENTS
6.18.2.2 CacheSetMRUT() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.18.3.2 updateReplacementForFetchedIndex() . . . . . . . . . . . . . . . . . . . . . . 168
6.18.4.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.18.4.2 m_mru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.18.4.3 m_rand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.19 CacheSetNMRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.19.1.1 CacheSetNMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.19.1.2 CacheSetNMRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.19.3.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.20 CacheSetNRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.20.1.1 CacheSetNRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.20.1.2 CacheSetNRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.20.3.1 m_lru_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.20.3.2 m_num_bits_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
CONTENTS xvii
6.21 CacheSetPLRU Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.21.1.1 CacheSetPLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.21.1.2 CacheSetPLRU() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.21.3.1 b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.22 CacheSetRandom Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.22.1.1 CacheSetRandom() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.22.1.2 CacheSetRandom() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.22.3.1 m_rand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.23 CacheSetRoundRobin Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.23.1.1 CacheSetRoundRobin() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.23.1.2 CacheSetRoundRobin() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.23.3.1 m_replacement_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.24 CacheSetSRRIP Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.24.1.1 CacheSetSRRIP() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
xviii CONTENTS
6.24.1.2 CacheSetSRRIP() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.24.3.1 m_num_attempts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.24.3.3 m_rrip_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.24.3.4 m_rrip_insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.24.3.5 m_rrip_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.24.3.6 m_rrip_numbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.24.3.7 m_set_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.25 CacheState Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.25.1.1 cstate_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.25.2.1 CacheState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.25.2.2 CacheState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.25.3.1 readable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.25.3.2 writable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.25.4.1 cstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.26 CacheSetEWLRU::ew_array Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.26.2.1 was_read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.26.2.2 was_written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.27 GhbPrefetcher::GHBEntry Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
CONTENTS xix
6.27.1.1 GHBEntry() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.27.2.1 delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.27.2.2 generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.27.2.3 nextIndex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.28 GhbPrefetcher Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.28.1.1 GhbPrefetcher() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.28.1.2 GhbPrefetcher() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.28.2.1 getNextAddress() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.28.3.1 INVALID_DELTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.2 INVALID_INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.3 m_generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.4 m_ghb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.5 m_ghbHead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.6 m_ghbSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.7 m_ghbTable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.8 m_lastAddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.28.3.9 m_prefetchDepth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.28.3.10 m_prefetchWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.28.3.11 m_tableHead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.28.3.12 m_tableSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.29 ParametricDramDirectoryMSI::MemoryManager Class Reference . . . . . . . . . . . . . . . . . . 204
6.29.1.1 MemoryManager() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.29.1.2 MemoryManager() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.29.2.1 accessTLB() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
xx CONTENTS
6.29.2.2 addL1Hits() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.29.2.3 broadcastMsg() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.29.2.4 coreInitiateMemoryAccess() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.29.2.5 disableModels() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.29.2.6 enableModels() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.29.2.7 getCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.29.2.8 getCacheBlockSize() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.29.2.9 getCacheCntlrAt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.29.2.10 getCost() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.29.2.11 getDramCntlr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.29.2.12 getDramControllerHomeLookup() . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.29.2.13 getDramDirectoryCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.29.2.14 getL1DCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.29.2.15 getL1HitLatency() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.29.2.16 getL1ICache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.29.2.17 getLastLevelCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.29.2.18 getModeledLength() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.29.2.19 getShmemRequester() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.29.2.20 getTagDirectoryHomeLookup() . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.29.2.21 handleMsgFromNetwork() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.29.2.22 incrElapsedTime() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.29.2.23 incrElapsedTime() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.29.2.24 sendMsg() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.29.2.25 setCacheCntlrAt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.29.3.1 m_all_cache_cntlrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.29.3.3 m_cache_cntlrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.29.3.4 m_cache_perf_models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.29.3.5 m_core_id_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
CONTENTS xxi
6.29.3.6 m_dram_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.29.3.7 m_dram_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.29.3.8 m_dram_cntlr_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.9 m_dram_controller_home_lookup . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.10 m_dram_directory_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.11 m_dtlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.12 m_enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.13 m_itlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.14 m_last_level_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.29.3.15 m_network_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.16 m_nuca_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.17 m_stlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.18 m_tag_directory_home_lookup . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.19 m_tag_directory_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.20 m_tlb_miss_parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.21 m_tlb_miss_penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.29.3.22 m_user_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.30 ParametricDramDirectoryMSI::MshrEntry Struct Reference . . . . . . . . . . . . . . . . . . . . . 225
6.30.1.1 t_complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.30.1.2 t_issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.31 NucaCache Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.31.1.1 NucaCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.31.1.2 NucaCache() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.31.2.1 accessDataArray() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.31.2.2 read() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.31.2.3 write() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
xxii CONTENTS
6.31.3.1 m_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.31.3.3 m_core_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.31.3.4 m_data_access_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.5 m_data_array_bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.6 m_home_lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.7 m_memory_manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.8 m_queue_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.9 m_read_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.10 m_reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.11 m_shmem_perf_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.31.3.12 m_tags_access_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.31.3.13 m_write_misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.31.3.14 m_writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.32 ParametricDramDirectoryMSI::Prefetch Class Reference . . . . . . . . . . . . . . . . . . . . . . . 232
6.32.1.1 prefetch_type_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.33 Prefetcher Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.33.1.1 createPrefetcher() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.33.1.2 getNextAddress() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.34 PrL1CacheBlockInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.34.1.1 PrL1CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.34.1.2 PrL1CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.35 PrL2CacheBlockInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.35.1.1 PrL2CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
6.35.1.2 PrL2CacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
CONTENTS xxiii
6.35.2.1 clearCachedLoc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
6.35.2.2 clone() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
6.35.2.3 getCachedLoc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.35.2.4 getCachedLocBitVec() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.35.2.5 invalidate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.35.2.6 setCachedLoc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.35.3.1 m_cached_loc_bitvec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.36 ReqQueueListTemplate< T_Req > Class Template Reference . . . . . . . . . . . . . . . . . . . 245
6.36.1.1 ReqQueueListTemplate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.36.1.2 ReqQueueListTemplate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.36.2.1 back() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.36.2.2 dequeue() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.36.2.3 empty() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.36.2.4 enqueue() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.36.2.5 front() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.36.2.6 size() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.36.3.1 m_req_queue_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.37 SharedCacheBlockInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.37.1.1 SharedCacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.37.1.2 SharedCacheBlockInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.37.2.1 clone() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.37.2.2 invalidate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.38 SimplePrefetcher Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
xxiv CONTENTS
6.38.1.1 SimplePrefetcher() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.2.1 getNextAddress() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.3.1 core_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.3.2 flows_per_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.3.3 m_prev_address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.3.4 n_flow_next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.38.3.5 n_flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.38.3.6 num_prefetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.38.3.7 shared_cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.38.3.8 stop_at_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.39 GhbPrefetcher::TableEntry Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.39.1.1 TableEntry() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.39.2.1 delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.39.2.2 generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.39.2.3 ghbIndex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.40 ParametricDramDirectoryMSI::TLB Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.40.1.1 TLB() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.40.2.1 allocate() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.40.2.2 lookup() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.40.3.1 m_access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.2 m_associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.3 m_cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.4 m_miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.5 m_next_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.6 m_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.7 SIM_PAGE_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.40.3.8 SIM_PAGE_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.40.3.9 SIM_PAGE_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.41 ParametricDramDirectoryMSI::Transition Class Reference . . . . . . . . . . . . . . . . . . . . . . 263
6.41.1.1 reason_t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
CONTENTS xxv
7 File Documentation 265
7.1 cache.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
7.2 cache.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
7.2.1 Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
7.2.1.1 moduloHashFn() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.3 cache_atd.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.4 cache_atd.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.5 cache_base.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
7.6 cache_base.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
7.6.1 Macro Definition Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.6.1.1 k_GIGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.6.1.2 k_KILO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.6.1.3 k_MEGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.7 cache_block_info.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.8 cache_block_info.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.9 cache_cntlr.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.9.1.1 MYLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.9.2 Variable Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.9.2.1 iolock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.10 cache_cntlr.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
7.10.1.1 PREFETCH_INTERVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
7.10.1.2 PREFETCH_MAX_QUEUE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . 274
7.11 cache_set.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
7.12 cache_set.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.13 cache_set_ew_lru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.14 cache_set_ew_lru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.15 cache_set_ew_srrip.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
7.16 cache_set_ew_srrip.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
xxvi CONTENTS
7.17 cache_set_lru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

7.18 cache_set_lru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.19 cache_set_mru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.20 cache_set_mru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.21 cache_set_mrut.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.22 cache_set_mrut.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.23 cache_set_nmru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.24 cache_set_nmru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.25 cache_set_nru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.26 cache_set_nru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.27 cache_set_plru.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.28 cache_set_plru.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
7.29 cache_set_random.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
7.30 cache_set_random.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.31 cache_set_round_robin.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.32 cache_set_round_robin.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.33 cache_set_srrip.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.34 cache_set_srrip.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.35 cache_state.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.36 ghb_prefetcher.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.37 ghb_prefetcher.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
7.38 memory_manager.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
7.38.1.1 MYLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
7.39 memory_manager.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
7.40 nuca_cache.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
7.41 nuca_cache.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
7.42 pr_l1_cache_block_info.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
7.43 pr_l2_cache_block_info.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.44 pr_l2_cache_block_info.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
7.45 prefetcher.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.46 prefetcher.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.47 req_queue_list_template.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
7.48 shared_cache_block_info.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
7.49 shared_cache_block_info.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
7.50 simple_prefetcher.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
7.50.1 Variable Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
7.50.1.1 PAGE_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
7.50.1.2 PAGE_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
7.51 simple_prefetcher.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
7.52 tlb.cc File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
7.53 tlb.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Chapter 1
Namespace Index
1.1 Namespace List
Here is a list of all namespaces with brief descriptions:
ParametricDramDirectoryMSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Namespace Index
Chapter 2
Hierarchical Index
2.1 Class Hierarchy
This inheritance list is sorted roughly, but not completely, alphabetically:
ATD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CacheBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CacheBlockInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PrL1CacheBlockInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SharedCacheBlockInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
CacheCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ParametricDramDirectoryMSI::CacheCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ParametricDramDirectoryMSI::CacheDirectoryWaiter . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ParametricDramDirectoryMSI::CacheMasterCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ParametricDramDirectoryMSI::CacheParameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CacheSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CacheSetEWLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CacheSetEWSRRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CacheSetLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CacheSetMRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
CacheSetMRUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
CacheSetNMRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
CacheSetNRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
CacheSetPLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CacheSetRandom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
CacheSetRoundRobin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
CacheSetSRRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CacheSetInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CacheSetInfoLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
CacheState . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CacheSetEWLRU::ew_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
GhbPrefetcher::GHBEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MemoryManagerBase
ParametricDramDirectoryMSI::MemoryManager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ParametricDramDirectoryMSI::MshrEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
NucaCache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ParametricDramDirectoryMSI::Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
4 Hierarchical Index
Prefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
GhbPrefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
SimplePrefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
ReqQueueListTemplate< T_Req > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
ReqQueueListTemplate< CacheDirectoryWaiter > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
GhbPrefetcher::TableEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
ParametricDramDirectoryMSI::TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
ParametricDramDirectoryMSI::Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
vector
ParametricDramDirectoryMSI::CacheCntlrList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 3
Class Index
3.1 Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
ATD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CacheBase
Cache_Base class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CacheBlockInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CacheCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ParametricDramDirectoryMSI::CacheCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ParametricDramDirectoryMSI::CacheCntlrList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ParametricDramDirectoryMSI::CacheDirectoryWaiter . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ParametricDramDirectoryMSI::CacheMasterCntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ParametricDramDirectoryMSI::CacheParameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CacheSet
Cache_Set class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CacheSetEWLRU
EW-LRU: Evict Write strategy for Least Recently Used cache replacement policy . . . . . . . 132
CacheSetEWSRRIP
EW-S-RRIP: Evict Write strategy for Static Re-reference Interval Prediction cache replacement
policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CacheSetInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CacheSetInfoLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
CacheSetLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CacheSetMRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
CacheSetMRUT
MRU-T: Most Recently Used - Tour cache replacement policy . . . . . . . . . . . . . . . . . . 163
CacheSetNMRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
CacheSetNRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
CacheSetPLRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CacheSetRandom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
CacheSetRoundRobin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
CacheSetSRRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CacheState . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CacheSetEWLRU::ew_array
A public struct variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
GhbPrefetcher::GHBEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
GhbPrefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6 Class Index
ParametricDramDirectoryMSI::MemoryManager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ParametricDramDirectoryMSI::MshrEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
NucaCache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ParametricDramDirectoryMSI::Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Prefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
ReqQueueListTemplate< T_Req > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
SharedCacheBlockInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SimplePrefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
GhbPrefetcher::TableEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
ParametricDramDirectoryMSI::TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
ParametricDramDirectoryMSI::Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Chapter 4
File Index
4.1 File List
Here is a list of all files with brief descriptions:
cache.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
cache.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
cache_atd.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
cache_atd.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
cache_base.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
cache_base.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
cache_block_info.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
cache_block_info.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
cache_cntlr.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
cache_cntlr.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
cache_set.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
cache_set.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
cache_set_ew_lru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
cache_set_ew_lru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
cache_set_ew_srrip.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
cache_set_ew_srrip.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
cache_set_lru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
cache_set_lru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
cache_set_mru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
cache_set_mru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
cache_set_mrut.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
cache_set_mrut.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
cache_set_nmru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
cache_set_nmru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
cache_set_nru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
cache_set_nru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
cache_set_plru.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
cache_set_plru.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
cache_set_random.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
cache_set_random.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
cache_set_round_robin.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
cache_set_round_robin.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
cache_set_srrip.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
cache_set_srrip.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
cache_state.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
8 File Index
ghb_prefetcher.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
ghb_prefetcher.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
memory_manager.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
memory_manager.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
nuca_cache.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
nuca_cache.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
pr_l1_cache_block_info.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
pr_l2_cache_block_info.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
pr_l2_cache_block_info.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
prefetcher.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
prefetcher.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
req_queue_list_template.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
shared_cache_block_info.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
shared_cache_block_info.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
simple_prefetcher.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
simple_prefetcher.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
tlb.cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
tlb.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Chapter 5
Namespace Documentation
5.1 ParametricDramDirectoryMSI Namespace Reference
Classes
class CacheCntlr
class CacheCntlrList
class CacheDirectoryWaiter
class CacheMasterCntlr
class CacheParameters
class MemoryManager
struct MshrEntry
class Prefetch
class TLB
class Transition
Typedefs
typedef ReqQueueListTemplate< CacheDirectoryWaiter > CacheDirectoryWaiterMap

typedef std::unordered_map< IntPtr, MshrEntry > Mshr
typedef std::pair< core_id_t, MemComponent::component_t > CoreComponentType
typedef std::map< CoreComponentType, CacheCntlr > CacheCntlrMap
Functions
char CStateString (CacheState::cstate_t cstate)

const char ReasonString (Transition::reason_t reason)
MshrEntry make_mshr (SubsecondTime t_issue, SubsecondTime t_complete)
5.1.1 Detailed Description
Cache_cntlr class is the main class for all cache information and operations
10 Namespace Documentation
5.1.2 Typedef Documentation
5.1.2.1 CacheCntlrMap
typedef std::map<CoreComponentType, CacheCntlr> ParametricDramDirectoryMSI::CacheCntlrMap
5.1.2.2 CacheDirectoryWaiterMap
typedef ReqQueueListTemplate<CacheDirectoryWaiter> ParametricDramDirectoryMSI::CacheDirectory-

WaiterMap
5.1.2.3 CoreComponentType
typedef std::pair<core_id_t, MemComponent::component_t> ParametricDramDirectoryMSI::Core-

ComponentType
5.1.2.4 Mshr
typedef std::unordered_map<IntPtr, MshrEntry> ParametricDramDirectoryMSI::Mshr
5.1.3 Function Documentation
5.1.3.1 CStateString()
char ParametricDramDirectoryMSI::CStateString (
CacheState::cstate_t cstate )
Here is the caller graph for this function:
ParametricDramDirectoryMSI
::CacheCntlr::processUpgradeRep
FromDramDirectory
ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::CacheCntlr ::CacheCntlr::processInvReqFrom
DramDirectory
::CacheCntlr::processWbReqFromDram
Directory
ParametricDramDirectoryMSI ::CacheCntlr::processFlushReqFrom ::CacheCntlr::handleMsgFromDram
::CacheCntlr::updateCacheBlock DramDirectory Directory
::CStateString
::CacheCntlr::processShRepFromDram
Directory
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::MemoryManager::handleMsgFromNetwork
::CacheCntlr::notifyPrevLevelEvict ::CacheCntlr::invalidateCacheBlock ParametricDramDirectoryMSI
::CacheCntlr::processExRepFromDram
Directory
::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
::CacheCntlr::insertCacheBlock Access
::CacheCntlr::copyDataFromNextLevel
::CacheCntlr::processMemOpFromCore
::CacheCntlr::processShmemReqFrom
PrevCache
::CacheCntlr::operationPermissibleinCache
::CacheCntlr::trainPrefetcher ::CacheCntlr::doPrefetch
::CacheCntlr::Prefetch
5.1 ParametricDramDirectoryMSI Namespace Reference 11
5.1.3.2 make_mshr()
MshrEntry ParametricDramDirectoryMSI::make_mshr (
SubsecondTime t_issue,
SubsecondTime t_complete )
::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ::MemoryManager::coreInitiateMemory
PrevCache ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore
ParametricDramDirectoryMSI Access
::make_mshr ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
::CacheCntlr::handleMsgFromDram
::MemoryManager::handleMsgFromNetwork
Directory
5.1.3.3 ReasonString()
const char ParametricDramDirectoryMSI::ReasonString (

Transition::reason_t reason )
::ReasonString ::CacheCntlr::CacheCntlr
12 Namespace Documentation
Chapter 6
Class Documentation
6.1 ATD Class Reference
#include <cache_atd.h>
14 Class Documentation
Collaboration diagram for ATD:
CacheBase
# m_name
# m_cache_size
# m_associativity
# m_blocksize
# m_hash
# m_num_sets
CacheSetInfo # m_ahl
# m_log_blocksize
+ CacheBase()
+ ~CacheSetInfo()
+ ~CacheBase()
+ splitAddress()
+ splitAddress()
+ tagToAddress()
+ getName()
+ getNumSets()
+ getAssociativity()
+ parseAddressHash()
-m_set_info -m_cache_base
ATD
- m_sets
- loads
- stores
- load_misses
- store_misses
- loads_constructive
- stores_constructive
- loads_destructive
- stores_destructive
+ ATD()
+ ~ATD()
+ access()
- isSampledSet()
Public Member Functions

ATD (String name, String configName, core_id_t core_id, UInt32 num_sets, UInt32 associativity, UInt32
cache_block_size, String replacement_policy, CacheBase::hash_t hash_function)
ATD ()
void access (Core::mem_op_t mem_op_type, bool hit, IntPtr address)
Private Member Functions

bool isSampledSet (UInt32 set_index)
6.1 ATD Class Reference 15
Private Attributes
CacheBase m_cache_base
std::unordered_map< UInt32, CacheSet > m_sets
CacheSetInfo m_set_info
UInt64 loads
UInt64 stores
UInt64 load_misses
UInt64 store_misses
UInt64 loads_constructive
UInt64 stores_constructive
UInt64 loads_destructive
UInt64 stores_destructive
6.1.1 Constructor & Destructor Documentation
6.1.1.1 ATD()
ATD::ATD (
String name,
String configName,
core_id_t core_id,
UInt32 num_sets,
UInt32 associativity,
UInt32 cache_block_size,
String replacement_policy,
CacheBase::hash_t hash_function )
Here is the call graph for this function:
CacheSet::createCacheSetInfo CacheSet::parsePolicyType
ATD::ATD
CacheSet::createCacheSet CacheSet::getNumQBSAttempts
6.1.1.2 ATD()
ATD::ATD ( )
6.1.2 Member Function Documentation
6.1.2.1 access()
void ATD::access (
Core::mem_op_t mem_op_type,
bool hit,
IntPtr address )
CacheBase::splitAddress
ATD::access
ATD::isSampledSet
6.1.2.2 isSampledSet()
bool ATD::isSampledSet (
UInt32 set_index ) [private]
ATD::isSampledSet ATD::access
6.1.3 Member Data Documentation
6.1.3.1 load_misses
UInt64 ATD::load_misses [private]
6.1 ATD Class Reference 17
6.1.3.2 loads
UInt64 ATD::loads [private]
6.1.3.3 loads_constructive
UInt64 ATD::loads_constructive [private]
6.1.3.4 loads_destructive
UInt64 ATD::loads_destructive [private]
6.1.3.5 m_cache_base
CacheBase ATD::m_cache_base [private]
6.1.3.6 m_set_info
CacheSetInfo ATD::m_set_info [private]
6.1.3.7 m_sets
std::unordered_map<UInt32, CacheSet> ATD::m_sets [private]
6.1.3.8 store_misses
UInt64 ATD::store_misses [private]
6.1.3.9 stores
UInt64 ATD::stores [private]
6.1.3.10 stores_constructive
UInt64 ATD::stores_constructive [private]
6.1.3.11 stores_destructive
UInt64 ATD::stores_destructive [private]
The documentation for this class was generated from the following files:
cache_atd.h
cache_atd.cc
6.2 Cache Class Reference
#include <cache.h>
6.2 Cache Class Reference 19
Inheritance diagram for Cache:
CacheBase
# m_name
# m_cache_size
# m_associativity
# m_blocksize
# m_hash
# m_num_sets
# m_ahl
# m_log_blocksize
+ CacheBase()
+ ~CacheBase()
+ splitAddress()
+ splitAddress()
+ tagToAddress()
+ getName()
+ getNumSets()
Cache
- m_enabled
- m_num_accesses
- m_num_hits
- m_cache_type
- m_sets
- m_set_info
- m_fault_injector
+ Cache()
+ ~Cache()
+ getSetLock()
+ invalidateSingleLine()
+ accessSingleLine()
+ insertSingleLine()
+ peekSingleLine()
+ peekBlock()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
Collaboration diagram for Cache:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
CacheBase # m_associativity
# m_blocksize
# m_name
# m_lock
# m_cache_size
# m_associativity + CacheSet()
# m_blocksize + ~CacheSet()
# m_hash + getBlockSize()
# m_num_sets + getAssociativity()
# m_ahl CacheSetInfo
+ getLock()
# m_log_blocksize + read_line()
+ write_line()
+ CacheBase()
+ ~CacheSetInfo() + find()
+ ~CacheBase()
+ invalidate()
+ splitAddress()
+ insert()
+ splitAddress()
+ peekBlock()
+ tagToAddress()
+ getDataPtr()
+ getName()
+ getBlockSize()
+ getNumSets()
+ getReplacementIndex()
+ updateReplacementIndex()
+ isValidReplacement()
+ createCacheSet()
+ createCacheSetInfo()
+ parsePolicyType()
+ getNumQBSAttempts()
-m_set_info -m_sets
Cache
- m_enabled
- m_num_accesses
- m_num_hits
- m_cache_type
- m_fault_injector
+ Cache()
+ ~Cache()
+ getSetLock()
+ peekSingleLine()
+ peekBlock()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
Cache (String name, String cfgname, core_id_t core_id, UInt32 num_sets, UInt32 associativity, UInt32
cache_block_size, String replacement_policy, cache_t cache_type, hash_t hash=CacheBase::HASH_MASK,
FaultInjector fault_injector=NULL, AddressHomeLookup ahl=NULL)
A test class.
Cache ()
Lock & getSetLock (IntPtr addr)

bool invalidateSingleLine (IntPtr addr)
CacheBlockInfo accessSingleLine (IntPtr addr, access_t access_type, Byte buff, UInt32 bytes,
SubsecondTime now, bool update_replacement)
void insertSingleLine (IntPtr addr, Byte fill_buff, bool eviction, IntPtr evict_addr, CacheBlockInfo evict_-
block_info, Byte evict_buff, SubsecondTime now, CacheCntlr cntlr=NULL)
CacheBlockInfo peekSingleLine (IntPtr addr)
CacheBlockInfo peekBlock (UInt32 set_index, UInt32 way) const
void updateCounters (bool cache_hit)
void updateHits (Core::mem_op_t mem_op_type, UInt64 hits)
void enable ()
void disable ()
Private Attributes
bool m_enabled
UInt64 m_num_accesses
UInt64 m_num_hits
cache_t m_cache_type
CacheSet m_sets
CacheSetInfo m_set_info
FaultInjector m_fault_injector
Additional Inherited Members
6.2.1.1 Cache()
Cache::Cache (
String name,
String cfgname,
core_id_t core_id,
UInt32 num_sets,
cache_t cache_type,
hash_t hash = CacheBase::HASH_MASK,
FaultInjector fault_injector = NULL,
AddressHomeLookup ahl = NULL )
A test class.
A more elaborate class description. Here is the call graph for this function:
CacheSet::createCacheSetInfo CacheSet::parsePolicyType
Cache::Cache
CacheSet::createCacheSet CacheSet::getNumQBSAttempts
6.2.1.2 Cache()
Cache::Cache ( )
6.2.2.1 accessSingleLine()
CacheBlockInfo Cache::accessSingleLine (
IntPtr addr,
access_t access_type,
Byte buff,
UInt32 bytes,
SubsecondTime now,
bool update_replacement )
Cache::accessSingleLine CacheBase::splitAddress
::TLB::lookup ::MemoryManager::accessTLB
::CacheCntlr::accessCache
::CacheCntlr::copyDataFromNextLevel Access
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI

::CacheCntlr::writeCacheBlock ParametricDramDirectoryMSI
::CacheCntlr::insertCacheBlock ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Cache::accessSingleLine ::CacheCntlr::processShmemReqFrom ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
PrevCache
::CacheCntlr::retrieveCacheBlock ::CacheCntlr::processShRepFromDram
Directory
NucaCache::read
NucaCache::write ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::MemoryManager::handleMsgFromNetwork
Directory
::CacheCntlr::processInvReqFrom ::CacheCntlr::handleMsgFromDram
::CacheCntlr::updateCacheBlock
DramDirectory Directory
::CacheCntlr::processFlushReqFrom
DramDirectory
Directory
FromDramDirectory
6.2.2.2 disable()
void Cache::disable ( ) [inline]
Cache::disable
::CacheCntlr::disable
6.2.2.3 enable()
void Cache::enable ( ) [inline]
Cache::enable
::CacheCntlr::enable
6.2.2.4 getSetLock()
Lock & Cache::getSetLock (

IntPtr addr )
Cache::getSetLock
CacheSet::getLock
6.2.2.5 insertSingleLine()
void Cache::insertSingleLine (
IntPtr addr,
Byte fill_buff,
bool eviction,
IntPtr evict_addr,
CacheBlockInfo evict_block_info,
Byte evict_buff,
SubsecondTime now,
CacheCntlr cntlr = NULL )
CacheBlockInfo::create
CacheSet::getReplacement
CacheBlockInfo::setTag Index
Cache::insertSingleLine CacheSet::insert CacheBlockInfo::clone CacheBlockInfo::getCState
CacheBlockInfo::getTag
CacheBase::tagToAddress
CacheSet::find
::TLB::lookup ParametricDramDirectoryMSI
::MemoryManager::accessTLB
ParametricDramDirectoryMSI ::CacheCntlr::processShRepFromDram
::TLB::allocate Directory
ParametricDramDirectoryMSI Directory
::CacheCntlr::processExRepFromDram ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory ParametricDramDirectoryMSI
Cache::insertSingleLine
NucaCache::write
ParametricDramDirectoryMSI ::CacheCntlr::processMemOpFromCore
PrevCache
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI
6.2.2.6 invalidateSingleLine()
bool Cache::invalidateSingleLine (
IntPtr addr )
Cache::invalidateSingleLine
CacheSet::invalidate CacheBlockInfo::invalidate
::CacheCntlr::invalidateCacheBlock
ParametricDramDirectoryMSI ::CacheCntlr::processShmemReqFrom
::CacheCntlr::copyDataFromNextLevel PrevCache ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore ::MemoryManager::coreInitiateMemory
Access ParametricDramDirectoryMSI ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
FromDramDirectory
::CacheCntlr::processInvReqFrom ::CacheCntlr::handleMsgFromDram ::MemoryManager::handleMsgFromNetwork
DramDirectory
Directory
6.2.2.7 peekBlock()
CacheBlockInfo Cache::peekBlock (
UInt32 set_index,
UInt32 way ) const [inline]
CacheSet::peekBlock
Cache::peekBlock Cache::updateCounters
Cache::updateHits
Cache::peekBlock
::CacheCntlr::walkUsageBits
6.2.2.8 peekSingleLine()
CacheBlockInfo Cache::peekSingleLine (
IntPtr addr )
Cache::peekSingleLine
CacheSet::find
::CacheCntlr::updateUsageBits
::CacheCntlr::operationPermissibleinCache ParametricDramDirectoryMSI
::CacheCntlr::trainPrefetcher
::CacheCntlr::getCacheBlockInfo
::CacheCntlr::setCacheState ::CacheCntlr::notifyPrevLevelInsert ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch
Cache::peekSingleLine NucaCache::read
::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI
PrevCache ::MemoryManager::coreInitiateMemory
NucaCache::write Access
::CacheCntlr::insertCacheBlock
Directory
::CacheCntlr::notifyPrevLevelEvict ParametricDramDirectoryMSI ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI Directory
::CacheCntlr::processUpgradeReq ::CacheCntlr::initiateDirectory
ToDirectory Access
::CacheCntlr::processExReqToDirectory
::CacheCntlr::getCacheState
::CacheCntlr::processFlushReqFrom ParametricDramDirectoryMSI
DramDirectory ::MemoryManager::handleMsgFromNetwork
Directory
FromDramDirectory
::CacheCntlr::processInvReqFrom
DramDirectory
Directory
6.2.2.9 updateCounters()
void Cache::updateCounters (
bool cache_hit )
Cache::peekBlock ::CacheCntlr::walkUsageBits
Cache::updateCounters
::CacheCntlr::updateHits ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::MemoryManager::coreInitiateMemory
::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
PrevCache
6.2.2.10 updateHits()
void Cache::updateHits (
UInt64 hits )
Cache::updateHits Cache::peekBlock
6.2.3.1 m_cache_type
cache_t Cache::m_cache_type [private]
6.2.3.2 m_enabled
bool Cache::m_enabled [private]
6.2.3.3 m_fault_injector
FaultInjector Cache::m_fault_injector [private]
6.2.3.4 m_num_accesses
UInt64 Cache::m_num_accesses [private]
6.2.3.5 m_num_hits
UInt64 Cache::m_num_hits [private]
6.2.3.6 m_set_info
CacheSetInfo Cache::m_set_info [private]
6.2.3.7 m_sets
CacheSet Cache::m_sets [private]
cache.h
cache.cc
6.3 CacheBase Class Reference 29
6.3 CacheBase Class Reference
Cache_Base class.
#include <cache_base.h>
Inheritance diagram for CacheBase:
CacheBase
# m_name
# m_cache_size
# m_associativity
# m_blocksize
# m_hash
# m_num_sets
# m_ahl
# m_log_blocksize
+ CacheBase()
+ ~CacheBase()
+ splitAddress()
+ splitAddress()
+ tagToAddress()
+ getName()
+ getNumSets()
Cache
- m_enabled
- m_num_accesses
- m_num_hits
- m_cache_type
- m_sets
- m_set_info
- m_fault_injector
+ Cache()
+ ~Cache()
+ getSetLock()
+ peekSingleLine()
+ peekBlock()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
Collaboration diagram for CacheBase:
CacheBase
# m_name
# m_cache_size
# m_associativity
# m_blocksize
# m_hash
# m_num_sets
# m_ahl
# m_log_blocksize
+ CacheBase()
+ ~CacheBase()
+ splitAddress()
+ splitAddress()
+ tagToAddress()
+ getName()
+ getNumSets()
Public Types
enum access_t {
INVALID_ACCESS_TYPE, MIN_ACCESS_TYPE, LOAD = MIN_ACCESS_TYPE, STORE,
MAX_ACCESS_TYPE = STORE, NUM_ACCESS_TYPES = MAX_ACCESS_TYPE - MIN_ACCESS_TYPE
+1}
enum cache_t {
INVALID_CACHE_TYPE, MIN_CACHE_TYPE, PR_L1_CACHE = MIN_CACHE_TYPE, PR_L2_CACHE,
SHARED_CACHE, MAX_CACHE_TYPE = SHARED_CACHE, NUM_CACHE_TYPES = MAX_CACHE_T-
YPE - MIN_CACHE_TYPE + 1 }
enum hash_t {
INVALID_HASH_TYPE, HASH_MASK, HASH_MOD, HASH_RNG1_MOD,
HASH_RNG2_MOD }
enum ReplacementPolicy {
ROUND_ROBIN = 0, LRU, EW_LRU, EW_SRRIP,
MRUT, LRU_QBS, NRU, MRU,
NMRU, PLRU, SRRIP, SRRIP_QBS,
RANDOM, NUM_REPLACEMENT_POLICIES }
An enum.
CacheBase (String name, UInt32 num_sets, UInt32 associativity, UInt32 cache_block_size, CacheBase-
::hash_t hash, AddressHomeLookup ahl=NULL)
virtual CacheBase ()
void splitAddress (const IntPtr addr, IntPtr &tag, UInt32 &set_index) const
void splitAddress (const IntPtr addr, IntPtr &tag, UInt32 &set_index, UInt32 &block_offset) const
IntPtr tagToAddress (const IntPtr tag)
String getName (void)
UInt32 getNumSets () const
UInt32 getAssociativity () const
Static Public Member Functions
static hash_t parseAddressHash (String hash_name)
Protected Attributes
String m_name
UInt64 m_cache_size
UInt32 m_associativity
UInt32 m_blocksize
CacheBase::hash_t m_hash
UInt32 m_num_sets
AddressHomeLookup m_ahl
UInt32 m_log_blocksize
Cache_Base class.
This class is edited in order to add new replacement algorithm files, and then Sniper can recognize them.
6.3.2 Member Enumeration Documentation
6.3.2.1 access_t
enum CacheBase::access_t
Enumerator
INVALID_ACCESS_TYPE
MIN_ACCESS_TYPE
LOAD
STORE
MAX_ACCESS_TYPE
NUM_ACCESS_TYPES
6.3.2.2 cache_t
enum CacheBase::cache_t
Enumerator
INVALID_CACHE_TYPE
MIN_CACHE_TYPE
PR_L1_CACHE
PR_L2_CACHE
SHARED_CACHE
MAX_CACHE_TYPE
NUM_CACHE_TYPES
6.3.2.3 hash_t
enum CacheBase::hash_t
Enumerator
INVALID_HASH_TYPE
HASH_MASK
HASH_MOD
HASH_RNG1_MOD
HASH_RNG2_MOD
6.3.2.4 ReplacementPolicy
enum CacheBase::ReplacementPolicy
An enum.
this enum variable will be used to get the name of the replacement policy that is chosen in the command line. The
policy name will be used in CacheSet class
Enumerator
ROUND_ROBIN
LRU
EW_LRU
EW_SRRIP
MRUT
LRU_QBS
NRU
MRU
Enumerator
NMRU
PLRU
SRRIP
SRRIP_QBS
RANDOM
NUM_REPLACEMENT_POLICIES
6.3.3.1 CacheBase()
CacheBase::CacheBase (
String name,
UInt32 num_sets,
CacheBase::hash_t hash,
AddressHomeLookup ahl = NULL )
6.3.3.2 CacheBase()
CacheBase::CacheBase ( ) [virtual]
6.3.4.1 getAssociativity()
UInt32 CacheBase::getAssociativity ( ) const [inline]
CacheBase::getAssociativity CacheBase::parseAddressHash
CacheBase::getAssociativity
6.3.4.2 getName()
String CacheBase::getName (
void ) [inline]
6.3.4.3 getNumSets()
UInt32 CacheBase::getNumSets ( ) const [inline]
CacheBase::getNumSets
6.3.4.4 parseAddressHash()
CacheBase::hash_t CacheBase::parseAddressHash (
String hash_name ) [static]
CacheBase::parseAddressHash
::CacheCntlr::CacheCntlr
NucaCache::NucaCache
6.3.4.5 splitAddress() [1/2]
void CacheBase::splitAddress (
const IntPtr addr,
IntPtr & tag,
UInt32 & set_index ) const
::CacheCntlr::notifyPrevLevelInsert
::CacheCntlr::doPrefetch ::CacheCntlr::processMemOpFromCore
::CacheCntlr::initiateDirectory ParametricDramDirectoryMSI
Access ::CacheCntlr::processShmemReqFrom
PrevCache
::CacheCntlr::setCacheState ::CacheCntlr::processUpgradeReq
ToDirectory
::CacheCntlr::insertCacheBlock ::CacheCntlr::copyDataFromNextLevel
::CacheCntlr::notifyPrevLevelEvict
NucaCache::read
Cache::getSetLock
::CacheCntlr::writeCacheBlock ParametricDramDirectoryMSI
Cache::peekSingleLine ::CacheCntlr::retrieveCacheBlock ::MemoryManager::accessTLB
Access
CacheBase::splitAddress Cache::accessSingleLine ::CacheCntlr::processShRepFromDram
Directory

::TLB::lookup ParametricDramDirectoryMSI ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
Cache::insertSingleLine NucaCache::write
ATD::access
::TLB::allocate
CacheBase::splitAddress ParametricDramDirectoryMSI
::CacheCntlr::processInvReqFrom ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::handleMsgFromDram
::CacheCntlr::updateCacheBlock ::CacheCntlr::processFlushReqFrom Directory
DramDirectory
Directory
FromDramDirectory
6.3.4.6 splitAddress() [2/2]
void CacheBase::splitAddress (
const IntPtr addr,
IntPtr & tag,
UInt32 & set_index,
UInt32 & block_offset ) const
CacheBase::splitAddress CacheBase::splitAddress
6.3.4.7 tagToAddress()
IntPtr CacheBase::tagToAddress (
const IntPtr tag )
Directory
NucaCache::write
::CacheCntlr::isInLowerLevelCache
PrevCache
6.3.5.1 m_ahl
AddressHomeLookup CacheBase::m_ahl [protected]
6.3.5.2 m_associativity
UInt32 CacheBase::m_associativity [protected]
6.3.5.3 m_blocksize
UInt32 CacheBase::m_blocksize [protected]
6.3.5.4 m_cache_size
UInt64 CacheBase::m_cache_size [protected]
6.3.5.5 m_hash
CacheBase::hash_t CacheBase::m_hash [protected]
6.3.5.6 m_log_blocksize
UInt32 CacheBase::m_log_blocksize [protected]
6.3.5.7 m_name
String CacheBase::m_name [protected]
6.3.5.8 m_num_sets
UInt32 CacheBase::m_num_sets [protected]
cache_base.h
cache_base.cc
6.4 CacheBlockInfo Class Reference
#include <cache_block_info.h>
Inheritance diagram for CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
PrL2CacheBlockInfo
- m_cached_loc_bitvec SharedCacheBlockInfo
PrL1CacheBlockInfo + PrL2CacheBlockInfo()
+ ~PrL2CacheBlockInfo()
+ getCachedLoc() + SharedCacheBlockInfo()
+ PrL1CacheBlockInfo() + setCachedLoc() + ~SharedCacheBlockInfo()
+ ~PrL1CacheBlockInfo() + clearCachedLoc() + invalidate()
+ getCachedLocBitVec() + clone()
+ invalidate()
+ clone()
6.4 CacheBlockInfo Class Reference 39
Collaboration diagram for CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
Public Types
enum option_t { PREFETCH, WARMUP, NUM_OPTIONS }

typedef UInt8 BitsUsedType
CacheBlockInfo (IntPtr tag=0, CacheState::cstate_t cstate=CacheState::INVALID, UInt64 options=0)

virtual CacheBlockInfo ()
virtual void invalidate (void)
virtual void clone (CacheBlockInfo cache_block_info)
bool isValid () const
IntPtr getTag () const
CacheState::cstate_t getCState () const
void setTag (IntPtr tag)
void setCState (CacheState::cstate_t cstate)
UInt64 getOwner () const
void setOwner (UInt64 owner)

bool hasOption (option_t option)
void setOption (option_t option)
void clearOption (option_t option)
BitsUsedType getUsage () const
bool updateUsage (UInt32 offset, UInt32 size)
bool updateUsage (BitsUsedType used)
static CacheBlockInfo create (CacheBase::cache_t cache_type)

static const char getOptionName (option_t option)
Static Public Attributes
static const UInt8 BitsUsedOffset = 3
Private Attributes
IntPtr m_tag
CacheState::cstate_t m_cstate
UInt64 m_owner
BitsUsedType m_used
UInt8 m_options
Static Private Attributes
static const char option_names [ ]
6.4.1 Member Typedef Documentation
6.4.1.1 BitsUsedType
typedef UInt8 CacheBlockInfo::BitsUsedType
6.4.2.1 option_t
enum CacheBlockInfo::option_t
Enumerator
PREFETCH
WARMUP
NUM_OPTIONS
6.4.3.1 CacheBlockInfo()
CacheBlockInfo::CacheBlockInfo (
IntPtr tag = 0,
CacheState::cstate_t cstate = CacheState::INVALID,
UInt64 options = 0 )
6.4.3.2 CacheBlockInfo()
CacheBlockInfo::CacheBlockInfo ( ) [virtual]
6.4.4.1 clearOption()
void CacheBlockInfo::clearOption (
option_t option ) [inline]
CacheBlockInfo::clearOption ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Access
PrevCache
6.4.4.2 clone()
void CacheBlockInfo::clone (
CacheBlockInfo cache_block_info ) [virtual]
Reimplemented in SharedCacheBlockInfo, and PrL2CacheBlockInfo.
CacheBlockInfo::clone
CacheBlockInfo::getCState
ParametricDramDirectoryMSI ::MemoryManager::accessTLB
::TLB::allocate ParametricDramDirectoryMSI
Directory
CacheSet::insert Cache::insertSingleLine
PrL2CacheBlockInfo PrL2CacheBlockInfo
CacheBlockInfo::clone NucaCache::write
::clone ::getCachedLocBitVec
SharedCacheBlockInfo SharedCacheBlockInfo
::clone ::~SharedCacheBlockInfo
PrevCache
6.4.4.3 create()
CacheBlockInfo CacheBlockInfo::create (
CacheBase::cache_t cache_type ) [static]
::TLB::lookup
Directory
CacheSet::CacheSet
NucaCache::write
PrevCache
6.4.4.4 getCState()
CacheState::cstate_t CacheBlockInfo::getCState ( ) const [inline]
PrL2CacheBlockInfo PrL2CacheBlockInfo NucaCache::write

CacheSet::insert Cache::insertSingleLine ::TLB::allocate ParametricDramDirectoryMSI
::TLB::lookup
::CacheCntlr::initiateDirectory PrevCache
Access ParametricDramDirectoryMSI
CacheBlockInfo::getCState ::CacheCntlr::Prefetch
Access
::CacheCntlr::copyDataFromNextLevel ParametricDramDirectoryMSI ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::CacheCntlr::accessCache
::CacheCntlr::writeCacheBlock
Directory
DramDirectory
Directory
FromDramDirectory
6.4.4.5 getOptionName()
const char CacheBlockInfo::getOptionName (

option_t option ) [static]
CacheBlockInfo::getOptionName CacheBlockInfo::getUsage
::CacheCntlr::copyDataFromNextLevel ParametricDramDirectoryMSI
::CacheCntlr::insertCacheBlock ::MemoryManager::coreInitiateMemory
Access
PrevCache ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory ::CacheCntlr::Prefetch
::CacheCntlr::processShRepFromDram ::MemoryManager::handleMsgFromNetwork
Directory
Directory
6.4.4.6 getOwner()
UInt64 CacheBlockInfo::getOwner ( ) const [inline]
CacheBlockInfo::getOwner
Access
Directory
Directory
6.4.4.7 getTag()
IntPtr CacheBlockInfo::getTag ( ) const [inline]
SharedCacheBlockInfo SharedCacheBlockInfo ::TLB::lookup ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::clone ::~SharedCacheBlockInfo ParametricDramDirectoryMSI
::MemoryManager::accessTLB ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
::TLB::allocate ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::processShRepFromDram ::MemoryManager::coreInitiateMemory
Directory Access
::clone ::getCachedLocBitVec ParametricDramDirectoryMSI
CacheBlockInfo::clone Directory
CacheSet::insert
Directory
NucaCache::write
::CacheCntlr::isInLowerLevelCache ::CacheCntlr::processMemOpFromCore
PrevCache
6.4.4.8 getUsage()
BitsUsedType CacheBlockInfo::getUsage ( ) const [inline]
CacheBlockInfo::updateUsage
CacheBlockInfo::getUsage
CacheBlockInfo::getOptionName
Access
Directory
Directory
6.4.4.9 hasOption()
bool CacheBlockInfo::hasOption (
::CacheCntlr::processMemOpFromCore ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI PrevCache
CacheBlockInfo::hasOption ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI Access

::CacheCntlr::processShRepFromDram ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
::CacheCntlr::processExRepFromDram ParametricDramDirectoryMSI
Directory ::MemoryManager::handleMsgFromNetwork
::CacheCntlr::processWbReqFromDram ::CacheCntlr::handleMsgFromDram
Directory Directory
FromDramDirectory
DramDirectory
DramDirectory
6.4.4.10 invalidate()
void CacheBlockInfo::invalidate (
void ) [virtual]
Reimplemented in SharedCacheBlockInfo, and PrL2CacheBlockInfo.
CacheSet::invalidate Cache::invalidateSingleLine
CacheBlockInfo::invalidate
SharedCacheBlockInfo ::CacheCntlr::processMemOpFromCore ParametricDramDirectoryMSI
::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
::invalidate ParametricDramDirectoryMSI
PrevCache Access
SharedCacheBlockInfo ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::~SharedCacheBlockInfo ::CacheCntlr::copyDataFromNextLevel ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
PrL2CacheBlockInfo
::invalidate
PrL2CacheBlockInfo ParametricDramDirectoryMSI
::getCachedLocBitVec ::CacheCntlr::processWbReqFromDram
Directory
::CacheCntlr::updateCacheBlock ::MemoryManager::handleMsgFromNetwork
::CacheCntlr::processUpgradeRep ::CacheCntlr::handleMsgFromDram
FromDramDirectory Directory
DramDirectory
DramDirectory
6.4.4.11 isValid()
bool CacheBlockInfo::isValid ( ) const [inline]
CacheBlockInfo::isValid
6.4.4.12 setCState()
void CacheBlockInfo::setCState (
CacheState::cstate_t cstate ) [inline]
ParametricDramDirectoryMSI ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
ParametricDramDirectoryMSI ::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::initiateDirectory PrevCache ParametricDramDirectoryMSI
CacheBlockInfo::setCState ::CacheCntlr::processMemOpFromCore
::CacheCntlr::setCacheState ::CacheCntlr::insertCacheBlock Access ::MemoryManager::coreInitiateMemory
Access
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI

::CacheCntlr::processUpgradeReq ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
ToDirectory
NucaCache::write
Directory
Directory
FromDramDirectory
DramDirectory
DramDirectory
Directory
6.4.4.13 setOption()
void CacheBlockInfo::setOption (
Directory
Directory
Directory
CacheBlockInfo::setOption
::CacheCntlr::insertCacheBlock ParametricDramDirectoryMSI

::CacheCntlr::processShmemReqFrom ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
PrevCache
6.4.4.14 setOwner()
void CacheBlockInfo::setOwner (
UInt64 owner ) [inline]
CacheBlockInfo::setOwner ParametricDramDirectoryMSI
::CacheCntlr::insertCacheBlock ::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
PrevCache Access
ParametricDramDirectoryMSI ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::processExRepFromDram ::CacheCntlr::Prefetch ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
Directory
Directory
6.4.4.15 setTag()
void CacheBlockInfo::setTag (
IntPtr tag ) [inline]
::TLB::lookup
Directory
CacheBlockInfo::setTag Cache::insertSingleLine
NucaCache::write
PrevCache
6.4.4.16 updateUsage() [1/2]
bool CacheBlockInfo::updateUsage (
UInt32 offset,
UInt32 size )
PrevCache
Access
CacheBlockInfo::getUsage ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
::CacheCntlr::processShRepFromDram ::CacheCntlr::handleMsgFromDram
Directory Directory
6.4.4.17 updateUsage() [2/2]
bool CacheBlockInfo::updateUsage (
BitsUsedType used )
6.4.5.1 BitsUsedOffset
const UInt8 CacheBlockInfo::BitsUsedOffset = 3 [static]
6.4.5.2 m_cstate
CacheState::cstate_t CacheBlockInfo::m_cstate [private]
6.4.5.3 m_options
UInt8 CacheBlockInfo::m_options [private]
6.4.5.4 m_owner
UInt64 CacheBlockInfo::m_owner [private]
6.4.5.5 m_tag
IntPtr CacheBlockInfo::m_tag [private]
6.4.5.6 m_used
BitsUsedType CacheBlockInfo::m_used [private]
6.4.5.7 option_names
const char CacheBlockInfo::option_names [static], [private]
Initial value:
=
{
"prefetch",
"warmup",
}
cache_block_info.h
cache_block_info.cc
6.5 CacheCntlr Class Reference 49
6.5 CacheCntlr Class Reference
#include <cache_block_info.h>
Inheritance diagram for CacheCntlr:
CacheCntlr
+ isInLowerLevelCache()
+ incrementQBSLookupCost()
::CacheCntlr
+ loads
+ stores
+ load_misses
+ store_misses
+ load_overlapping_misses
+ store_overlapping_misses
+ loads_state
+ stores_state
+ loads_where
+ stores_where
+ load_misses_state
+ store_misses_state
+ loads_prefetch
+ stores_prefetch
+ hits_prefetch
+ evict_prefetch
+ invalidate_prefetch
+ evict
and 13 more...
- m_mem_component
- m_memory_manager
- m_master
- m_next_cache_cntlr
- m_last_level
- m_tag_directory_home
_lookup
- m_shmem_req_source_map
- m_perfect
- m_passthrough
- m_coherent
- m_prefetch_on_prefetch_hit
- m_l1_mshr
- stats
- m_core_id
- m_cache_block_size
- m_cache_writethrough
- m_writeback_time
- m_next_level_read_bandwidth
and 10 more...
+ CacheCntlr()
+ ~CacheCntlr()
+ getCache()
+ getLock()
+ setPrevCacheCntlrs()
+ setNextCacheCntlr()
+ createSetLocks()
+ setDRAMDirectAccess()
+ processMemOpFromCore()
+ updateHits()
+ notifyPrevLevelInsert()
+ notifyPrevLevelEvict()
+ handleMsgFromDramDirectory()
+ acquireLock()
+ releaseLock()
+ acquireStackLock()
+ releaseStackLock()
+ isMasterCache()
+ isFirstLevel()
+ isLastLevel()
+ isShared()
+ enable()
+ disable()
- updateCounters()
- cleanupMshr()
- transition()
- updateUncoreStatistics()
- accessCache()
- operationPermissibleinCache()
- copyDataFromNextLevel()
- trainPrefetcher()
- Prefetch()
- doPrefetch()
- getCacheBlockInfo()
- getCacheState()
- getCacheState()
- setCacheState()
- invalidateCacheBlock()
- retrieveCacheBlock()
- insertCacheBlock()
- updateCacheBlock()
and 26 more...
- __walkUsageBits()
Collaboration diagram for CacheCntlr:
CacheCntlr
virtual bool isInLowerLevelCache (CacheBlockInfo block_info)

virtual void incrementQBSLookupCost ()
6.5.1.1 incrementQBSLookupCost()
virtual void CacheCntlr::incrementQBSLookupCost ( ) [inline], [virtual]
Reimplemented in ParametricDramDirectoryMSI::CacheCntlr.
CacheSetLRU::getReplacement
Index
CacheCntlr::incrementQBSLookupCost
CacheSetSRRIP::getReplacement
Index
6.6 ParametricDramDirectoryMSI::CacheCntlr Class Reference 51
6.5.1.2 isInLowerLevelCache()
virtual bool CacheCntlr::isInLowerLevelCache (

CacheBlockInfo block_info ) [inline], [virtual]
Reimplemented in ParametricDramDirectoryMSI::CacheCntlr.
Index
CacheCntlr::isInLowerLevel
Cache
Index
The documentation for this class was generated from the following file:
cache_block_info.h
6.6 ParametricDramDirectoryMSI::CacheCntlr Class Reference
#include <cache_cntlr.h>
Inheritance diagram for ParametricDramDirectoryMSI::CacheCntlr:
CacheCntlr
::CacheCntlr
+ loads
+ stores
+ load_misses
+ store_misses
+ loads_state
+ stores_state
+ loads_where
+ stores_where
+ load_misses_state
+ loads_prefetch
+ stores_prefetch
+ hits_prefetch
+ evict_prefetch
+ evict
and 13 more...
- m_mem_component
- m_memory_manager
- m_master
- m_next_cache_cntlr
- m_last_level
_lookup
- m_perfect
- m_passthrough
- m_coherent
- m_l1_mshr
- stats
- m_core_id
- m_writeback_time
and 10 more...
+ CacheCntlr()
+ ~CacheCntlr()
+ getCache()
+ getLock()
+ createSetLocks()
+ updateHits()
+ acquireLock()
+ releaseLock()
+ isMasterCache()
+ isFirstLevel()
+ isLastLevel()
+ isShared()
+ enable()
+ disable()
- updateCounters()
- cleanupMshr()
- transition()
- accessCache()
- trainPrefetcher()
- Prefetch()
- doPrefetch()
- getCacheState()
- getCacheState()
- setCacheState()
and 26 more...
- __walkUsageBits()
Collaboration diagram for ParametricDramDirectoryMSI::CacheCntlr:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity CacheBase
# m_blocksize
# m_name
# m_lock
# m_cache_size
+ CacheSet() # m_associativity ReqQueueListTemplate
+ ~CacheSet() # m_blocksize < T_Req >
+ getBlockSize() # m_hash
- m_req_queue_list
+ getAssociativity() # m_num_sets
+ getLock() # m_ahl CacheSetInfo std::vector< CacheCntlr * > + ReqQueueListTemplate()
+ read_line() # m_log_blocksize + ~ReqQueueListTemplate()
+ write_line() + enqueue()
+ CacheBase()
+ find() + ~CacheSetInfo() + dequeue()
+ ~CacheBase()
+ invalidate() + front()
+ splitAddress()
+ insert() + back()
+ splitAddress()
+ peekBlock() + size()
+ tagToAddress()
+ getDataPtr() + empty()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
-m_sets -m_set_info < CacheDirectoryWaiter >
Cache
- m_enabled
- m_num_accesses
- m_num_hits ReqQueueListTemplate
- m_cache_type < CacheDirectoryWaiter >
- m_fault_injector
- m_req_queue_list
+ Cache() ParametricDramDirectoryMSI Prefetcher
::CacheCntlrList + ReqQueueListTemplate()
+ ~Cache()
+ ~ReqQueueListTemplate()
+ getSetLock()
+ enqueue()
+ invalidateSingleLine() + getNextAddress()
+ dequeue()
+ accessSingleLine() + createPrefetcher()
+ front()
+ back()
+ peekSingleLine()
+ size()
+ peekBlock()
+ empty()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_cache -m_cache -m_cache -m_prev_cache_cntlrs -m_directory_waiters -m_prefetcher
::CacheMasterCntlr
- m_cache_lock
- m_smt_lock
- m_dram_cntlr
- m_dram_outstanding
_writebacks
- mshr
- m_l1_mshr
CacheCntlr - m_next_level_read_bandwidth
- m_evicting_address
- m_evicting_buf
- m_atds
+ isInLowerLevelCache() - m_setlocks
+ incrementQBSLookupCost() - m_log_blocksize
- m_num_sets
- m_prefetch_list
- m_prefetch_next
- createSetLocks()
- getSetLock()
- createATDs()
- accessATDs()
- CacheMasterCntlr()
- ~CacheMasterCntlr()
NucaCache
- m_core_id
- m_memory_manager
ParametricDramDirectoryMSI::TLB - m_shmem_perf_model
- m_home_lookup
- m_size - m_cache_block_size
- m_associativity - m_data_access_time
- m_access - m_tags_access_time
- m_miss - m_data_array_bandwidth
- SIM_PAGE_SHIFT -m_next_level - m_queue_model -m_master
- SIM_PAGE_SIZE - m_reads
- SIM_PAGE_MASK - m_writes
- m_read_misses
+ TLB() - m_write_misses
+ lookup()
+ allocate() + NucaCache()
+ ~NucaCache()
+ read()
+ write()
- accessDataArray()
::CacheCntlr
+ loads
+ stores
+ load_misses
+ store_misses
+ loads_state
+ stores_state
+ loads_where
+ stores_where
+ load_misses_state
+ loads_prefetch
+ stores_prefetch
+ hits_prefetch
+ evict_prefetch
+ evict
and 13 more...
- m_mem_component
_lookup
- m_perfect
- m_passthrough
- m_coherent
- m_l1_mshr
- stats
- m_core_id
- m_writeback_time
- m_shared_cores
- m_core_id_master
- m_user_thread_sem
- m_network_thread_sem
- m_last_remote_hit_where
- m_shmem_perf
- m_shmem_perf_global
MemoryManagerBase - m_shmem_perf_totaltime
-m_itlb - m_shmem_perf_numrequests
-m_next_cache_cntlr
-m_dtlb -m_nuca_cache - m_shmem_perf_model
-m_last_level
-m_stlb
+ CacheCntlr()
+ ~CacheCntlr()
+ getCache()
+ getLock()
+ createSetLocks()
+ updateHits()
+ acquireLock()
+ releaseLock()
+ isMasterCache()
+ isFirstLevel()
+ isLastLevel()
+ isShared()
+ enable()
+ disable()
- updateCounters()
- cleanupMshr()
- transition()
- accessCache()
- trainPrefetcher()
- Prefetch()
- doPrefetch()
- getCacheState()
- getCacheState()
- setCacheState()
and 26 more...
- __walkUsageBits()
-m_memory_manager -m_cache_cntlrs
::MemoryManager
- m_dram_cache
- m_dram_directory_cntlr
- m_dram_cntlr
_lookup
- m_dram_controller_home
_lookup
- m_tlb_miss_penalty
- m_tlb_miss_parallel
- m_core_id_master
- m_tag_directory_present
- m_dram_cntlr_present
- m_user_thread_sem
- m_last_level_cache
- m_enabled
- m_cache_perf_models
- m_all_cache_cntlrs
+ MemoryManager()
+ ~MemoryManager()
+ getCacheBlockSize()
+ getCache()
+ getL1ICache()
+ getL1DCache()
+ getLastLevelCache()
+ getDramDirectoryCache()
+ getDramCntlr()
+ getTagDirectoryHomeLookup()
+ getDramControllerHomeLookup()
+ getCacheCntlrAt()
+ setCacheCntlrAt()
+ coreInitiateMemoryAccess()
+ handleMsgFromNetwork()
+ sendMsg()
+ broadcastMsg()
+ getL1HitLatency()
+ addL1Hits()
+ enableModels()
+ disableModels()
+ getShmemRequester()
+ getModeledLength()
+ getCost()
+ incrElapsedTime()
+ incrElapsedTime()
- accessTLB()
CacheCntlr (MemComponent::component_t mem_component, String name, core_id_t core_id, Memory-

Manager memory_manager, AddressHomeLookup tag_directory_home_lookup, Semaphore user_-
thread_sem, Semaphore network_thread_sem, UInt32 cache_block_size, CacheParameters &cache_-
params, ShmemPerfModel shmem_perf_model, bool is_last_level_cache)
virtual CacheCntlr ()
Cache getCache ()
Lock & getLock ()
void setPrevCacheCntlrs (CacheCntlrList &prev_cache_cntlrs)
void setNextCacheCntlr (CacheCntlr next_cache_cntlr)
void createSetLocks (UInt32 cache_block_size, UInt32 num_sets, UInt32 core_offset, UInt32 num_cores)
void setDRAMDirectAccess (DramCntlrInterface dram_cntlr, UInt64 num_outstanding)
HitWhere::where_t processMemOpFromCore (Core::lock_signal_t lock_signal, Core::mem_op_t mem_op-
_type, IntPtr ca_address, UInt32 offset, Byte data_buf, UInt32 data_length, bool modeled, bool count)
void updateHits (Core::mem_op_t mem_op_type, UInt64 hits)
void notifyPrevLevelInsert (core_id_t core_id, MemComponent::component_t mem_component, IntPtr ad-
dress)
void notifyPrevLevelEvict (core_id_t core_id, MemComponent::component_t mem_component, IntPtr ad-
dress)
void handleMsgFromDramDirectory (core_id_t sender, PrL1PrL2DramDirectoryMSI::ShmemMsg shmem-
_msg)
void acquireLock (UInt64 address)
void releaseLock (UInt64 address)
void acquireStackLock (UInt64 address, bool this_is_locked=false)
void releaseStackLock (UInt64 address, bool this_is_locked=false)
bool isMasterCache (void)
bool isFirstLevel (void)
bool isLastLevel (void)
bool isShared (core_id_t core_id)
bool isInLowerLevelCache (CacheBlockInfo block_info)
void incrementQBSLookupCost ()
void enable ()
void disable ()
void updateCounters (Core::mem_op_t mem_op_type, IntPtr address, bool cache_hit, CacheState::cstate_t

state, Prefetch::prefetch_type_t isPrefetch)
void cleanupMshr ()
void transition (IntPtr address, Transition::reason_t reason, CacheState::cstate_t old_state, CacheState-
::cstate_t new_state)
void updateUncoreStatistics (HitWhere::where_t hit_where, SubsecondTime now)
void accessCache (Core::mem_op_t mem_op_type, IntPtr ca_address, UInt32 offset, Byte data_buf, UInt32
data_length, bool update_replacement)
bool operationPermissibleinCache (IntPtr address, Core::mem_op_t mem_op_type, CacheBlockInfo
cache_block_info=NULL)
void copyDataFromNextLevel (Core::mem_op_t mem_op_type, IntPtr address, bool modeled, Subsecond-
Time t_start)
void trainPrefetcher (IntPtr address, bool cache_hit, bool prefetch_hit, SubsecondTime t_issue)
void Prefetch (SubsecondTime t_start)
void doPrefetch (IntPtr prefetch_address, SubsecondTime t_start)
SharedCacheBlockInfo getCacheBlockInfo (IntPtr address)
CacheState::cstate_t getCacheState (IntPtr address)
CacheState::cstate_t getCacheState (CacheBlockInfo cache_block_info)
SharedCacheBlockInfo setCacheState (IntPtr address, CacheState::cstate_t cstate)
void invalidateCacheBlock (IntPtr address)
void retrieveCacheBlock (IntPtr address, Byte data_buf, ShmemPerfModel::Thread_t thread_num, bool
update_replacement)
SharedCacheBlockInfo insertCacheBlock (IntPtr address, CacheState::cstate_t cstate, Byte data_buf,
core_id_t requester, ShmemPerfModel::Thread_t thread_num)
std::pair< SubsecondTime, bool > updateCacheBlock (IntPtr address, CacheState::cstate_t cstate,

Transition::reason_t reason, Byte out_buf, ShmemPerfModel::Thread_t thread_num)
void writeCacheBlock (IntPtr address, UInt32 offset, Byte data_buf, UInt32 data_length, ShmemPerfModel-
::Thread_t thread_num)
HitWhere::where_t processShmemReqFromPrevCache (CacheCntlr requester, Core::mem_op_t mem_-
op_type, IntPtr address, bool modeled, bool count, Prefetch::prefetch_type_t isPrefetch, SubsecondTime
t_issue, bool have_write_lock)
boost::tuple< HitWhere::where_t, SubsecondTime > accessDRAM (Core::mem_op_t mem_op_type, IntPtr
address, bool isPrefetch, Byte data_buf)
void initiateDirectoryAccess (Core::mem_op_t mem_op_type, IntPtr address, bool isPrefetch, Subsecond-
Time t_issue)
void processExReqToDirectory (IntPtr address)
void processShReqToDirectory (IntPtr address)
void processUpgradeReqToDirectory (IntPtr address, ShmemPerf perf, ShmemPerfModel::Thread_-
t thread_num)
void processExRepFromDramDirectory (core_id_t sender, core_id_t requester, PrL1PrL2DramDirectoryM-
SI::ShmemMsg shmem_msg)
void processShRepFromDramDirectory (core_id_t sender, core_id_t requester, PrL1PrL2DramDirectoryM-
SI::ShmemMsg shmem_msg)
void processUpgradeRepFromDramDirectory (core_id_t sender, core_id_t requester, PrL1PrL2Dram-
DirectoryMSI::ShmemMsg shmem_msg)
void processInvReqFromDramDirectory (core_id_t sender, PrL1PrL2DramDirectoryMSI::ShmemMsg
shmem_msg)
void processFlushReqFromDramDirectory (core_id_t sender, PrL1PrL2DramDirectoryMSI::ShmemMsg
shmem_msg)
void processWbReqFromDramDirectory (core_id_t sender, PrL1PrL2DramDirectoryMSI::ShmemMsg
shmem_msg)
UInt32 getCacheBlockSize ()
MemoryManager getMemoryManager ()
ShmemPerfModel getShmemPerfModel ()
void updateUsageBits (IntPtr address, CacheBlockInfo::BitsUsedType used)
void walkUsageBits ()
void wakeUpUserThread (Semaphore user_thread_sem=NULL)
void waitForUserThread (Semaphore network_thread_sem=NULL)
void waitForNetworkThread (void)
void wakeUpNetworkThread (void)
Semaphore getUserThreadSemaphore (void)
Semaphore getNetworkThreadSemaphore (void)
core_id_t getHome (IntPtr address)
CacheCntlr lastLevelCache (void)
Static Private Member Functions
static SInt64 __walkUsageBits (UInt64 arg0, UInt64 arg1)
Private Attributes
MemComponent::component_t m_mem_component
MemoryManager m_memory_manager
CacheMasterCntlr m_master
CacheCntlr m_next_cache_cntlr
CacheCntlr m_last_level
AddressHomeLookup m_tag_directory_home_lookup
std::unordered_map< IntPtr, MemComponent::component_t > m_shmem_req_source_map

bool m_perfect
bool m_passthrough
bool m_coherent
bool m_prefetch_on_prefetch_hit
bool m_l1_mshr
struct {
UInt64 loads
UInt64 stores
UInt64 load_misses
UInt64 store_misses
UInt64 load_overlapping_misses
UInt64 store_overlapping_misses
UInt64 loads_state [CacheState::NUM_CSTATE_STATES]
UInt64 stores_state [CacheState::NUM_CSTATE_STATES]
UInt64 loads_where [HitWhere::NUM_HITWHERES]
UInt64 stores_where [HitWhere::NUM_HITWHERES]
UInt64 load_misses_state [CacheState::NUM_CSTATE_STATES]
UInt64 store_misses_state [CacheState::NUM_CSTATE_STATES]
UInt64 loads_prefetch
UInt64 stores_prefetch
UInt64 hits_prefetch
UInt64 evict_prefetch
UInt64 invalidate_prefetch
UInt64 evict [CacheState::NUM_CSTATE_STATES]
UInt64 backinval [CacheState::NUM_CSTATE_STATES]
UInt64 hits_warmup
UInt64 evict_warmup
UInt64 invalidate_warmup
SubsecondTime total_latency
SubsecondTime snoop_latency
SubsecondTime qbs_query_latency
SubsecondTime mshr_latency
UInt64 prefetches
UInt64 coherency_downgrades
UInt64 coherency_upgrades
UInt64 coherency_invalidates
UInt64 coherency_writebacks
} stats
core_id_t m_core_id
UInt32 m_cache_block_size
bool m_cache_writethrough
ComponentLatency m_writeback_time
ComponentBandwidthPerCycle m_next_level_read_bandwidth
UInt32 m_shared_cores
core_id_t m_core_id_master
Semaphore m_user_thread_sem
Semaphore m_network_thread_sem
volatile HitWhere::where_t m_last_remote_hit_where
ShmemPerf m_shmem_perf
ShmemPerf m_shmem_perf_global
SubsecondTime m_shmem_perf_totaltime
UInt64 m_shmem_perf_numrequests
ShmemPerfModel m_shmem_perf_model
Friends
class CacheCntlrList
class MemoryManager
6.6.1.1 CacheCntlr()
CacheCntlr::CacheCntlr (
MemComponent::component_t mem_component,
String name,
core_id_t core_id,
MemoryManager memory_manager,
AddressHomeLookup tag_directory_home_lookup,
Semaphore user_thread_sem,
Semaphore network_thread_sem,
CacheParameters & cache_params,
ShmemPerfModel shmem_perf_model,
bool is_last_level_cache )
::CacheCntlr::isMasterCache
Prefetcher::createPrefetcher
::CacheMasterCntlr::createATDs
::CacheCntlr::CacheCntlr ::CacheCntlr::__walkUsageBits
::CacheCntlr::getMemoryManager
::MemoryManager::getCacheCntlrAt
::CStateString
::ReasonString
6.6.1.2 CacheCntlr()
CacheCntlr::CacheCntlr ( ) [virtual]
::CacheCntlr::~CacheCntlr ::CacheCntlr::isMasterCache
6.6.2.1 __walkUsageBits()
static SInt64 ParametricDramDirectoryMSI::CacheCntlr::__walkUsageBits (

UInt64 arg0,
UInt64 arg1 ) [inline], [static], [private]
::CacheCntlr::__walkUsageBits ::CacheCntlr::CacheCntlr
6.6.2.2 accessCache()
void CacheCntlr::accessCache (
IntPtr ca_address,
UInt32 offset,
Byte data_buf,
UInt32 data_length,
bool update_replacement ) [private]
::CacheCntlr::accessCache ::CacheCntlr::getShmemPerfModel
ParametricDramDirectoryMSI ::CacheCntlr::acquireStackLock ::CacheMasterCntlr::getSetLock
::CacheCntlr::releaseStackLock ::CacheCntlr::lastLevelCache
::CacheCntlr::getCacheBlockSize
::CacheCntlr::accessCache ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.3 accessDRAM()
boost::tuple< HitWhere::where_t, SubsecondTime > CacheCntlr::accessDRAM (

IntPtr address,
bool isPrefetch,
Byte data_buf ) [private]
::CacheCntlr::getLock
::CacheCntlr::accessDRAM
::CacheCntlr::getShmemPerfModel
Directory
::CacheCntlr::processExRepFromDram ::CacheCntlr::handleMsgFromDram ParametricDramDirectoryMSI
Directory Directory ::MemoryManager::handleMsgFromNetwork
PrevCache
6.6.2.4 acquireLock()
void CacheCntlr::acquireLock (
UInt64 address )
::CacheCntlr::isFirstLevel
::CacheCntlr::acquireLock ::CacheCntlr::lastLevelCache
::CacheMasterCntlr::getSetLock
::CacheCntlr::acquireLock ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.5 acquireStackLock()
void CacheCntlr::acquireStackLock (
UInt64 address,
bool this_is_locked = false )
::CacheCntlr::lastLevelCache
::CacheCntlr::acquireStackLock
PrevCache
::CacheCntlr::accessCache ::CacheCntlr::processMemOpFromCore
Directory
Directory
FromDramDirectory
Directory
DramDirectory
DramDirectory
Directory
6.6.2.6 cleanupMshr()
void CacheCntlr::cleanupMshr ( ) [private]
ParametricDramDirectoryMSI ::CacheCntlr::updateHits
::CacheCntlr::updateCounters ParametricDramDirectoryMSI
Access
::CacheCntlr::cleanupMshr ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
PrevCache ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.7 copyDataFromNextLevel()
void CacheCntlr::copyDataFromNextLevel (
IntPtr address,
bool modeled,
SubsecondTime t_start ) [private]
Cache::invalidateSingleLine CacheSet::invalidate
ParametricDramDirectoryMSI CacheState::writable
CacheState::readable
::CStateString ParametricDramDirectoryMSI
::CacheCntlr::retrieveCacheBlock
Cache::accessSingleLine
Cache::peekSingleLine CacheSet::find
::CacheCntlr::transition CacheBase::tagToAddress
CacheBlockInfo::hasOption CacheBlockInfo::getTag
CacheBlockInfo::setTag
CacheSet::insert
Index

::CacheCntlr::writeCacheBlock ::CacheCntlr::releaseStackLock ::CacheCntlr::lastLevelCache
::CacheCntlr::acquireStackLock ::CacheMasterCntlr::getSetLock
::CacheCntlr::setCacheState CacheBlockInfo::setCState
::MemoryManager::sendMsg
CacheBlockInfo::setOption ::CacheCntlr::getShmemPerfModel
CacheBlockInfo::setOwner
::CacheCntlr::accessDRAM ::CacheCntlr::getLock
::CacheCntlr::getHome
::MemoryManager::incrElapsedTime
::CacheCntlr::copyDataFromNextLevel ::MemoryManager::coreInitiateMemory
Access
PrevCache
6.6.2.8 createSetLocks()
void ParametricDramDirectoryMSI::CacheCntlr::createSetLocks (
UInt32 num_sets,
UInt32 core_offset,
UInt32 num_cores ) [inline]
::CacheCntlr::createSetLocks ::CacheMasterCntlr::createSetLocks
6.6.2.9 disable()
void ParametricDramDirectoryMSI::CacheCntlr::disable ( ) [inline]
Cache::disable
::CacheCntlr::disable
6.6.2.10 doPrefetch()
void CacheCntlr::doPrefetch (
IntPtr prefetch_address,
::CacheCntlr::accessDRAM ::CacheCntlr::getLock
::CacheCntlr::updateUncoreStatistics
::CacheCntlr::initiateDirectory
Access
::make_mshr
::CacheCntlr::doPrefetch ::CacheCntlr::getShmemPerfModel
CacheBlockInfo::hasOption
::CacheCntlr::transition
::CacheCntlr::updateCounters
::CacheCntlr::cleanupMshr ParametricDramDirectoryMSI
::CacheCntlr::trainPrefetcher CacheBlockInfo::getCState
PrevCache
::CacheCntlr::waitForNetworkThread
::CacheCntlr::wakeUpNetworkThread
::CacheCntlr::retrieveCacheBlock CacheBlockInfo::setOwner
CacheBlockInfo::setCState
::CacheCntlr::setCacheState
CacheState::writable
SharedCacheBlockInfo
::invalidate
::CStateString
ParametricDramDirectoryMSI ::CacheCntlr::getMemoryManager
::CacheCntlr::getCache
Cache::updateCounters ::MemoryManager::incrElapsedTime
::CacheCntlr::invalidateCacheBlock ::CacheCntlr::notifyPrevLevelEvict
CacheBlockInfo::clearOption
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.11 enable()
void ParametricDramDirectoryMSI::CacheCntlr::enable ( ) [inline]
Cache::enable
::CacheCntlr::enable
6.6.2.12 getCache()
Cache ParametricDramDirectoryMSI::CacheCntlr::getCache ( ) [inline]
::CacheCntlr::updateHits ::MemoryManager::coreInitiateMemory
Access
PrevCache
::MemoryManager::getL1ICache
::MemoryManager::getCache
::MemoryManager::getL1DCache
::MemoryManager::getLastLevelCache
6.6.2.13 getCacheBlockInfo()
SharedCacheBlockInfo CacheCntlr::getCacheBlockInfo (
IntPtr address ) [private]
CacheSet::find
::CacheCntlr::operationPermissibleinCache ParametricDramDirectoryMSI
::CacheCntlr::getCacheBlockInfo ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
::CacheCntlr::setCacheState ::CacheCntlr::notifyPrevLevelInsert ParametricDramDirectoryMSI Access
Directory
ParametricDramDirectoryMSI ::CacheCntlr::initiateDirectory
::CacheCntlr::processUpgradeReq Access
ToDirectory
Directory
FromDramDirectory
DramDirectory
Directory
6.6.2.14 getCacheBlockSize()
UInt32 ParametricDramDirectoryMSI::CacheCntlr::getCacheBlockSize ( ) [inline], [private]
::CacheCntlr::insertCacheBlock ::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
PrevCache ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI
Directory
DramDirectory
::CacheCntlr::walkUsageBits ::CacheCntlr::processFlushReqFrom
DramDirectory
Directory
6.6.2.15 getCacheState() [1/2]
CacheState::cstate_t CacheCntlr::getCacheState (
::CacheCntlr::getCacheState ::CacheCntlr::getCacheBlockInfo
CacheSet::find
Directory
FromDramDirectory
DramDirectory
::CacheCntlr::processFlushReqFrom ::CacheCntlr::handleMsgFromDram
::CacheCntlr::getCacheState ParametricDramDirectoryMSI

::CacheCntlr::notifyPrevLevelEvict ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
::CacheCntlr::processUpgradeReq ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
ToDirectory ::CacheCntlr::processShRepFromDram Access
Directory
::CacheCntlr::copyDataFromNextLevel ::CacheCntlr::processMemOpFromCore
::CacheCntlr::processExReqToDirectory ::CacheCntlr::initiateDirectory
PrevCache ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI
6.6.2.16 getCacheState() [2/2]
CacheState::cstate_t CacheCntlr::getCacheState (
CacheBlockInfo cache_block_info ) [private]
6.6.2.17 getHome()
core_id_t ParametricDramDirectoryMSI::CacheCntlr::getHome (
IntPtr address ) [inline], [private]
Directory
::CacheCntlr::processExRepFromDram ::CacheCntlr::handleMsgFromDram ParametricDramDirectoryMSI
Directory Directory ::MemoryManager::handleMsgFromNetwork
::CacheCntlr::processUpgradeReq
ToDirectory
::CacheCntlr::getHome ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
PrevCache
::CacheCntlr::processShReqToDirectory
Access
6.6.2.18 getLock()
Lock& ParametricDramDirectoryMSI::CacheCntlr::getLock ( ) [inline]
PrevCache
::CacheCntlr::getLock ParametricDramDirectoryMSI ::CacheCntlr::processMemOpFromCore
::CacheCntlr::Prefetch Access
Directory
Directory
Directory
FromDramDirectory
DramDirectory
DramDirectory
::CacheCntlr::updateHits
6.6.2.19 getMemoryManager()
MemoryManager ParametricDramDirectoryMSI::CacheCntlr::getMemoryManager ( ) [inline], [private]
ParametricDramDirectoryMSI ::CacheCntlr::processMemOpFromCore ParametricDramDirectoryMSI
::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
PrevCache ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI Access
Directory
::CacheCntlr::processExReqToDirectory ParametricDramDirectoryMSI ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::CacheCntlr::processShRepFromDram ::MemoryManager::handleMsgFromNetwork
::CacheCntlr::getMemoryManager Directory
ToDirectory ParametricDramDirectoryMSI
Directory
DramDirectory
DramDirectory
::CacheCntlr::incrementQBSLookupCost
Directory
6.6.2.20 getNetworkThreadSemaphore()
Semaphore CacheCntlr::getNetworkThreadSemaphore (
void ) [private]
6.6.2.21 getShmemPerfModel()
ShmemPerfModel ParametricDramDirectoryMSI::CacheCntlr::getShmemPerfModel ( ) [inline], [private]
::CacheCntlr::updateCounters ::CacheCntlr::updateHits
::CacheCntlr::initiateDirectory ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
Access
PrevCache
Access
::CacheCntlr::processExRepFromDram ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Directory ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
::CacheCntlr::retrieveCacheBlock ParametricDramDirectoryMSI
::CacheCntlr::writeCacheBlock ::CacheCntlr::updateCacheBlock
FromDramDirectory
Directory
Directory
DramDirectory
DramDirectory
6.6.2.22 getUserThreadSemaphore()
Semaphore CacheCntlr::getUserThreadSemaphore (
void ) [private]
6.6.2.23 handleMsgFromDramDirectory()
void CacheCntlr::handleMsgFromDramDirectory (
core_id_t sender,
PrL1PrL2DramDirectoryMSI::ShmemMsg shmem_msg )
ReqQueueListTemplate ParametricDramDirectoryMSI ParametricDramDirectoryMSI

::CacheCntlr::releaseStackLock ::CacheMasterCntlr::getSetLock
::front
::CacheCntlr::acquireStackLock ::CacheCntlr::lastLevelCache
FromDramDirectory
::CacheCntlr::getLock Cache::insertSingleLine
Directory
::CacheCntlr::getShmemPerfModel ParametricDramDirectoryMSI
::MemoryManager::incrElapsedTime Cache::peekSingleLine
::CacheCntlr::processWbReqFromDram CacheBlockInfo::hasOption
Directory
DramDirectory
DramDirectory
ReqQueueListTemplate
::empty
::CacheCntlr::notifyPrevLevelEvict ::CacheCntlr::getCacheBlockInfo
::CStateString
::CacheCntlr::wakeUpUserThread
::CacheCntlr::waitForUserThread
::make_mshr
ParametricDramDirectoryMSI ::CacheCntlr::processUpgradeReq
::CacheCntlr::cleanupMshr ToDirectory ParametricDramDirectoryMSI
::dequeue ParametricDramDirectoryMSI
::MemoryManager::handleMsgFromNetwork ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.24 incrementQBSLookupCost()
void CacheCntlr::incrementQBSLookupCost ( ) [virtual]
Reimplemented from CacheCntlr.
::CacheCntlr::incrementQBSLookupCost
6.6.2.25 initiateDirectoryAccess()
void CacheCntlr::initiateDirectoryAccess (
IntPtr address,
bool isPrefetch,
SubsecondTime t_issue ) [private]
::enqueue
::size
::CacheCntlr::initiateDirectory CacheBlockInfo::setCState
Access
::CacheCntlr::setCacheState CacheBase::splitAddress
ParametricDramDirectoryMSI ::CacheCntlr::getCacheBlockInfo
::CacheCntlr::processUpgradeReq ParametricDramDirectoryMSI CacheSet::find
ToDirectory ::CacheCntlr::getCacheState
::CacheCntlr::processExReqToDirectory ::CacheCntlr::getMemoryManager
::CacheCntlr::processShReqToDirectory ::MemoryManager::sendMsg
CacheBlockInfo::getCState ParametricDramDirectoryMSI

::CacheCntlr::initiateDirectory ::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Access PrevCache ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.26 insertCacheBlock()
SharedCacheBlockInfo CacheCntlr::insertCacheBlock (
IntPtr address,
CacheState::cstate_t cstate,
Byte data_buf,
core_id_t requester,
ShmemPerfModel::Thread_t thread_num ) [private]
::CStateString
::CacheCntlr::setCacheState ::CacheCntlr::getCacheBlockInfo
::CacheCntlr::notifyPrevLevelInsert Cache::peekSingleLine
CacheSet::find
CacheSet::insert Index
CacheBase::tagToAddress CacheBlockInfo::clone
::CacheCntlr::insertCacheBlock ::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
PrevCache Access
Directory
Directory
Directory
6.6.2.27 invalidateCacheBlock()
void CacheCntlr::invalidateCacheBlock (
Cache::invalidateSingleLine CacheSet::invalidate CacheBlockInfo::invalidate
::CStateString
FromDramDirectory
DramDirectory
Directory
6.6.2.28 isFirstLevel()
bool ParametricDramDirectoryMSI::CacheCntlr::isFirstLevel (
void ) [inline]
::CacheCntlr::acquireLock
::CacheCntlr::isFirstLevel ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
::CacheCntlr::releaseLock
6.6.2.29 isInLowerLevelCache()
bool CacheCntlr::isInLowerLevelCache (
CacheBlockInfo block_info ) [virtual]
Reimplemented from CacheCntlr.
::CacheCntlr::isInLowerLevelCache
6.6.2.30 isLastLevel()
bool ParametricDramDirectoryMSI::CacheCntlr::isLastLevel (
void ) [inline]
6.6.2.31 isMasterCache()
bool ParametricDramDirectoryMSI::CacheCntlr::isMasterCache (
void ) [inline]
::CacheCntlr::isMasterCache
::CacheCntlr::~CacheCntlr
6.6.2.32 isShared()
bool CacheCntlr::isShared (
core_id_t core_id )
6.6.2.33 lastLevelCache()
CacheCntlr CacheCntlr::lastLevelCache (
void ) [private]
::CacheCntlr::releaseStackLock
PrevCache ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
Directory
Access
DramDirectory
ParametricDramDirectoryMSI ::CacheCntlr::processWbReqFromDram ::CacheCntlr::handleMsgFromDram
::CacheCntlr::acquireStackLock Directory Directory ParametricDramDirectoryMSI ParametricDramDirectoryMSI
FromDramDirectory
DramDirectory
6.6.2.34 notifyPrevLevelEvict()
void CacheCntlr::notifyPrevLevelEvict (
core_id_t core_id,
IntPtr address )
::CacheCntlr::notifyPrevLevelEvict ::CStateString Cache::peekSingleLine
CacheSet::find

PrevCache ParametricDramDirectoryMSI
::CacheCntlr::notifyPrevLevelEvict Access
Directory
::CacheCntlr::invalidateCacheBlock ParametricDramDirectoryMSI
DramDirectory
Directory Directory
FromDramDirectory
DramDirectory
6.6.2.35 notifyPrevLevelInsert()
void CacheCntlr::notifyPrevLevelInsert (
core_id_t core_id,
IntPtr address )
::CacheCntlr::notifyPrevLevelInsert ::CacheCntlr::getCacheBlockInfo
CacheSet::find
::CacheCntlr::notifyPrevLevelInsert ::CacheCntlr::insertCacheBlock ::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
PrevCache Access
Directory
Directory
Directory
6.6.2.36 operationPermissibleinCache()
bool CacheCntlr::operationPermissibleinCache (
IntPtr address,
CacheBlockInfo cache_block_info = NULL ) [private]
ParametricDramDirectoryMSI CacheSet::find
::CStateString
Access
::CacheCntlr::operationPermissibleinCache ::CacheCntlr::trainPrefetcher
6.6.2.37 Prefetch()
void CacheCntlr::Prefetch (
Access
::CacheCntlr::waitForNetworkThread CacheState::writable
ParametricDramDirectoryMSI ParametricDramDirectoryMSI CacheState::readable

::CacheCntlr::wakeUpNetworkThread ::CacheCntlr::operationPermissibleinCache
::CacheCntlr::doPrefetch ::CacheCntlr::getCacheState

::CacheCntlr::updateUncoreStatistics ::CacheCntlr::invalidateCacheBlock ::CStateString
::make_mshr
Cache::peekSingleLine CacheBase::splitAddress
PrevCache ::CacheCntlr::notifyPrevLevelInsert
Cache::insertSingleLine CacheSet::find
ParametricDramDirectoryMSI ::CacheCntlr::getShmemPerfModel
::CacheCntlr::copyDataFromNextLevel ::CacheCntlr::insertCacheBlock
ParametricDramDirectoryMSI CacheBlockInfo::getUsage
::invalidate
Cache::updateCounters ParametricDramDirectoryMSI
::CacheCntlr::cleanupMshr ParametricDramDirectoryMSI
CacheBlockInfo::clearOption ParametricDramDirectoryMSI
::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.38 processExRepFromDramDirectory()
void CacheCntlr::processExRepFromDramDirectory (
core_id_t sender,
PrL1PrL2DramDirectoryMSI::ShmemMsg shmem_msg ) [private]
::CStateString
CacheSet::find
Directory
::CacheCntlr::processExRepFromDram ::CacheCntlr::handleMsgFromDram
Directory Directory
6.6.2.39 processExReqToDirectory()
void CacheCntlr::processExReqToDirectory (

::CacheCntlr::initiateDirectory ::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
::CacheCntlr::processExReqToDirectory ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access PrevCache Access
6.6.2.40 processFlushReqFromDramDirectory()
void CacheCntlr::processFlushReqFromDramDirectory (
core_id_t sender,
::CacheCntlr::invalidateCacheBlock ParametricDramDirectoryMSI Cache::peekSingleLine CacheSet::find
::CStateString
::CacheCntlr::updateCacheBlock Cache::invalidateSingleLine
::CacheCntlr::retrieveCacheBlock Cache::accessSingleLine
::CacheCntlr::releaseStackLock ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::lastLevelCache
::CacheCntlr::writeCacheBlock ::CacheCntlr::acquireStackLock
DramDirectory
6.6.2.41 processInvReqFromDramDirectory()
void CacheCntlr::processInvReqFromDramDirectory (
core_id_t sender,
ParametricDramDirectoryMSI Cache::peekSingleLine CacheSet::find
::CStateString
ParametricDramDirectoryMSI Cache::invalidateSingleLine
::CacheCntlr::writeCacheBlock ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::getLock Cache::accessSingleLine
::CacheCntlr::retrieveCacheBlock ::CacheCntlr::getCacheBlockSize
DramDirectory
6.6.2.42 processMemOpFromCore()
HitWhere::where_t CacheCntlr::processMemOpFromCore (
Core::lock_signal_t lock_signal,
IntPtr ca_address,
UInt32 offset,
Byte data_buf,
UInt32 data_length,
bool modeled,
bool count )
::CacheCntlr::acquireLock ::CacheCntlr::isFirstLevel
::CacheCntlr::releaseLock ::CacheMasterCntlr::getSetLock
::CacheCntlr::accessCache ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::MemoryManager::incrElapsedTime
PrevCache
ParametricDramDirectoryMSI ::CStateString
::CacheCntlr::Prefetch ::CacheCntlr::operationPermissibleinCache CacheState::readable
CacheBlockInfo::getUsage CacheBlockInfo::updateUsage
Access
6.6.2.43 processShmemReqFromPrevCache()
HitWhere::where_t CacheCntlr::processShmemReqFromPrevCache (
CacheCntlr requester,
IntPtr address,
bool modeled,
bool count,
Prefetch::prefetch_type_t isPrefetch,
SubsecondTime t_issue,
bool have_write_lock ) [private]
::CacheCntlr::copyDataFromNextLevel ::CacheCntlr::setCacheState
CacheBlockInfo::getOwner ParametricDramDirectoryMSI
::MemoryManager::sendMsg Cache::peekSingleLine
PrevCache ::CacheCntlr::initiateDirectory
Access
SharedCacheBlockInfo ::CacheCntlr::accessDRAM
::invalidate
::CacheCntlr::updateCounters ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ::CacheCntlr::transition
::CacheMasterCntlr::accessATDs
::CacheCntlr::cleanupMshr
ParametricDramDirectoryMSI ::CStateString
::make_mshr ::CacheCntlr::trainPrefetcher
::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
PrevCache ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.44 processShRepFromDramDirectory()
void CacheCntlr::processShRepFromDramDirectory (
core_id_t sender,
::CStateString
CacheSet::find
Directory
::CacheCntlr::processShRepFromDram ::CacheCntlr::handleMsgFromDram
Directory Directory
6.6.2.45 processShReqToDirectory()
void CacheCntlr::processShReqToDirectory (
::CacheCntlr::processShReqToDirectory ::MemoryManager::sendMsg

::CacheCntlr::initiateDirectory ::CacheCntlr::processShmemReqFrom ::MemoryManager::coreInitiateMemory
::CacheCntlr::processShReqToDirectory ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access PrevCache Access
6.6.2.46 processUpgradeRepFromDramDirectory()
void CacheCntlr::processUpgradeRepFromDramDirectory (
core_id_t sender,
::CacheCntlr::processUpgradeRep ParametricDramDirectoryMSI
FromDramDirectory ::CacheCntlr::notifyPrevLevelEvict
::CStateString ParametricDramDirectoryMSI
::CacheCntlr::invalidateCacheBlock ::CacheCntlr::getCacheBlockInfo
Cache::invalidateSingleLine CacheSet::invalidate CacheBlockInfo::invalidate
ParametricDramDirectoryMSI ParametricDramDirectoryMSI CacheBase::splitAddress

6.6.2.47 processUpgradeReqToDirectory()
void CacheCntlr::processUpgradeReqToDirectory (
IntPtr address,
ShmemPerf perf,
::CacheCntlr::getCacheState Cache::peekSingleLine
CacheSet::find
ToDirectory
::CacheCntlr::initiateDirectory ::CacheCntlr::processShmemReqFrom ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Access PrevCache ::MemoryManager::coreInitiateMemory
ParametricDramDirectoryMSI ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore
Access
::CacheCntlr::processUpgradeReq ParametricDramDirectoryMSI ParametricDramDirectoryMSI
ToDirectory ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.48 processWbReqFromDramDirectory()
void CacheCntlr::processWbReqFromDramDirectory (
core_id_t sender,
::CacheCntlr::invalidateCacheBlock ParametricDramDirectoryMSI Cache::peekSingleLine CacheSet::find
::CStateString
::CacheCntlr::updateCacheBlock Cache::invalidateSingleLine
::CacheCntlr::retrieveCacheBlock Cache::accessSingleLine
::CacheCntlr::releaseStackLock ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::lastLevelCache
::CacheCntlr::writeCacheBlock ::CacheCntlr::acquireStackLock
Directory
Directory Directory
6.6.2.49 releaseLock()
void CacheCntlr::releaseLock (
UInt64 address )
::CacheCntlr::isFirstLevel
::CacheCntlr::releaseLock ::CacheCntlr::lastLevelCache
::CacheCntlr::releaseLock ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.50 releaseStackLock()
void CacheCntlr::releaseStackLock (
UInt64 address,
bool this_is_locked = false )
PrevCache
::CacheCntlr::accessCache ::CacheCntlr::processMemOpFromCore
Directory
Directory
FromDramDirectory
Directory
DramDirectory
DramDirectory
Directory
6.6.2.51 retrieveCacheBlock()
void CacheCntlr::retrieveCacheBlock (
IntPtr address,
Byte data_buf,
ShmemPerfModel::Thread_t thread_num,
bool update_replacement ) [private]
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::processShmemReqFrom
::CacheCntlr::retrieveCacheBlock ::CacheCntlr::copyDataFromNextLevel PrevCache
ParametricDramDirectoryMSI ::CacheCntlr::processMemOpFromCore ::MemoryManager::coreInitiateMemory
::CacheCntlr::processUpgradeRep Access
FromDramDirectory ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::updateCacheBlock ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::MemoryManager::handleMsgFromNetwork
DramDirectory
Directory
6.6.2.52 setCacheState()
SharedCacheBlockInfo CacheCntlr::setCacheState (
IntPtr address,
CacheState::cstate_t cstate ) [private]
ToDirectory Access
ParametricDramDirectoryMSI ::CacheCntlr::processExRepFromDram ::CacheCntlr::handleMsgFromDram ParametricDramDirectoryMSI
::CacheCntlr::setCacheState Directory Directory ::MemoryManager::handleMsgFromNetwork

::CacheCntlr::processShRepFromDram ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
PrevCache ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore
6.6.2.53 setDRAMDirectAccess()
void CacheCntlr::setDRAMDirectAccess (
DramCntlrInterface dram_cntlr,
UInt64 num_outstanding )
6.6.2.54 setNextCacheCntlr()
void ParametricDramDirectoryMSI::CacheCntlr::setNextCacheCntlr (
CacheCntlr next_cache_cntlr ) [inline]
::CacheCntlr::setNextCacheCntlr ::MemoryManager::MemoryManager
6.6.2.55 setPrevCacheCntlrs()
void CacheCntlr::setPrevCacheCntlrs (
CacheCntlrList & prev_cache_cntlrs )
::CacheCntlr::setPrevCacheCntlrs ::MemoryManager::MemoryManager
6.6.2.56 trainPrefetcher()
void CacheCntlr::trainPrefetcher (
IntPtr address,
bool cache_hit,
bool prefetch_hit,
SubsecondTime t_issue ) [private]
::CacheCntlr::getLock CacheBase::splitAddress
ParametricDramDirectoryMSI ParametricDramDirectoryMSI CacheSet::find
Prefetcher::getNextAddress
::CacheCntlr::trainPrefetcher ::CacheCntlr::getCacheState
::CStateString
::CacheCntlr::trainPrefetcher ::MemoryManager::coreInitiateMemory
Access
PrevCache
6.6.2.57 transition()
void CacheCntlr::transition (
IntPtr address,
Transition::reason_t reason,
CacheState::cstate_t old_state,
CacheState::cstate_t new_state ) [private]
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI PrevCache
::CacheCntlr::transition ::CacheCntlr::insertCacheBlock ::CacheCntlr::copyDataFromNextLevel
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI Access

Directory
::CacheCntlr::processShRepFromDram ParametricDramDirectoryMSI
Directory ::MemoryManager::handleMsgFromNetwork
Directory Directory
FromDramDirectory
DramDirectory
DramDirectory
6.6.2.58 updateCacheBlock()
std::pair< SubsecondTime, bool > CacheCntlr::updateCacheBlock (

IntPtr address,
CacheState::cstate_t cstate,
Transition::reason_t reason,
Byte out_buf,
ParametricDramDirectoryMSI Cache::peekSingleLine CacheSet::find
::CStateString
::CacheCntlr::processUpgradeRep ::CacheCntlr::processMemOpFromCore
PrevCache ::MemoryManager::coreInitiateMemory
FromDramDirectory ParametricDramDirectoryMSI Access ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::updateCacheBlock ParametricDramDirectoryMSI
DramDirectory ParametricDramDirectoryMSI
Directory
DramDirectory
Directory
6.6.2.59 updateCounters()
void CacheCntlr::updateCounters (
IntPtr address,
bool cache_hit,
CacheState::cstate_t state,
Prefetch::prefetch_type_t isPrefetch ) [private]
::CacheCntlr::updateCounters ::CacheCntlr::updateHits ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Access
PrevCache
6.6.2.60 updateHits()
void CacheCntlr::updateHits (
UInt64 hits )
::CacheCntlr::getCache ParametricDramDirectoryMSI
6.6.2.61 updateUncoreStatistics()
void CacheCntlr::updateUncoreStatistics (
HitWhere::where_t hit_where,
SubsecondTime now ) [private]
PrevCache ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore
::CacheCntlr::updateUncoreStatistics ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.62 updateUsageBits()
void CacheCntlr::updateUsageBits (
IntPtr address,
CacheBlockInfo::BitsUsedType used ) [private]
::CacheCntlr::updateUsageBits ::CacheCntlr::getCacheBlockInfo
CacheSet::find
::CacheCntlr::updateUsageBits ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.6.2.63 waitForNetworkThread()
void CacheCntlr::waitForNetworkThread (
void ) [private]
::CacheCntlr::waitForNetworkThread ::MemoryManager::coreInitiateMemory
Access
6.6.2.64 waitForUserThread()
void CacheCntlr::waitForUserThread (
Semaphore network_thread_sem = NULL ) [private]
::CacheCntlr::waitForUserThread ::MemoryManager::handleMsgFromNetwork ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.65 wakeUpNetworkThread()
void CacheCntlr::wakeUpNetworkThread (
void ) [private]
::CacheCntlr::wakeUpNetworkThread ::MemoryManager::coreInitiateMemory
Access
6.6.2.66 wakeUpUserThread()
void CacheCntlr::wakeUpUserThread (
Semaphore user_thread_sem = NULL ) [private]
::CacheCntlr::wakeUpUserThread ::MemoryManager::handleMsgFromNetwork ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Directory
6.6.2.67 walkUsageBits()
void CacheCntlr::walkUsageBits ( ) [private]
CacheBase::getNumSets
CacheSet::peekBlock
Cache::peekBlock
CacheBlockInfo::isValid
Cache::updateHits
6.6.2.68 writeCacheBlock()
void CacheCntlr::writeCacheBlock (
IntPtr address,
UInt32 offset,
Byte data_buf,
UInt32 data_length,
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CacheCntlr::processShmemReqFrom ::CacheCntlr::processMemOpFromCore
::CacheCntlr::writeCacheBlock ::CacheCntlr::insertCacheBlock ::CacheCntlr::copyDataFromNextLevel PrevCache ParametricDramDirectoryMSI
::CacheCntlr::doPrefetch ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::Prefetch ::MemoryManager::coreInitiateMemory
Access
Directory
Directory
Directory
FromDramDirectory
DramDirectory
6.6.3 Friends And Related Function Documentation
6.6.3.1 CacheCntlrList
friend class CacheCntlrList [friend]
6.6.3.2 MemoryManager
friend class MemoryManager [friend]
6.6.4.1 backinval
UInt64 ParametricDramDirectoryMSI::CacheCntlr::backinval[CacheState::NUM_CSTATE_STATES]
6.6.4.2 coherency_downgrades
UInt64 ParametricDramDirectoryMSI::CacheCntlr::coherency_downgrades
6.6.4.3 coherency_invalidates
UInt64 ParametricDramDirectoryMSI::CacheCntlr::coherency_invalidates
6.6.4.4 coherency_upgrades
UInt64 ParametricDramDirectoryMSI::CacheCntlr::coherency_upgrades
6.6.4.5 coherency_writebacks
UInt64 ParametricDramDirectoryMSI::CacheCntlr::coherency_writebacks
6.6.4.6 evict
UInt64 ParametricDramDirectoryMSI::CacheCntlr::evict[CacheState::NUM_CSTATE_STATES]
6.6.4.7 evict_prefetch
UInt64 ParametricDramDirectoryMSI::CacheCntlr::evict_prefetch
6.6.4.8 evict_warmup
UInt64 ParametricDramDirectoryMSI::CacheCntlr::evict_warmup
6.6.4.9 hits_prefetch
UInt64 ParametricDramDirectoryMSI::CacheCntlr::hits_prefetch
6.6.4.10 hits_warmup
UInt64 ParametricDramDirectoryMSI::CacheCntlr::hits_warmup
6.6.4.11 invalidate_prefetch
UInt64 ParametricDramDirectoryMSI::CacheCntlr::invalidate_prefetch
6.6.4.12 invalidate_warmup
UInt64 ParametricDramDirectoryMSI::CacheCntlr::invalidate_warmup
6.6.4.13 load_misses
UInt64 ParametricDramDirectoryMSI::CacheCntlr::load_misses
6.6.4.14 load_misses_state
UInt64 ParametricDramDirectoryMSI::CacheCntlr::load_misses_state[CacheState::NUM_CSTATE_STAT-
ES]
6.6.4.15 load_overlapping_misses
UInt64 ParametricDramDirectoryMSI::CacheCntlr::load_overlapping_misses
6.6.4.16 loads
UInt64 ParametricDramDirectoryMSI::CacheCntlr::loads
6.6.4.17 loads_prefetch
UInt64 ParametricDramDirectoryMSI::CacheCntlr::loads_prefetch
6.6.4.18 loads_state
UInt64 ParametricDramDirectoryMSI::CacheCntlr::loads_state[CacheState::NUM_CSTATE_STATES]
6.6.4.19 loads_where
UInt64 ParametricDramDirectoryMSI::CacheCntlr::loads_where[HitWhere::NUM_HITWHERES]
6.6.4.20 m_cache_block_size
UInt32 ParametricDramDirectoryMSI::CacheCntlr::m_cache_block_size [private]
6.6.4.21 m_cache_writethrough
bool ParametricDramDirectoryMSI::CacheCntlr::m_cache_writethrough [private]
6.6.4.22 m_coherent
bool ParametricDramDirectoryMSI::CacheCntlr::m_coherent [private]
6.6.4.23 m_core_id
core_id_t ParametricDramDirectoryMSI::CacheCntlr::m_core_id [private]
6.6.4.24 m_core_id_master
core_id_t ParametricDramDirectoryMSI::CacheCntlr::m_core_id_master [private]
Core id of the 'master' (actual) cache controller we're proxying
6.6.4.25 m_l1_mshr
bool ParametricDramDirectoryMSI::CacheCntlr::m_l1_mshr [private]
6.6.4.26 m_last_level
CacheCntlr ParametricDramDirectoryMSI::CacheCntlr::m_last_level [private]
6.6.4.27 m_last_remote_hit_where
volatile HitWhere::where_t ParametricDramDirectoryMSI::CacheCntlr::m_last_remote_hit_where

[private]
6.6.4.28 m_master
CacheMasterCntlr ParametricDramDirectoryMSI::CacheCntlr::m_master [private]
6.6.4.29 m_mem_component
MemComponent::component_t ParametricDramDirectoryMSI::CacheCntlr::m_mem_component [private]
6.6.4.30 m_memory_manager
MemoryManager ParametricDramDirectoryMSI::CacheCntlr::m_memory_manager [private]
6.6.4.31 m_network_thread_sem
Semaphore ParametricDramDirectoryMSI::CacheCntlr::m_network_thread_sem [private]
6.6.4.32 m_next_cache_cntlr
CacheCntlr ParametricDramDirectoryMSI::CacheCntlr::m_next_cache_cntlr [private]
6.6.4.33 m_next_level_read_bandwidth
ComponentBandwidthPerCycle ParametricDramDirectoryMSI::CacheCntlr::m_next_level_read_bandwidth
[private]
6.6.4.34 m_passthrough
bool ParametricDramDirectoryMSI::CacheCntlr::m_passthrough [private]
6.6.4.35 m_perfect
bool ParametricDramDirectoryMSI::CacheCntlr::m_perfect [private]
6.6.4.36 m_prefetch_on_prefetch_hit
bool ParametricDramDirectoryMSI::CacheCntlr::m_prefetch_on_prefetch_hit [private]
6.6.4.37 m_shared_cores
UInt32 ParametricDramDirectoryMSI::CacheCntlr::m_shared_cores [private]
Number of cores this cache is shared with
6.6.4.38 m_shmem_perf
ShmemPerf ParametricDramDirectoryMSI::CacheCntlr::m_shmem_perf [private]
6.6.4.39 m_shmem_perf_global
ShmemPerf ParametricDramDirectoryMSI::CacheCntlr::m_shmem_perf_global [private]
6.6.4.40 m_shmem_perf_model
ShmemPerfModel ParametricDramDirectoryMSI::CacheCntlr::m_shmem_perf_model [private]
6.6.4.41 m_shmem_perf_numrequests
UInt64 ParametricDramDirectoryMSI::CacheCntlr::m_shmem_perf_numrequests [private]
6.6.4.42 m_shmem_perf_totaltime
SubsecondTime ParametricDramDirectoryMSI::CacheCntlr::m_shmem_perf_totaltime [private]
6.6.4.43 m_shmem_req_source_map
std::unordered_map<IntPtr, MemComponent::component_t> ParametricDramDirectoryMSI::CacheCntlr-

::m_shmem_req_source_map [private]
6.6.4.44 m_tag_directory_home_lookup
AddressHomeLookup ParametricDramDirectoryMSI::CacheCntlr::m_tag_directory_home_lookup [private]
6.6.4.45 m_user_thread_sem
Semaphore ParametricDramDirectoryMSI::CacheCntlr::m_user_thread_sem [private]
6.6.4.46 m_writeback_time
ComponentLatency ParametricDramDirectoryMSI::CacheCntlr::m_writeback_time [private]
6.6.4.47 mshr_latency
SubsecondTime ParametricDramDirectoryMSI::CacheCntlr::mshr_latency
6.6.4.48 prefetches
UInt64 ParametricDramDirectoryMSI::CacheCntlr::prefetches
6.6.4.49 qbs_query_latency
SubsecondTime ParametricDramDirectoryMSI::CacheCntlr::qbs_query_latency
6.6.4.50 snoop_latency
SubsecondTime ParametricDramDirectoryMSI::CacheCntlr::snoop_latency
6.6.4.51 stats
struct { ... } ParametricDramDirectoryMSI::CacheCntlr::stats [private]
6.6.4.52 store_misses
UInt64 ParametricDramDirectoryMSI::CacheCntlr::store_misses
6.6.4.53 store_misses_state
UInt64 ParametricDramDirectoryMSI::CacheCntlr::store_misses_state[CacheState::NUM_CSTATE_STA-
TES]
6.6.4.54 store_overlapping_misses
UInt64 ParametricDramDirectoryMSI::CacheCntlr::store_overlapping_misses
6.6.4.55 stores
UInt64 ParametricDramDirectoryMSI::CacheCntlr::stores
6.6.4.56 stores_prefetch
UInt64 ParametricDramDirectoryMSI::CacheCntlr::stores_prefetch
6.6.4.57 stores_state
UInt64 ParametricDramDirectoryMSI::CacheCntlr::stores_state[CacheState::NUM_CSTATE_STATES]
6.6.4.58 stores_where
UInt64 ParametricDramDirectoryMSI::CacheCntlr::stores_where[HitWhere::NUM_HITWHERES]
6.6.4.59 total_latency
SubsecondTime ParametricDramDirectoryMSI::CacheCntlr::total_latency
cache_cntlr.h
cache_cntlr.cc
6.7 ParametricDramDirectoryMSI::CacheCntlrList Class Reference
Inheritance diagram for ParametricDramDirectoryMSI::CacheCntlrList:
std::vector< CacheCntlr * >
::CacheCntlrList
6.8 ParametricDramDirectoryMSI::CacheDirectoryWaiter Class Reference 105
Collaboration diagram for ParametricDramDirectoryMSI::CacheCntlrList:
std::vector< CacheCntlr * >
::CacheCntlrList
cache_cntlr.h
6.8 ParametricDramDirectoryMSI::CacheDirectoryWaiter Class Reference
Collaboration diagram for ParametricDramDirectoryMSI::CacheDirectoryWaiter:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_blocksize
# m_name
# m_lock
# m_cache_size
ReqQueueListTemplate + CacheSet() # m_associativity
< T_Req > + ~CacheSet() # m_blocksize
- m_req_queue_list
+ ReqQueueListTemplate() std::vector< CacheCntlr * > CacheSetInfo + getLock() # m_ahl
+ ~ReqQueueListTemplate() + read_line() # m_log_blocksize
+ enqueue() + write_line()
+ CacheBase()
+ dequeue() + ~CacheSetInfo() + find()
+ ~CacheBase()
+ front() + invalidate()
+ splitAddress()
+ back() + insert()
+ splitAddress()
+ size() + peekBlock()
+ tagToAddress()
+ empty() + getDataPtr()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
< CacheDirectoryWaiter > -m_set_info -m_sets
Cache
- m_enabled
- m_num_accesses
ReqQueueListTemplate - m_num_hits
< CacheDirectoryWaiter > - m_cache_type
- m_fault_injector
- m_req_queue_list
Prefetcher ParametricDramDirectoryMSI + Cache()
+ ReqQueueListTemplate() ::CacheCntlrList + ~Cache()
+ getSetLock()
+ enqueue()
+ getNextAddress() + invalidateSingleLine()
+ dequeue()
+ createPrefetcher() + accessSingleLine()
+ front()
+ back()
+ peekSingleLine()
+ size()
+ peekBlock()
+ empty()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_directory_waiters -m_prefetcher -m_prev_cache_cntlrs -m_cache -m_cache -m_cache
::CacheMasterCntlr
- m_cache_lock
- m_smt_lock
- m_dram_cntlr
_writebacks
- mshr
- m_l1_mshr
CacheCntlr - m_next_level_read_bandwidth
- m_evicting_buf
- m_atds
+ isInLowerLevelCache() - m_setlocks
+ incrementQBSLookupCost() - m_log_blocksize
- m_num_sets
- m_prefetch_list
- m_prefetch_next
- createSetLocks()
- getSetLock()
- createATDs()
- accessATDs()
NucaCache
- m_core_id
- m_memory_manager
- m_shmem_perf_model ParametricDramDirectoryMSI::TLB
- m_home_lookup
- m_cache_block_size - m_size
- m_data_access_time - m_associativity
- m_tags_access_time - m_access
- m_data_array_bandwidth - m_miss
-m_master - m_queue_model - SIM_PAGE_SHIFT -m_next_level
- m_reads - SIM_PAGE_SIZE
- m_writes - SIM_PAGE_MASK
- m_read_misses
- m_write_misses + TLB()
+ lookup()
+ NucaCache() + allocate()
+ ~NucaCache()
+ read()
+ write()
- accessDataArray()
::CacheCntlr
+ loads
+ stores
+ load_misses
+ store_misses
+ loads_state
+ stores_state
+ loads_where
+ stores_where
+ load_misses_state
+ loads_prefetch
+ stores_prefetch
+ hits_prefetch
+ evict_prefetch
+ evict
and 13 more...
- m_mem_component
_lookup
- m_perfect
- m_passthrough
- m_coherent
- m_l1_mshr
- stats
- m_core_id
- m_writeback_time
- m_shared_cores
- m_core_id_master
- m_user_thread_sem
- m_shmem_perf
- m_shmem_perf_totaltime MemoryManagerBase
- m_shmem_perf_numrequests -m_itlb
-m_next_cache_cntlr
- m_shmem_perf_model -m_nuca_cache -m_dtlb
-m_last_level
-m_stlb
+ CacheCntlr()
+ ~CacheCntlr()
+ getCache()
+ getLock()
+ createSetLocks()
+ updateHits()
+ acquireLock()
+ releaseLock()
+ isMasterCache()
+ isFirstLevel()
+ isLastLevel()
+ isShared()
+ enable()
+ disable()
- updateCounters()
- cleanupMshr()
- transition()
- accessCache()
- trainPrefetcher()
- Prefetch()
- doPrefetch()
- getCacheState()
- getCacheState()
- setCacheState()
and 26 more...
- __walkUsageBits()
+cache_cntlr -m_cache_cntlrs -m_memory_manager
::MemoryManager
- m_dram_cache
- m_dram_cntlr
_lookup
_lookup
- m_core_id_master
- m_user_thread_sem
- m_enabled
ParametricDramDirectoryMSI - m_all_cache_cntlrs
::CacheDirectoryWaiter + MemoryManager()
+ exclusive + ~MemoryManager()
+ isPrefetch + getCacheBlockSize()
+ t_issue + getCache()
+ getL1ICache()
+ CacheDirectoryWaiter() + getL1DCache()
+ getDramCntlr()
+ getCacheCntlrAt()
+ setCacheCntlrAt()
+ sendMsg()
+ broadcastMsg()
+ getL1HitLatency()
+ addL1Hits()
+ enableModels()
+ disableModels()
+ getCost()
+ incrElapsedTime()
+ incrElapsedTime()
- accessTLB()

CacheDirectoryWaiter (bool _exclusive, bool _isPrefetch, CacheCntlr _cache_cntlr, SubsecondTime _t_-
issue)
Public Attributes
bool exclusive
6.8 ParametricDramDirectoryMSI::CacheDirectoryWaiter Class Reference 107
bool isPrefetch
CacheCntlr cache_cntlr
SubsecondTime t_issue
6.8.1.1 CacheDirectoryWaiter()
ParametricDramDirectoryMSI::CacheDirectoryWaiter::CacheDirectoryWaiter (
bool _exclusive,
bool _isPrefetch,
CacheCntlr _cache_cntlr,
SubsecondTime _t_issue ) [inline]
6.8.2.1 cache_cntlr
CacheCntlr ParametricDramDirectoryMSI::CacheDirectoryWaiter::cache_cntlr
6.8.2.2 exclusive
bool ParametricDramDirectoryMSI::CacheDirectoryWaiter::exclusive
6.8.2.3 isPrefetch
bool ParametricDramDirectoryMSI::CacheDirectoryWaiter::isPrefetch
6.8.2.4 t_issue
SubsecondTime ParametricDramDirectoryMSI::CacheDirectoryWaiter::t_issue
cache_cntlr.h
6.9 ParametricDramDirectoryMSI::CacheMasterCntlr Class Reference
Collaboration diagram for ParametricDramDirectoryMSI::CacheMasterCntlr:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_blocksize
# m_name
# m_lock
# m_cache_size
ReqQueueListTemplate # m_associativity + CacheSet()
< T_Req > # m_blocksize + ~CacheSet()
- m_req_queue_list
std::vector< CacheCntlr * > + ReqQueueListTemplate() # m_ahl CacheSetInfo + getLock()
+ ~ReqQueueListTemplate() # m_log_blocksize + read_line()
+ enqueue() + write_line()
+ CacheBase()
+ dequeue() + ~CacheSetInfo() + find()
+ ~CacheBase()
+ front() + invalidate()
+ splitAddress()
+ back() + insert()
+ splitAddress()
+ size() + peekBlock()
+ tagToAddress()
+ empty() + getDataPtr()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
< CacheDirectoryWaiter > -m_set_info -m_sets
Cache
- m_enabled
- m_num_accesses
ReqQueueListTemplate - m_num_hits
< CacheDirectoryWaiter > - m_cache_type
- m_fault_injector
- m_req_queue_list
Prefetcher ParametricDramDirectoryMSI
+ Cache()
+ ~Cache()
+ getSetLock()
+ enqueue()
+ getNextAddress() + invalidateSingleLine()
+ dequeue()
+ createPrefetcher() + accessSingleLine()
+ front()
+ back()
+ peekSingleLine()
+ size()
+ peekBlock()
+ empty()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_prefetcher -m_prev_cache_cntlrs -m_directory_waiters -m_cache
::CacheMasterCntlr
- m_cache_lock
- m_smt_lock
- m_dram_cntlr
_writebacks
- mshr
- m_l1_mshr
- m_evicting_buf
- m_atds
- m_setlocks
- m_log_blocksize
- m_num_sets
- m_prefetch_list
- m_prefetch_next
- createSetLocks()
- getSetLock()
- createATDs()
- accessATDs()
void createSetLocks (UInt32 cache_block_size, UInt32 num_sets, UInt32 core_offset, UInt32 num_cores)
SetLock getSetLock (IntPtr addr)
6.9 ParametricDramDirectoryMSI::CacheMasterCntlr Class Reference 109
void createATDs (String name, String configName, core_id_t core_id, UInt32 shared_cores, UInt32 size,
UInt32 associativity, UInt32 block_size, String replacement_policy, CacheBase::hash_t hash_function)
void accessATDs (Core::mem_op_t mem_op_type, bool hit, IntPtr address, UInt32 core_num)
CacheMasterCntlr (String name, core_id_t core_id, UInt32 outstanding_misses)
CacheMasterCntlr ()
Private Attributes
Cache m_cache
Lock m_cache_lock
Lock m_smt_lock
CacheCntlrList m_prev_cache_cntlrs
Prefetcher m_prefetcher
DramCntlrInterface m_dram_cntlr
ContentionModel m_dram_outstanding_writebacks
Mshr mshr
ContentionModel m_l1_mshr
ContentionModel m_next_level_read_bandwidth
CacheDirectoryWaiterMap m_directory_waiters
IntPtr m_evicting_address
Byte m_evicting_buf
std::vector< ATD > m_atds
std::vector< SetLock > m_setlocks
UInt32 m_log_blocksize
UInt32 m_num_sets
std::deque< IntPtr > m_prefetch_list
SubsecondTime m_prefetch_next
Friends
class CacheCntlr
6.9.1.1 CacheMasterCntlr()
ParametricDramDirectoryMSI::CacheMasterCntlr::CacheMasterCntlr (
String name,
core_id_t core_id,
UInt32 outstanding_misses ) [inline], [private]
6.9.1.2 CacheMasterCntlr()
ParametricDramDirectoryMSI::CacheMasterCntlr::CacheMasterCntlr ( ) [private]
6.9.2.1 accessATDs()
void ParametricDramDirectoryMSI::CacheMasterCntlr::accessATDs (
bool hit,
IntPtr address,
UInt32 core_num ) [private]

::CacheMasterCntlr::accessATDs ::CacheCntlr::updateCounters ::CacheCntlr::updateHits ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
Access
PrevCache
6.9.2.2 createATDs()
void ParametricDramDirectoryMSI::CacheMasterCntlr::createATDs (
String name,
String configName,
core_id_t core_id,
UInt32 shared_cores,
UInt32 size,
UInt32 block_size,
CacheBase::hash_t hash_function ) [private]
::CacheMasterCntlr::createATDs ::CacheCntlr::CacheCntlr
6.9.2.3 createSetLocks()
void ParametricDramDirectoryMSI::CacheMasterCntlr::createSetLocks (
UInt32 num_sets,
UInt32 core_offset,
UInt32 num_cores ) [private]
::CacheMasterCntlr::createSetLocks ::CacheCntlr::createSetLocks
6.9.2.4 getSetLock()
SetLock ParametricDramDirectoryMSI::CacheMasterCntlr::getSetLock (
IntPtr addr ) [private]
PrevCache ::CacheCntlr::doPrefetch ::CacheCntlr::Prefetch
Directory
Access
DramDirectory
ParametricDramDirectoryMSI ::CacheCntlr::processWbReqFromDram ::CacheCntlr::handleMsgFromDram
::CacheCntlr::acquireStackLock Directory Directory ParametricDramDirectoryMSI ParametricDramDirectoryMSI
FromDramDirectory
DramDirectory
6.9.3 Friends And Related Function Documentation
6.9.3.1 CacheCntlr
friend class CacheCntlr [friend]
6.9.4.1 m_atds
std::vector<ATD> ParametricDramDirectoryMSI::CacheMasterCntlr::m_atds [private]
6.9.4.2 m_cache
Cache ParametricDramDirectoryMSI::CacheMasterCntlr::m_cache [private]
6.9.4.3 m_cache_lock
Lock ParametricDramDirectoryMSI::CacheMasterCntlr::m_cache_lock [private]
6.9.4.4 m_directory_waiters
CacheDirectoryWaiterMap ParametricDramDirectoryMSI::CacheMasterCntlr::m_directory_waiters
[private]
6.9.4.5 m_dram_cntlr
DramCntlrInterface ParametricDramDirectoryMSI::CacheMasterCntlr::m_dram_cntlr [private]
6.9.4.6 m_dram_outstanding_writebacks
ContentionModel ParametricDramDirectoryMSI::CacheMasterCntlr::m_dram_outstanding_writebacks
[private]
6.9.4.7 m_evicting_address
IntPtr ParametricDramDirectoryMSI::CacheMasterCntlr::m_evicting_address [private]
6.9.4.8 m_evicting_buf
Byte ParametricDramDirectoryMSI::CacheMasterCntlr::m_evicting_buf [private]
6.9.4.9 m_l1_mshr
ContentionModel ParametricDramDirectoryMSI::CacheMasterCntlr::m_l1_mshr [private]
6.9.4.10 m_log_blocksize
UInt32 ParametricDramDirectoryMSI::CacheMasterCntlr::m_log_blocksize [private]
6.9.4.11 m_next_level_read_bandwidth
ContentionModel ParametricDramDirectoryMSI::CacheMasterCntlr::m_next_level_read_bandwidth
[private]
6.9.4.12 m_num_sets
UInt32 ParametricDramDirectoryMSI::CacheMasterCntlr::m_num_sets [private]
6.9.4.13 m_prefetch_list
std::deque<IntPtr> ParametricDramDirectoryMSI::CacheMasterCntlr::m_prefetch_list [private]
6.9.4.14 m_prefetch_next
SubsecondTime ParametricDramDirectoryMSI::CacheMasterCntlr::m_prefetch_next [private]
6.9.4.15 m_prefetcher
Prefetcher ParametricDramDirectoryMSI::CacheMasterCntlr::m_prefetcher [private]
6.9.4.16 m_prev_cache_cntlrs
CacheCntlrList ParametricDramDirectoryMSI::CacheMasterCntlr::m_prev_cache_cntlrs [private]
6.9.4.17 m_setlocks
std::vector<SetLock> ParametricDramDirectoryMSI::CacheMasterCntlr::m_setlocks [private]
6.9.4.18 m_smt_lock
Lock ParametricDramDirectoryMSI::CacheMasterCntlr::m_smt_lock [private]
6.9.4.19 mshr
Mshr ParametricDramDirectoryMSI::CacheMasterCntlr::mshr [private]
cache_cntlr.h
cache_cntlr.cc
6.10 ParametricDramDirectoryMSI::CacheParameters Class Reference 115
6.10 ParametricDramDirectoryMSI::CacheParameters Class Reference
Collaboration diagram for ParametricDramDirectoryMSI::CacheParameters:
::CacheParameters
+ configName
+ size
+ num_sets
+ associativity
+ hash_function
+ replacement_policy
+ perfect
+ coherent
+ data_access_time
+ tags_access_time
+ writeback_time
+ next_level_read_bandwidth
+ perf_model_type
+ writethrough
+ shared_cores
+ prefetcher
+ outstanding_misses
+ CacheParameters()
+ CacheParameters()
CacheParameters ()
CacheParameters (String _configName, UInt32 _size, UInt32 _associativity, UInt32 block_size, String _-
hash_function, String _replacement_policy, bool _perfect, bool _coherent, const ComponentLatency &_-
data_access_time, const ComponentLatency &_tags_access_time, const ComponentLatency &_writeback-
_time, const ComponentBandwidthPerCycle &_next_level_read_bandwidth, String _perf_model_type, bool
_writethrough, UInt32 _shared_cores, String _prefetcher, UInt32 _outstanding_misses)
Public Attributes
String configName
UInt32 size
UInt32 num_sets
UInt32 associativity
String hash_function
String replacement_policy
bool perfect
bool coherent
ComponentLatency data_access_time
ComponentLatency tags_access_time
ComponentLatency writeback_time
ComponentBandwidthPerCycle next_level_read_bandwidth
String perf_model_type
bool writethrough
UInt32 shared_cores
String prefetcher
UInt32 outstanding_misses
6.10.1.1 CacheParameters() [1/2]
ParametricDramDirectoryMSI::CacheParameters::CacheParameters ( ) [inline]
6.10.1.2 CacheParameters() [2/2]
ParametricDramDirectoryMSI::CacheParameters::CacheParameters (
String _configName,
UInt32 _size,
UInt32 _associativity,
UInt32 block_size,
String _hash_function,
String _replacement_policy,
bool _perfect,
bool _coherent,
const ComponentLatency & _data_access_time,
const ComponentLatency & _tags_access_time,
const ComponentLatency & _writeback_time,
const ComponentBandwidthPerCycle & _next_level_read_bandwidth,
String _perf_model_type,
bool _writethrough,
UInt32 _shared_cores,
String _prefetcher,
UInt32 _outstanding_misses ) [inline]
6.10.2.1 associativity
UInt32 ParametricDramDirectoryMSI::CacheParameters::associativity
6.10 ParametricDramDirectoryMSI::CacheParameters Class Reference 117
6.10.2.2 coherent
bool ParametricDramDirectoryMSI::CacheParameters::coherent
6.10.2.3 configName
String ParametricDramDirectoryMSI::CacheParameters::configName
6.10.2.4 data_access_time
ComponentLatency ParametricDramDirectoryMSI::CacheParameters::data_access_time
6.10.2.5 hash_function
String ParametricDramDirectoryMSI::CacheParameters::hash_function
6.10.2.6 next_level_read_bandwidth
ComponentBandwidthPerCycle ParametricDramDirectoryMSI::CacheParameters::next_level_read_-
bandwidth
6.10.2.7 num_sets
UInt32 ParametricDramDirectoryMSI::CacheParameters::num_sets
6.10.2.8 outstanding_misses
UInt32 ParametricDramDirectoryMSI::CacheParameters::outstanding_misses
6.10.2.9 perf_model_type
String ParametricDramDirectoryMSI::CacheParameters::perf_model_type
6.10.2.10 perfect
bool ParametricDramDirectoryMSI::CacheParameters::perfect
6.10.2.11 prefetcher
String ParametricDramDirectoryMSI::CacheParameters::prefetcher
6.10.2.12 replacement_policy
String ParametricDramDirectoryMSI::CacheParameters::replacement_policy
6.10.2.13 shared_cores
UInt32 ParametricDramDirectoryMSI::CacheParameters::shared_cores
6.10.2.14 size
UInt32 ParametricDramDirectoryMSI::CacheParameters::size
6.10.2.15 tags_access_time
ComponentLatency ParametricDramDirectoryMSI::CacheParameters::tags_access_time
6.10.2.16 writeback_time
ComponentLatency ParametricDramDirectoryMSI::CacheParameters::writeback_time
6.11 CacheSet Class Reference 119
6.10.2.17 writethrough
bool ParametricDramDirectoryMSI::CacheParameters::writethrough
cache_cntlr.h
6.11 CacheSet Class Reference
Cache_Set class.
#include <cache_set.h>
Inheritance diagram for CacheSet:
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_cache_block_info
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetEWSRRIP
CacheSetEWLRU + m_rrip_flag
+ m_rrip_W_index CacheSetSRRIP
+ m_stored_EW_type
+ m_rrip_RW_index CacheSetMRUT
+ m_lru_W_index CacheSetLRU
+ m_rrip_R_index CacheSetNRU - m_rrip_numbits
+ m_lru_RW_index CacheSetNMRU
- m_rrip_numbits CacheSetMRU - m_lru_bits CacheSetPLRU CacheSetRandom CacheSetRoundRobin - m_rrip_max
+ m_lru_R_index # m_num_attempts
- m_rrip_max - m_mru_bits - m_lru_bits - m_rrip_insert
# m_num_attempts # m_lru_bits - m_lru_bits
- m_rrip_insert - m_lru_bits - m_rand - m_num_bits_set -b - m_rand - m_replacement_index - m_num_attempts
# m_lru_bits # m_set_info - m_replacement_pointer
- m_num_attempts - m_replacement_pointer - m_rrip_bits
# m_set_info + CacheSetMRU() + CacheSetMRUT() + CacheSetPLRU() + CacheSetRandom() + CacheSetRoundRobin()
- m_rrip_bits + CacheSetLRU() + CacheSetNMRU() - m_replacement_pointer
- m_replacement_pointer + ~CacheSetMRU() + ~CacheSetMRUT() + CacheSetNRU() + ~CacheSetPLRU() + ~CacheSetRandom() + ~CacheSetRoundRobin() - m_set_info
+ CacheSetEWLRU() + ~CacheSetLRU() + ~CacheSetNMRU()
- m_set_info + getReplacementIndex() + getReplacementIndex() + ~CacheSetNRU() + getReplacementIndex() + getReplacementIndex() + getReplacementIndex()
+ ~CacheSetEWLRU() + getReplacementIndex() + getReplacementIndex()
+ updateReplacementIndex() + updateReplacementIndex() + getReplacementIndex() + updateReplacementIndex() + updateReplacementIndex() + updateReplacementIndex() + CacheSetSRRIP()
+ getReplacementIndex() + updateReplacementIndex() + updateReplacementIndex()
+ CacheSetEWSRRIP() + updateReplacementForFetched + updateReplacementIndex() + ~CacheSetSRRIP()
+ updateReplacementIndex() # moveToMRU()
+ ~CacheSetEWSRRIP() Index() + getReplacementIndex()
# moveToMRU()
+ getReplacementIndex() + updateReplacementIndex()
# evictEW()
# updateEW()
# evictEW()
# updateEW()
Collaboration diagram for CacheSet:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
Public Types
enum ew_access_t { EMPTY = 0, WRITE = 1, READ = 2 }

A public enum variable.
CacheSet (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

A constructor.
virtual CacheSet ()
A destructor.
UInt32 getBlockSize ()
UInt32 getAssociativity ()
Lock & getLock ()
void read_line (UInt32 line_index, UInt32 offset, Byte out_buff, UInt32 bytes, bool update_replacement)
A read line method is called when the block is found and read process is sent from CPU- hit.
void write_line (UInt32 line_index, UInt32 offset, Byte in_buff, UInt32 bytes, bool update_replacement)
A write line method is called when the block is found and write process is sent from CPU- hit-.
CacheBlockInfo find (IntPtr tag, UInt32 line_index=NULL)
bool invalidate (IntPtr &tag)
void insert (CacheBlockInfo cache_block_info, Byte fill_buff, bool eviction, CacheBlockInfo evict_block-
_info, Byte evict_buff, CacheCntlr cntlr=NULL)
When it is cache miss, this method will be called.
CacheBlockInfo peekBlock (UInt32 way) const
char getDataPtr (UInt32 line_index, UInt32 offset=0)
UInt32 getBlockSize (void) const
virtual UInt32 getReplacementIndex (CacheCntlr cntlr)=0
virtual void updateReplacementIndex (UInt32)=0
bool isValidReplacement (UInt32 index)
static CacheSet createCacheSet (String cfgname, core_id_t core_id, String replacement_policy, Cache-
Base::cache_t cache_type, UInt32 associativity, UInt32 blocksize, CacheSetInfo set_info=NULL)
create Cache Set
static CacheSetInfo createCacheSetInfo (String name, String cfgname, core_id_t core_id, String
replacement_policy, UInt32 associativity)
static CacheBase::ReplacementPolicy parsePolicyType (String policy)
static UInt8 getNumQBSAttempts (CacheBase::ReplacementPolicy, String cfgname, core_id_t core_id)
Public Attributes
UInt32 m_coming_EW_type
A public variable.
UInt32 m_block_op
A public variable.
CacheBlockInfo m_cache_block_info_array
char m_blocks
UInt32 m_blocksize
Lock m_lock
Cache_Set class.
Everything related to cache sets. When the pointer of the execution reaches this class's methods, this means the
CPU wants to access or insert a specific block in a set. Per-cache object to store replacement-policy related info
(e.g. statistics), can collect data from all CacheSet objects which are per set and implement the actual replacement
policy
6.11.2.1 ew_access_t
enum CacheSet::ew_access_t
A public enum variable.
we use this variable save the EW access types
Enumerator
EMPTY
WRITE
READ
6.11.3.1 CacheSet()
CacheSet::CacheSet (
CacheBase::cache_t cache_type,
UInt32 blocksize )
A constructor.
The constructor wil be use to initialize "m_block_op" array and "m_coming_EW_type" to EMPTY. Here is the call
graph for this function:
CacheSet::CacheSet CacheBlockInfo::create
6.11.3.2 CacheSet()
CacheSet::CacheSet ( ) [virtual]
A destructor.
Free "m_block_op" array from the data that acquired during its lifetime.
6.11.4.1 createCacheSet()
CacheSet CacheSet::createCacheSet (
String cfgname,
core_id_t core_id,
UInt32 blocksize,
CacheSetInfo set_info = NULL ) [static]
create Cache Set

we added the new three replacement policy name so they can be used in separately without affecting the original
Sniper files. EW_LRU, MRUT, and EW_SRRIP. Here is the call graph for this function:
CacheSet::parsePolicyType
CacheSet::createCacheSet
CacheSet::getNumQBSAttempts
Cache::Cache
CacheSet::createCacheSet
ATD::ATD
6.11.4.2 createCacheSetInfo()
CacheSetInfo CacheSet::createCacheSetInfo (
String name,
String cfgname,
core_id_t core_id,
UInt32 associativity ) [static]
CacheSet::createCacheSetInfo
Cache::Cache
CacheSet::createCacheSetInfo
ATD::ATD
6.11.4.3 find()
CacheBlockInfo CacheSet::find (
IntPtr tag,
UInt32 line_index = NULL )
::CacheCntlr::notifyPrevLevelInsert ::CacheCntlr::trainPrefetcher
ParametricDramDirectoryMSI ::CacheCntlr::Prefetch ::CacheCntlr::processMemOpFromCore
NucaCache::read ParametricDramDirectoryMSI
Cache::peekSingleLine ::CacheCntlr::processShmemReqFrom
PrevCache
CacheSet::find NucaCache::write ::CacheCntlr::setCacheState ::CacheCntlr::insertCacheBlock
Cache::insertSingleLine ParametricDramDirectoryMSI ParametricDramDirectoryMSI

::CacheCntlr::notifyPrevLevelEvict ::CacheCntlr::copyDataFromNextLevel
Directory
ToDirectory Access
::CacheCntlr::getCacheState ::CacheCntlr::processExRepFromDram
Directory
Directory Directory
ParametricDramDirectoryMSI ::MemoryManager::accessTLB Access
::CacheCntlr::updateCacheBlock ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::processUpgradeRep ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
FromDramDirectory
DramDirectory
::CacheCntlr::processInvReqFrom ::TLB::lookup
DramDirectory
::TLB::allocate
6.11.4.4 getAssociativity()
UInt32 CacheSet::getAssociativity ( ) [inline]
6.11.4.5 getBlockSize() [1/2]
UInt32 CacheSet::getBlockSize ( ) [inline]
6.11.4.6 getBlockSize() [2/2]
UInt32 CacheSet::getBlockSize (
void ) const [inline]
6.11.4.7 getDataPtr()
char CacheSet::getDataPtr (
UInt32 line_index,
UInt32 offset = 0 )
6.11.4.8 getLock()
Lock& CacheSet::getLock ( ) [inline]
CacheSet::getLock Cache::getSetLock
6.11.4.9 getNumQBSAttempts()
UInt8 CacheSet::getNumQBSAttempts (
CacheBase::ReplacementPolicy policy,
String cfgname,
core_id_t core_id ) [static]
CacheSet::createCacheSet Cache::Cache
CacheSet::createCacheSetInfo ATD::ATD
6.11.4.10 getReplacementIndex()
virtual UInt32 CacheSet::getReplacementIndex (

CacheCntlr cntlr ) [pure virtual]
Implemented in CacheSetLRU, CacheSetEWSRRIP, CacheSetEWLRU, CacheSetMRUT, CacheSetSRRIP,

CacheSetMRU, CacheSetNMRU, CacheSetNRU, CacheSetPLRU, CacheSetRandom, and CacheSetRound-
Robin.
::TLB::lookup
CacheSet::getReplacement ParametricDramDirectoryMSI ::MemoryManager::coreInitiateMemory
Index ::CacheCntlr::insertCacheBlock Access
NucaCache::write
PrevCache
6.11.4.11 insert()
void CacheSet::insert (
CacheBlockInfo cache_block_info,
Byte fill_buff,
bool eviction,
CacheBlockInfo evict_block_info,
Byte evict_buff,
CacheCntlr cntlr = NULL )
When it is cache miss, this method will be called.
On miss, the cache will get the index that will be evicted from the cache set.In order to get the victim index, the
"insert" method will call getReplacementIndex method from the specified replacement policy in the command line.
Index
CacheSet::insert CacheBlockInfo::getTag
Directory
NucaCache::write
PrevCache
bool CacheSet::invalidate (
IntPtr & tag )
CacheSet::invalidate Cache::invalidateSingleLine
FromDramDirectory
DramDirectory
Directory
6.11.4.13 isValidReplacement()
bool CacheSet::isValidReplacement (
UInt32 index )
CacheSetEWLRU::getReplacement
Index
Index
CacheSetMRU::getReplacement
Index
CacheSetNMRU::getReplacement
Index
CacheSetNRU::getReplacement
CacheSet::isValidReplacement
Index
CacheSetPLRU::getReplacement
Index
CacheSetRandom::getReplacement
Index
CacheSetRoundRobin
::getReplacementIndex
Index
6.11.4.14 parsePolicyType()
CacheBase::ReplacementPolicy CacheSet::parsePolicyType (
String policy ) [static]
CacheSet::createCacheSet Cache::Cache
CacheSet::createCacheSetInfo ATD::ATD
6.11.4.15 peekBlock()
CacheBlockInfo CacheSet::peekBlock (
UInt32 way ) const [inline]
CacheSet::peekBlock Cache::peekBlock
6.11.4.16 read_line()
void CacheSet::read_line (
UInt32 line_index,
UInt32 offset,
Byte out_buff,
UInt32 bytes,
A read line method is called when the block is found and read process is sent from CPU- hit.
For EW-SRRIP :the m_block_op array will save the operation corresponded to the line(block)index. 1 is read, 2 for
write, and 3 for both
For EW-LRU : "m_coming_EW_type" will be set to ew_access_t(READ=2), so we can check this in the EWLRU
replacement policy class when this method is invoked during a hit and the operation is read. The m_block_op array
will save the operation corresponded to the line(block)index. 1 is read, 2 for write, and 3 for bothHere is the call
graph for this function:
CacheSet::updateReplacement
CacheSet::read_line
Index
6.11.4.17 updateReplacementIndex()
virtual void CacheSet::updateReplacementIndex (

UInt32 ) [pure virtual]
Implemented in CacheSetLRU, CacheSetEWSRRIP, CacheSetEWLRU, CacheSetMRUT, CacheSetSRRIP,

CacheSetMRU, CacheSetNMRU, CacheSetNRU, CacheSetPLRU, CacheSetRandom, and CacheSetRound-
Robin.
CacheSet::read_line
Index
CacheSet::write_line
6.11.4.18 write_line()
void CacheSet::write_line (
UInt32 line_index,
UInt32 offset,
Byte in_buff,
UInt32 bytes,
A write line method is called when the block is found and write process is sent from CPU- hit-.
For EW-SRRIP :the m_block_op array will save the operation corresponded to the line(block)index. 1 is read, 2 for
write, and 3 for both
For EW-LRU : "m_coming_EW_type" will be set to ew_access_t(WRITE = 1), so we can check this in the EWLRU
replacement policy class when this method is invoked when we got a hit and the operation is write. The m_block_op
array will save the operation corresponded to the line(block)index. 1 is read, 2 for write, and 3 for both Here is the
call graph for this function:
CacheSet::write_line
Index
UInt32 CacheSet::m_associativity [protected]
6.11.5.2 m_block_op
UInt32 CacheSet::m_block_op
A public variable.
We use this variable as array for W-SRRIP index access types
6.11.5.3 m_blocks
char CacheSet::m_blocks [protected]
6.11.5.4 m_blocksize
UInt32 CacheSet::m_blocksize [protected]
6.11.5.5 m_cache_block_info_array
CacheBlockInfo CacheSet::m_cache_block_info_array [protected]
6.11.5.6 m_coming_EW_type
UInt32 CacheSet::m_coming_EW_type
A public variable.
We use this variable as array for EW-LRU access type
6.11.5.7 m_lock
Lock CacheSet::m_lock [protected]
cache_set.h
cache_set.cc
6.12 CacheSetEWLRU Class Reference
EW-LRU: Evict Write strategy for Least Recently Used cache replacement policy.
#include <cache_set_ew_lru.h>
6.12 CacheSetEWLRU Class Reference 133
Inheritance diagram for CacheSetEWLRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetEWLRU
+ m_stored_EW_type
+ m_lru_W_index
+ m_lru_RW_index
+ m_lru_R_index
# m_num_attempts
# m_lru_bits
# m_set_info
+ CacheSetEWLRU()
+ ~CacheSetEWLRU()
# moveToMRU()
# evictEW()
# updateEW()
Collaboration diagram for CacheSetEWLRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
CacheSetInfo
+ clone()
+ isValid()
+ getTag()
+ getCState() + ~CacheSetInfo()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet() CacheSetInfoLRU
+ getBlockSize()
+ getAssociativity() CacheSetEWLRU::ew_array - m_associativity
+ getLock() - m_access
+ read_line() + was_read - m_attempts
+ write_line() + was_written
+ CacheSetInfoLRU()
+ find()
+ ~CacheSetInfoLRU()
+ invalidate()
+ increment()
+ insert()
+ incrementAttempt()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
+m_stored_EW_type #m_set_info
CacheSetEWLRU
+ m_lru_W_index
+ m_lru_RW_index
+ m_lru_R_index
# m_num_attempts
# m_lru_bits
+ CacheSetEWLRU()
+ ~CacheSetEWLRU()
# moveToMRU()
# evictEW()
# updateEW()
Classes
struct ew_array
A public struct variable.
CacheSetEWLRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize, CacheSetInfo-

LRU set_info, UInt8 num_attempts)
A constructor.
virtual CacheSetEWLRU ()
A destructor.
virtual UInt32 getReplacementIndex (CacheCntlr cntlr)
1- When there is a valid block in the cache set.
void updateReplacementIndex (UInt32 accessed_index)
updateReplacementIndex() will be invoked if we got a hit from CacheSet::read_line() or CacheSet::wite_line() meth-
ods
Public Attributes
struct ew_array m_stored_EW_type

SInt32 m_lru_W_index
A public variable.
SInt32 m_lru_RW_index
A public variable.
SInt32 m_lru_R_index
A public variable.
Protected Member Functions
void moveToMRU (UInt32 accessed_index)

Method responsible to move the block to MRU position. the MRU is index "0" in m_lru_bits array, which will be send
back to CacheSet::insert method.
UInt32 evictEW ()
evictEW() method for return the type of the operation that happened in the block
void updateEW (UInt32 accessed_index)
const UInt8 m_num_attempts

UInt8 m_lru_bits
CacheSetInfoLRU m_set_info
EWLRU eviction decision evicts the LRU block that was reused by write operation since it was brought in the cache.
If there are no blocks in the set are reused by writes, blocks that have both read and written are the next candidates
for replacement. If there are no block had both read and write, then the strategy fallbacks to LRU eviction for the
read blocks. When the candidate has been chosen, then evict it and replace it by the new block which will move to
the MRU position
6.12.2.1 CacheSetEWLRU()
CacheSetEWLRU::CacheSetEWLRU (
UInt32 blocksize,
CacheSetInfoLRU set_info,
UInt8 num_attempts )
A constructor.
"m_stored_EW_type" is of the type struct ew_array. It has two bool values "was_read" and "was_write", and they
will be initialized to false.
6.12.2.2 CacheSetEWLRU()
CacheSetEWLRU::CacheSetEWLRU ( ) [virtual]
A destructor.
Free m_lru_bits and m_stored_EW_type from the data that acquired during their lifetime.
6.12.3.1 evictEW()
UInt32 CacheSetEWLRU::evictEW ( ) [protected]
looping through a loop "m_associativity" times
1- Search through the "m_stored_EW_type array"
2.1- If the index is found with "m_stored_EW_type.was_read" and "m_stored_EW_type.was_written" are ture , then
save it in "m_lru_RW_index"
2.2- If the index is with only "m_stored_EW_type.was_read" being true, then save it in "m_lru_R_index" variable
2.3- If the index is with only "m_stored_EW_type[i].was_written" being true, then save it in " m_lru_W_index" variable
2.4- keep repeating and looping through the entire set to get the LRU blocks
when the loop is done, check the following :
3.1- Check if block with write operation was found then return it
3.2- Check if block with both operations was found then return it
3.3- Check if block with read operation was found then return it
Returns
The victim block to be evicted
CacheSetEWLRU::evictEW
Index
UInt32 CacheSetEWLRU::getReplacementIndex (
CacheCntlr cntlr ) [virtual]
1- When there is a valid block in the cache set.
getReplacementIndex method will first uses loop and checks if there is an invalid line(s) in the set. When a block
is found, the block will be moved to MRU and then the new block will overwritten it in the CacheSet::insert method.
Next, updateEW() will be called to update m_stored_EW_type variable.
See also
updateEW()
Returns
The victim block to be evicted2- No valid block in the cache set
If there is no valid block, then calling evictEW() method will be made to find the right block. When a block is found,
the block will be moved to MRU and then the new block will overwritten it in the CacheSet::insert method. Then later
updateEW() will be called to update m_stored_EW_type variable.
See also
updateEW() , evictEW()
Returns
Implements CacheSet.
CacheSetEWLRU::moveToMRU
CacheSetEWLRU::updateEW
Index
CacheSetEWLRU::evictEW
6.12.3.3 moveToMRU()
void CacheSetEWLRU::moveToMRU (
UInt32 accessed_index ) [protected]
Method responsible to move the block to MRU position. the MRU is index "0" in m_lru_bits array, which will be send
back to CacheSet::insert method.
Index
CacheSetEWLRU::updateReplacement
Index
6.12.3.4 updateEW()
void CacheSetEWLRU::updateEW (
To update m_stored_EW_type array, we check first if CacheSet::m_coming_EW_type variable equals to either

CacheSet::READ or CacheSet::WRITE Then m_stored_EW_type bool values will be updated corresponding to
the calling method.
See also:
See also
CacheSet::read_line()
CacheSet::write_line()
Index
Index
void CacheSetEWLRU::updateReplacementIndex (
UInt32 accessed_index ) [virtual]

ods
The accessed block will be updated by moving to MRU position. Then later updateEW() will be called to update
m_stored_EW_type variable. See also:
See also
updateEW()
CacheSetInfoLRU::increment
Index
6.12.4.1 m_lru_bits
UInt8 CacheSetEWLRU::m_lru_bits [protected]
6.12.4.2 m_lru_R_index
SInt32 CacheSetEWLRU::m_lru_R_index
A public variable.
we use this variable to assign the type of the read operation that was done on a block
6.12.4.3 m_lru_RW_index
SInt32 CacheSetEWLRU::m_lru_RW_index
A public variable.
we use this variable to assign the type of the read/ write operation that was done on a block
6.12.4.4 m_lru_W_index
SInt32 CacheSetEWLRU::m_lru_W_index
A public variable.
we use the variable to assign the type of the write operation that was done on a block
6.13 CacheSetEWSRRIP Class Reference 141
6.12.4.5 m_num_attempts
const UInt8 CacheSetEWLRU::m_num_attempts [protected]
6.12.4.6 m_set_info
CacheSetInfoLRU CacheSetEWLRU::m_set_info [protected]
6.12.4.7 m_stored_EW_type
struct ew_array CacheSetEWLRU::m_stored_EW_type
cache_set_ew_lru.h
cache_set_ew_lru.cc
6.13 CacheSetEWSRRIP Class Reference
EW-S-RRIP: Evict Write strategy for Static Re-reference Interval Prediction cache replacement policy.
#include <cache_set_ew_srrip.h>
Inheritance diagram for CacheSetEWSRRIP:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetEWSRRIP
+ m_rrip_flag
+ m_rrip_W_index
+ m_rrip_RW_index
+ m_rrip_R_index
- m_rrip_numbits
- m_rrip_max
- m_rrip_insert
- m_num_attempts
- m_rrip_bits
- m_replacement_pointer
- m_set_info
+ CacheSetEWSRRIP()
+ ~CacheSetEWSRRIP()
# evictEW()
# updateEW()
Collaboration diagram for CacheSetEWSRRIP:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
CacheSetInfo
+ clone()
+ isValid()
+ getTag()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ getBlockSize()
+ getAssociativity() - m_associativity
+ read_line() - m_attempts
+ write_line()
+ CacheSetInfoLRU()
+ find()
+ invalidate()
+ increment()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
-m_set_info
CacheSetEWSRRIP
+ m_rrip_flag
+ m_rrip_W_index
+ m_rrip_RW_index
+ m_rrip_R_index
- m_rrip_numbits
- m_rrip_max
- m_rrip_insert
- m_num_attempts
- m_rrip_bits
+ CacheSetEWSRRIP()
+ ~CacheSetEWSRRIP()
# evictEW()
# updateEW()
CacheSetEWSRRIP (String cfgname, core_id_t core_id, CacheBase::cache_t cache_type, UInt32 associa-

tivity, UInt32 blocksize, CacheSetInfoLRU set_info, UInt8 num_attempts)
A constructor.
CacheSetEWSRRIP ()
A destructor.
UInt32 getReplacementIndex (CacheCntlr cntlr)

ods
Public Attributes
char m_rrip_flag
A public variable.
UInt32 m_rrip_W_index
A public variable.
UInt32 m_rrip_RW_index
A public variable.
UInt32 m_rrip_R_index
A public variable.
UInt32 evictEW ()
void updateEW (UInt32 accessed_index)
Private Attributes
const UInt8 m_rrip_numbits

const UInt8 m_rrip_max
const UInt8 m_rrip_insert
UInt8 m_rrip_bits
UInt8 m_replacement_pointer
EW-SRRIP eviction decision finds the block that has max RRPV bits and it had only write operation. If there are
no write blocks, it chooses the block that has read and write operation. when the block with both operations is
not found, then the strategy fallbacks to SRRIP eviction for the read blocks, which evict the block with max RRPV.
Eventually, the block is found and its RRPV decremented by one.
6.13.2.1 CacheSetEWSRRIP()
CacheSetEWSRRIP::CacheSetEWSRRIP (
String cfgname,
core_id_t core_id,
UInt32 blocksize,
A constructor.
The following parameters will be initialized in the constructor
Parameters
m_rrip_numbits : Constant integer to save the entered RPPV in the configuration

m_rrip_insert : Constant array to save the number of RRIP bits for each block
m_rrip_bits : Integer array to store the max bits for each block that will be change during the execution
m_rrip_flag : Integer flag to get the operation type inside the for loop
m_rrip_W_index : The block has write operation
m_rrip_RW_index : The block has both operation
m_rrip_R_index : The block has read operation
6.13.2.2 CacheSetEWSRRIP()
CacheSetEWSRRIP::CacheSetEWSRRIP ( )
A destructor.
Free m_rrip_bits from the data that acquired during its lifetime.
6.13.3.1 evictEW()
UInt32 CacheSetEWSRRIP::evictEW ( ) [protected]
looping through a loop "m_associativity" times
1- Search through the m_rrip_bits and return the index that have max bit
2.1- If index is found with max rrip bits, then check if has write/read operations
2.2- If index is found with max rrip bits, then check if has read operation
2.3- If index is found with max rrip bits, then check if has write operation
2.4- If the index rrip bit is not max, then move to the next block and complete in round robin manner using "m_-
replacement_pointer"
3.1- Check if block with write operation was found then increment the pointer
3.2- Check if block with both operations was found then increment the pointer
3.3- Check if block with read operation was found then increment the pointer
Returns
CacheSetEWSRRIP::getReplacement
CacheSetEWSRRIP::evictEW
Index
UInt32 CacheSetEWSRRIP::getReplacementIndex (
getReplacementIndex method will first uses loop and checks if there is an invalid line(s) in the set, regardless of the
LRU bits of other lines, we choose the first invalid line to replace Prepare way for a new line: set prediction to 'long'.
If there is no valid block, then another for loop will start calling evictEW() method.
See also
evictEW()
Returns
CacheSetEWSRRIP::getReplacement
CacheSetEWSRRIP::evictEW
Index
6.13.3.3 updateEW()
void CacheSetEWSRRIP::updateEW (
void CacheSetEWSRRIP::updateReplacementIndex (

ods
m_rrip_bits will be decrement by one each time we get a hit. See also:
See also
CacheSetEWSRRIP::updateReplacement
Index
const UInt8 CacheSetEWSRRIP::m_num_attempts [private]
6.13.4.2 m_replacement_pointer
UInt8 CacheSetEWSRRIP::m_replacement_pointer [private]
6.13.4.3 m_rrip_bits
UInt8 CacheSetEWSRRIP::m_rrip_bits [private]
6.13.4.4 m_rrip_flag
char CacheSetEWSRRIP::m_rrip_flag
A public variable.
A flag to check the latest type stored of the loop indexes
6.13.4.5 m_rrip_insert
const UInt8 CacheSetEWSRRIP::m_rrip_insert [private]
6.13.4.6 m_rrip_max
const UInt8 CacheSetEWSRRIP::m_rrip_max [private]
6.13.4.7 m_rrip_numbits
const UInt8 CacheSetEWSRRIP::m_rrip_numbits [private]
6.13.4.8 m_rrip_R_index
UInt32 CacheSetEWSRRIP::m_rrip_R_index
A public variable.
we use this variable to assign the type of the read operation that was done on a block
6.13.4.9 m_rrip_RW_index
UInt32 CacheSetEWSRRIP::m_rrip_RW_index
A public variable.
we use this variable to assign the type of the read/ write operation that was done on a block
6.14 CacheSetInfo Class Reference 149
6.13.4.10 m_rrip_W_index
UInt32 CacheSetEWSRRIP::m_rrip_W_index
A public variable.
we use the variable to assign the type of the write operation that was done on a block
6.13.4.11 m_set_info
CacheSetInfoLRU CacheSetEWSRRIP::m_set_info [private]
cache_set_ew_srrip.h
cache_set_ew_srrip.cc
6.14 CacheSetInfo Class Reference
#include <cache_set.h>
Inheritance diagram for CacheSetInfo:
CacheSetInfo
+ ~CacheSetInfo()
CacheSetInfoLRU
- m_associativity
- m_access
- m_attempts
+ CacheSetInfoLRU()
+ increment()
Collaboration diagram for CacheSetInfo:
CacheSetInfo
+ ~CacheSetInfo()
virtual CacheSetInfo ()
6.14.1.1 CacheSetInfo()
virtual CacheSetInfo::CacheSetInfo ( ) [inline], [virtual]
cache_set.h
6.15 CacheSetInfoLRU Class Reference
#include <cache_set_lru.h>
6.15 CacheSetInfoLRU Class Reference 151
Inheritance diagram for CacheSetInfoLRU:
CacheSetInfo
+ ~CacheSetInfo()
CacheSetInfoLRU
- m_associativity
- m_access
- m_attempts
+ CacheSetInfoLRU()
+ increment()
Collaboration diagram for CacheSetInfoLRU:
CacheSetInfo
+ ~CacheSetInfo()
CacheSetInfoLRU
- m_associativity
- m_access
- m_attempts
+ CacheSetInfoLRU()
+ increment()
CacheSetInfoLRU (String name, String cfgname, core_id_t core_id, UInt32 associativity, UInt8 num_-
attempts)
virtual CacheSetInfoLRU ()
void increment (UInt32 index)
void incrementAttempt (UInt8 attempt)
Private Attributes
const UInt32 m_associativity

UInt64 m_access
UInt64 m_attempts
6.15.1.1 CacheSetInfoLRU()
CacheSetInfoLRU::CacheSetInfoLRU (
String name,
String cfgname,
core_id_t core_id,
6.15.1.2 CacheSetInfoLRU()
CacheSetInfoLRU::CacheSetInfoLRU ( ) [virtual]
6.15 CacheSetInfoLRU Class Reference 153
6.15.2.1 increment()
void CacheSetInfoLRU::increment (
UInt32 index ) [inline]
Index
CacheSetEWSRRIP::updateReplacement
Index
CacheSetLRU::updateReplacement
Index
CacheSetSRRIP::updateReplacement
Index
6.15.2.2 incrementAttempt()
void CacheSetInfoLRU::incrementAttempt (
UInt8 attempt ) [inline]
Index
Attempt
Index
6.15.3.1 m_access
UInt64 CacheSetInfoLRU::m_access [private]
const UInt32 CacheSetInfoLRU::m_associativity [private]
6.15.3.3 m_attempts
UInt64 CacheSetInfoLRU::m_attempts [private]
cache_set_lru.h
cache_set_lru.cc
6.16 CacheSetLRU Class Reference
#include <cache_set_lru.h>
6.16 CacheSetLRU Class Reference 155
Inheritance diagram for CacheSetLRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetLRU
# m_num_attempts
# m_lru_bits
# m_set_info
+ CacheSetLRU()
+ ~CacheSetLRU()
# moveToMRU()
Collaboration diagram for CacheSetLRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
CacheSetInfo
+ clone()
+ isValid()
+ getTag()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ getBlockSize()
+ write_line()
+ CacheSetInfoLRU()
+ find()
+ invalidate()
+ increment()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
#m_set_info
CacheSetLRU
# m_num_attempts
# m_lru_bits
+ CacheSetLRU()
+ ~CacheSetLRU()
# moveToMRU()
CacheSetLRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize, CacheSetInfoLRU

set_info, UInt8 num_attempts)
virtual CacheSetLRU ()
virtual UInt32 getReplacementIndex (CacheCntlr cntlr)
void moveToMRU (UInt32 accessed_index)

UInt8 m_lru_bits
6.16.1.1 CacheSetLRU()
CacheSetLRU::CacheSetLRU (
UInt32 blocksize,
6.16.1.2 CacheSetLRU()
CacheSetLRU::CacheSetLRU ( ) [virtual]
UInt32 CacheSetLRU::getReplacementIndex (
CacheSetLRU::moveToMRU
CacheSetLRU::getReplacement CacheCntlr::isInLowerLevel
Index Cache
Attempt
6.16.2.2 moveToMRU()
void CacheSetLRU::moveToMRU (
Index
Index
void CacheSetLRU::updateReplacementIndex (
Index
6.16.3.1 m_lru_bits
UInt8 CacheSetLRU::m_lru_bits [protected]
const UInt8 CacheSetLRU::m_num_attempts [protected]
6.16.3.3 m_set_info
CacheSetInfoLRU CacheSetLRU::m_set_info [protected]
cache_set_lru.h
cache_set_lru.cc
6.17 CacheSetMRU Class Reference
#include <cache_set_mru.h>
Inheritance diagram for CacheSetMRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetMRU
- m_lru_bits
+ CacheSetMRU()
+ ~CacheSetMRU()
6.17 CacheSetMRU Class Reference 161
Collaboration diagram for CacheSetMRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetMRU
- m_lru_bits
+ CacheSetMRU()
+ ~CacheSetMRU()
CacheSetMRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetMRU ()
Private Attributes
UInt8 m_lru_bits
6.17.1.1 CacheSetMRU()
CacheSetMRU::CacheSetMRU (
UInt32 blocksize )
6.17.1.2 CacheSetMRU()
CacheSetMRU::CacheSetMRU ( )
UInt32 CacheSetMRU::getReplacementIndex (
CacheSetMRU::updateReplacement
Index
CacheSetMRU::getReplacement
Index
6.18 CacheSetMRUT Class Reference 163
void CacheSetMRU::updateReplacementIndex (
CacheSetMRU::updateReplacement CacheSetMRU::getReplacement
Index Index
6.17.3.1 m_lru_bits
UInt8 CacheSetMRU::m_lru_bits [private]
cache_set_mru.h
cache_set_mru.cc
6.18 CacheSetMRUT Class Reference
MRU-T: Most Recently Used - Tour cache replacement policy.
#include <cache_set_mrut.h>
Inheritance diagram for CacheSetMRUT:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetMRUT
- m_lru_bits
- m_mru_bits
- m_rand
+ CacheSetMRUT()
+ ~CacheSetMRUT()
+ updateReplacementForFetched
Index()
Collaboration diagram for CacheSetMRUT:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetMRUT
- m_lru_bits
- m_mru_bits
- m_rand
+ CacheSetMRUT()
+ ~CacheSetMRUT()
+ updateReplacementForFetched
Index()
CacheSetMRUT (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

A constructor.
CacheSetMRUT ()
A destructor.

This method is for setting the m_mru_bits to "1" which means block has multiple tours, and it will be moved to MRU.
void updateReplacementForFetchedIndex (UInt32 accessed_index)
This method is for setting the m_mru_bits to "0" and move the block to MRU.
Private Attributes
UInt8 m_lru_bits
UInt8 m_mru_bits
A private variable.
Random m_rand
A private variable.
MRU-Tour algorithm basic idea is to keep checking the number of the times the block occupies the MRU position
while it stored in the cache. When the block is fetched, this will indicate that the first tour for this block has begun.
If the block has never been referenced, then it is a candidate for eviction. Otherwise, the block is referenced which
represents the second tour for the block has begun, which means that the block has multiple MRUTs.
6.18.2.1 CacheSetMRUT()
CacheSetMRUT::CacheSetMRUT (
UInt32 blocksize )
A constructor.
Parameters
m_mru_bits : to save the number of times the block has been accessed during its life time in the cache
m_lru_bits : used to move the block to the MRU position
6.18.2.2 CacheSetMRUT()
CacheSetMRUT::CacheSetMRUT ( )
A destructor.
Free m_lru_bits and m_mru_bits from the data that acquired during their lifetime.
UInt32 CacheSetMRUT::getReplacementIndex (
getReplacementIndex method will first uses loop and checks if there is an invalid line(s) in the set, which is for the
compulsory miss. The blocks in the set are fetched to the cache, then they will have MRUT-bit =0, then they will
be moved to the MRU position updateReplacementForFetchedIndex method will be invoked to set the bit to "0" and
move the block to MRU. The a block that is found will be moved to MRU and then the new block will overwritten it in
the CacheSet::insert method.
See also
updateReplacementForFetchedIndex()
Returns
If the are no valid blocks then we have to choose a victim block to evict. Another for loop is used, and here we
could either choose the first index with bit = 0, or randomly, but we make the attempets equals to the number of
the associativity. when the block is found, the updateReplacementForFetchedIndex method will be called to set the
block m_mru_bits to "0" and move it to MRU position
See also
Returns
Another for loop is used, and here we could either choose the first index with bit = 0, If there are no index with bit=
0 then choose randomly from the indices that has m_mru_bits "1". loop until you find one satisfy the if statement
when the block is found, the updateReplacementForFetchedIndex method will be called to set the block m_mru_bits
to "0" and move it to MRU position
See also
Returns
CacheSetMRUT::getReplacement CacheSetMRUT::updateReplacement
Index ForFetchedIndex
6.18.3.2 updateReplacementForFetchedIndex()
void CacheSetMRUT::updateReplacementForFetchedIndex (
UInt32 accessed_index )
This method is for setting the m_mru_bits to "0" and move the block to MRU.
updateReplacementForFetchedIndex will be invoked when the block is fetched. The block MRUT-bit will be set to
0 which means starting the first tour. The a block that is found will be moved to MRU and then the new block will
overwritten it in the CacheSet::insert method. Here is the caller graph for this function:
CacheSetMRUT::updateReplacement CacheSetMRUT::getReplacement
ForFetchedIndex Index
void CacheSetMRUT::updateReplacementIndex (
This method is for setting the m_mru_bits to "1" which means block has multiple tours, and it will be moved to MRU.
updateReplacementIndex will be invoked if we got a hit from CacheSet::read_line() or CacheSet::wite_line() meth-

ods m_rrip_bits will be decrement by one each time we get a hit . See also:
See also
CacheSet::write_line()The a block that is found will be moved to MRU and then the new block will overwritten
it in the CacheSet::insert method.
6.19 CacheSetNMRU Class Reference 169
6.18.4.1 m_lru_bits
UInt8 CacheSetMRUT::m_lru_bits [private]
6.18.4.2 m_mru_bits
UInt8 CacheSetMRUT::m_mru_bits [private]
A private variable.
we use this variable as array to save the number of times the block get to the MRU position
6.18.4.3 m_rand
Random CacheSetMRUT::m_rand [private]
A private variable.
we use this variable of type Random to get a random number for the index in the set when all the "m_mru_bits" is
"1"
cache_set_mrut.h
cache_set_mrut.cc
6.19 CacheSetNMRU Class Reference
#include <cache_set_nmru.h>
Inheritance diagram for CacheSetNMRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetNMRU
- m_lru_bits
+ CacheSetNMRU()
+ ~CacheSetNMRU()
Collaboration diagram for CacheSetNMRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetNMRU
- m_lru_bits
+ CacheSetNMRU()
+ ~CacheSetNMRU()
CacheSetNMRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetNMRU ()
Private Attributes
UInt8 m_lru_bits
6.19.1.1 CacheSetNMRU()
CacheSetNMRU::CacheSetNMRU (
UInt32 blocksize )
6.19.1.2 CacheSetNMRU()
CacheSetNMRU::CacheSetNMRU ( )
UInt32 CacheSetNMRU::getReplacementIndex (
CacheSetNMRU::updateReplacement
Index
CacheSetNMRU::getReplacement
Index
void CacheSetNMRU::updateReplacementIndex (
CacheSetNMRU::updateReplacement CacheSetNMRU::getReplacement
Index Index
6.19.3.1 m_lru_bits
UInt8 CacheSetNMRU::m_lru_bits [private]
UInt8 CacheSetNMRU::m_replacement_pointer [private]
cache_set_nmru.h
cache_set_nmru.cc
6.20 CacheSetNRU Class Reference
#include <cache_set_nru.h>
Inheritance diagram for CacheSetNRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetNRU
- m_lru_bits
- m_num_bits_set
+ CacheSetNRU()
+ ~CacheSetNRU()
6.20 CacheSetNRU Class Reference 175
Collaboration diagram for CacheSetNRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetNRU
- m_lru_bits
- m_num_bits_set
+ CacheSetNRU()
+ ~CacheSetNRU()
CacheSetNRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetNRU ()
Private Attributes
UInt8 m_lru_bits
UInt8 m_num_bits_set
6.20.1.1 CacheSetNRU()
CacheSetNRU::CacheSetNRU (
UInt32 blocksize )
6.20.1.2 CacheSetNRU()
CacheSetNRU::CacheSetNRU ( )
UInt32 CacheSetNRU::getReplacementIndex (
CacheSetNRU::updateReplacement
Index
CacheSetNRU::getReplacement
Index
6.20 CacheSetNRU Class Reference 177
void CacheSetNRU::updateReplacementIndex (
CacheSetNRU::updateReplacement CacheSetNRU::getReplacement
Index Index
6.20.3.1 m_lru_bits
UInt8 CacheSetNRU::m_lru_bits [private]
6.20.3.2 m_num_bits_set
UInt8 CacheSetNRU::m_num_bits_set [private]
UInt8 CacheSetNRU::m_replacement_pointer [private]
cache_set_nru.h
cache_set_nru.cc
6.21 CacheSetPLRU Class Reference
#include <cache_set_plru.h>
Inheritance diagram for CacheSetPLRU:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetPLRU
-b
+ CacheSetPLRU()
+ ~CacheSetPLRU()
6.21 CacheSetPLRU Class Reference 179
Collaboration diagram for CacheSetPLRU:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetPLRU
-b
+ CacheSetPLRU()
+ ~CacheSetPLRU()
CacheSetPLRU (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetPLRU ()
Private Attributes
UInt8 b [8]
6.21.1.1 CacheSetPLRU()
CacheSetPLRU::CacheSetPLRU (
UInt32 blocksize )
6.21.1.2 CacheSetPLRU()
CacheSetPLRU::CacheSetPLRU ( )
UInt32 CacheSetPLRU::getReplacementIndex (
CacheSetPLRU::updateReplacement
Index
CacheSetPLRU::getReplacement
Index
6.22 CacheSetRandom Class Reference 181
void CacheSetPLRU::updateReplacementIndex (
CacheSetPLRU::updateReplacement CacheSetPLRU::getReplacement
Index Index
6.21.3.1 b
UInt8 CacheSetPLRU::b[8] [private]
cache_set_plru.h
cache_set_plru.cc
6.22 CacheSetRandom Class Reference
#include <cache_set_random.h>
Inheritance diagram for CacheSetRandom:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetRandom
- m_rand
+ CacheSetRandom()
+ ~CacheSetRandom()
6.22 CacheSetRandom Class Reference 183
Collaboration diagram for CacheSetRandom:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetRandom
- m_rand
+ CacheSetRandom()
+ ~CacheSetRandom()
CacheSetRandom (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetRandom ()
Private Attributes
Random m_rand
6.22.1.1 CacheSetRandom()
CacheSetRandom::CacheSetRandom (
UInt32 blocksize )
6.22.1.2 CacheSetRandom()
CacheSetRandom::CacheSetRandom ( )
UInt32 CacheSetRandom::getReplacementIndex (
CacheSetRandom::getReplacement
Index
6.23 CacheSetRoundRobin Class Reference 185
void CacheSetRandom::updateReplacementIndex (
6.22.3.1 m_rand
Random CacheSetRandom::m_rand [private]
cache_set_random.h
cache_set_random.cc
6.23 CacheSetRoundRobin Class Reference
#include <cache_set_round_robin.h>
Inheritance diagram for CacheSetRoundRobin:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetRoundRobin
- m_replacement_index
+ CacheSetRoundRobin()
+ ~CacheSetRoundRobin()
6.23 CacheSetRoundRobin Class Reference 187
Collaboration diagram for CacheSetRoundRobin:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetRoundRobin
- m_replacement_index
+ CacheSetRoundRobin()
+ ~CacheSetRoundRobin()
CacheSetRoundRobin (CacheBase::cache_t cache_type, UInt32 associativity, UInt32 blocksize)

CacheSetRoundRobin ()
Private Attributes
UInt32 m_replacement_index
6.23.1.1 CacheSetRoundRobin()
CacheSetRoundRobin::CacheSetRoundRobin (
UInt32 blocksize )
6.23.1.2 CacheSetRoundRobin()
CacheSetRoundRobin::CacheSetRoundRobin ( )
UInt32 CacheSetRoundRobin::getReplacementIndex (
CacheSetRoundRobin
::getReplacementIndex
6.24 CacheSetSRRIP Class Reference 189
void CacheSetRoundRobin::updateReplacementIndex (
6.23.3.1 m_replacement_index
UInt32 CacheSetRoundRobin::m_replacement_index [private]
cache_set_round_robin.h
cache_set_round_robin.cc
6.24 CacheSetSRRIP Class Reference
#include <cache_set_srrip.h>
Inheritance diagram for CacheSetSRRIP:
CacheSet
+ m_coming_EW_type
+ m_block_op
_array
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ ~CacheSet()
+ getBlockSize()
+ getLock()
+ read_line()
+ write_line()
+ find()
+ invalidate()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
CacheSetSRRIP
- m_rrip_numbits
- m_rrip_max
- m_rrip_insert
- m_num_attempts
- m_rrip_bits
- m_set_info
+ CacheSetSRRIP()
+ ~CacheSetSRRIP()
Collaboration diagram for CacheSetSRRIP:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone() CacheSetInfo
+ isValid()
+ getTag()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_associativity
# m_blocksize
# m_lock
+ CacheSet()
+ getBlockSize()
+ write_line()
+ CacheSetInfoLRU()
+ find()
+ invalidate()
+ increment()
+ insert()
+ peekBlock()
+ getDataPtr()
+ getBlockSize()
+ createCacheSet()
+ parsePolicyType()
-m_set_info
CacheSetSRRIP
- m_rrip_numbits
- m_rrip_max
- m_rrip_insert
- m_num_attempts
- m_rrip_bits
+ CacheSetSRRIP()
+ ~CacheSetSRRIP()
CacheSetSRRIP (String cfgname, core_id_t core_id, CacheBase::cache_t cache_type, UInt32 associativity,

UInt32 blocksize, CacheSetInfoLRU set_info, UInt8 num_attempts)
CacheSetSRRIP ()
Private Attributes
const UInt8 m_rrip_numbits

const UInt8 m_rrip_max
const UInt8 m_rrip_insert
UInt8 m_rrip_bits
6.24.1.1 CacheSetSRRIP()
CacheSetSRRIP::CacheSetSRRIP (
String cfgname,
core_id_t core_id,
UInt32 blocksize,
6.24.1.2 CacheSetSRRIP()
CacheSetSRRIP::CacheSetSRRIP ( )
UInt32 CacheSetSRRIP::getReplacementIndex (
CacheCntlr::isInLowerLevel
Cache
Index
Attempt
void CacheSetSRRIP::updateReplacementIndex (
CacheSetSRRIP::updateReplacement
Index
const UInt8 CacheSetSRRIP::m_num_attempts [private]
UInt8 CacheSetSRRIP::m_replacement_pointer [private]
6.24.3.3 m_rrip_bits
UInt8 CacheSetSRRIP::m_rrip_bits [private]
6.24.3.4 m_rrip_insert
const UInt8 CacheSetSRRIP::m_rrip_insert [private]
6.24.3.5 m_rrip_max
const UInt8 CacheSetSRRIP::m_rrip_max [private]
6.24.3.6 m_rrip_numbits
const UInt8 CacheSetSRRIP::m_rrip_numbits [private]
6.24.3.7 m_set_info
CacheSetInfoLRU CacheSetSRRIP::m_set_info [private]
cache_set_srrip.h
cache_set_srrip.cc
6.25 CacheState Class Reference 195
6.25 CacheState Class Reference
#include <cache_state.h>
Collaboration diagram for CacheState:
CacheState
- cstate
+ CacheState()
+ ~CacheState()
+ readable()
+ writable()
Public Types
enum cstate_t {
CSTATE_FIRST = 0, INVALID = CSTATE_FIRST, SHARED, SHARED_UPGRADING,
EXCLUSIVE, OWNED, MODIFIED, NUM_CSTATE_STATES,
INVALID_COLD = NUM_CSTATE_STATES, INVALID_EVICT, INVALID_COHERENCY, NUM_CSTATE_-
SPECIAL_STATES }
CacheState (cstate_t state=INVALID)

CacheState ()
bool readable ()
bool writable ()
Private Attributes
cstate_t cstate
6.25.1.1 cstate_t
enum CacheState::cstate_t
Enumerator
CSTATE_FIRST
INVALID
SHARED
SHARED_UPGRADING
EXCLUSIVE
OWNED
MODIFIED
NUM_CSTATE_STATES
INVALID_COLD
INVALID_EVICT
INVALID_COHERENCY
NUM_CSTATE_SPECIAL_STATES
6.25.2.1 CacheState()
CacheState::CacheState (
cstate_t state = INVALID ) [inline]
6.25.2.2 CacheState()
CacheState::CacheState ( ) [inline]
6.25.3.1 readable()
bool CacheState::readable ( ) [inline]
Access
6.26 CacheSetEWLRU::ew_array Struct Reference 197
6.25.3.2 writable()
bool CacheState::writable ( ) [inline]
Access
6.25.4.1 cstate
cstate_t CacheState::cstate [private]
cache_state.h
6.26 CacheSetEWLRU::ew_array Struct Reference
#include <cache_set_ew_lru.h>
Collaboration diagram for CacheSetEWLRU::ew_array:
CacheSetEWLRU::ew_array
+ was_read
+ was_written
Public Attributes
bool was_read
bool was_written
we declare a structure type ew_array, and defines it having two boolean members "was_read" and "was_written". a
declaration for variable "m_stored_EW_type which is then used to declare the two boolean objects, which is of the
type ew_array.
6.26.2.1 was_read
bool CacheSetEWLRU::ew_array::was_read
6.26.2.2 was_written
bool CacheSetEWLRU::ew_array::was_written
The documentation for this struct was generated from the following file:
cache_set_ew_lru.h
6.27 GhbPrefetcher::GHBEntry Struct Reference
Collaboration diagram for GhbPrefetcher::GHBEntry:
GhbPrefetcher::GHBEntry
+ nextIndex
+ delta
+ generation
+ GHBEntry()
GHBEntry ()
6.27 GhbPrefetcher::GHBEntry Struct Reference 199
Public Attributes
UInt32 nextIndex
SInt64 delta
UInt32 generation
6.27.1.1 GHBEntry()
GhbPrefetcher::GHBEntry::GHBEntry ( ) [inline]
6.27.2.1 delta
SInt64 GhbPrefetcher::GHBEntry::delta
6.27.2.2 generation
UInt32 GhbPrefetcher::GHBEntry::generation
6.27.2.3 nextIndex
UInt32 GhbPrefetcher::GHBEntry::nextIndex
ghb_prefetcher.h
6.28 GhbPrefetcher Class Reference
#include <ghb_prefetcher.h>
Inheritance diagram for GhbPrefetcher:
Prefetcher
+ getNextAddress()
+ createPrefetcher()
GhbPrefetcher
- m_prefetchWidth
- m_prefetchDepth
- m_lastAddress
- m_ghbSize
- m_ghbHead
- m_generation
- m_ghb
- m_tableSize
- m_tableHead
- m_ghbTable
- INVALID_DELTA
- INVALID_INDEX
+ GhbPrefetcher()
+ getNextAddress()
+ ~GhbPrefetcher()
6.28 GhbPrefetcher Class Reference 201
Collaboration diagram for GhbPrefetcher:
Prefetcher
+ getNextAddress()
GhbPrefetcher
- m_prefetchWidth
- m_prefetchDepth
- m_lastAddress
- m_ghbSize
- m_ghbHead
- m_generation
- m_ghb
- m_tableSize
- m_tableHead
- m_ghbTable
- INVALID_DELTA
- INVALID_INDEX
+ GhbPrefetcher()
+ getNextAddress()
+ ~GhbPrefetcher()
Classes
struct GHBEntry
struct TableEntry
GhbPrefetcher (String configName, core_id_t core_id)

std::vector< IntPtr > getNextAddress (IntPtr currentAddress, core_id_t core_id)
GhbPrefetcher ()
Private Attributes
UInt32 m_prefetchWidth
UInt32 m_prefetchDepth
IntPtr m_lastAddress
UInt32 m_ghbSize
UInt32 m_ghbHead
UInt32 m_generation
std::vector< GHBEntry > m_ghb
UInt32 m_tableSize
UInt32 m_tableHead
std::vector< TableEntry > m_ghbTable
static const SInt64 INVALID_DELTA = INT64_MAX

static const UInt32 INVALID_INDEX = UINT32_MAX
6.28.1.1 GhbPrefetcher()
GhbPrefetcher::GhbPrefetcher (
String configName,
core_id_t core_id )
6.28.1.2 GhbPrefetcher()
GhbPrefetcher::GhbPrefetcher ( )
6.28.2.1 getNextAddress()
std::vector< IntPtr > GhbPrefetcher::getNextAddress (

IntPtr currentAddress,
core_id_t core_id ) [virtual]
Implements Prefetcher.
6.28 GhbPrefetcher Class Reference 203
6.28.3.1 INVALID_DELTA
const SInt64 GhbPrefetcher::INVALID_DELTA = INT64_MAX [static], [private]
6.28.3.2 INVALID_INDEX
const UInt32 GhbPrefetcher::INVALID_INDEX = UINT32_MAX [static], [private]
6.28.3.3 m_generation
UInt32 GhbPrefetcher::m_generation [private]
6.28.3.4 m_ghb
std::vector<GHBEntry> GhbPrefetcher::m_ghb [private]
6.28.3.5 m_ghbHead
UInt32 GhbPrefetcher::m_ghbHead [private]
6.28.3.6 m_ghbSize
UInt32 GhbPrefetcher::m_ghbSize [private]
6.28.3.7 m_ghbTable
std::vector<TableEntry> GhbPrefetcher::m_ghbTable [private]
6.28.3.8 m_lastAddress
IntPtr GhbPrefetcher::m_lastAddress [private]
6.28.3.9 m_prefetchDepth
UInt32 GhbPrefetcher::m_prefetchDepth [private]
6.28.3.10 m_prefetchWidth
UInt32 GhbPrefetcher::m_prefetchWidth [private]
6.28.3.11 m_tableHead
UInt32 GhbPrefetcher::m_tableHead [private]
6.28.3.12 m_tableSize
UInt32 GhbPrefetcher::m_tableSize [private]
ghb_prefetcher.h
ghb_prefetcher.cc
6.29 ParametricDramDirectoryMSI::MemoryManager Class Reference
#include <memory_manager.h>
6.29 ParametricDramDirectoryMSI::MemoryManager Class Reference 205
Inheritance diagram for ParametricDramDirectoryMSI::MemoryManager:
MemoryManagerBase
::MemoryManager
- m_cache_cntlrs
- m_nuca_cache
- m_dram_cache
- m_dram_cntlr
_lookup
_lookup
- m_itlb
- m_dtlb
- m_stlb
- m_core_id_master
- m_user_thread_sem
- m_enabled
+ MemoryManager()
+ ~MemoryManager()
+ getCacheBlockSize()
+ getCache()
+ getL1ICache()
+ getL1DCache()
+ getDramCntlr()
+ getCacheCntlrAt()
+ setCacheCntlrAt()
+ sendMsg()
+ broadcastMsg()
+ getL1HitLatency()
+ addL1Hits()
+ enableModels()
+ disableModels()
+ getCost()
+ incrElapsedTime()
+ incrElapsedTime()
- accessTLB()
Collaboration diagram for ParametricDramDirectoryMSI::MemoryManager:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_blocksize
# m_name
# m_lock
# m_cache_size
+ CacheSet() # m_associativity ReqQueueListTemplate
+ ~CacheSet() # m_blocksize < T_Req >
- m_req_queue_list
+ getLock() # m_ahl CacheSetInfo std::vector< CacheCntlr * > + ReqQueueListTemplate()
+ read_line() # m_log_blocksize + ~ReqQueueListTemplate()
+ write_line() + enqueue()
+ CacheBase()
+ find() + ~CacheSetInfo() + dequeue()
+ ~CacheBase()
+ invalidate() + front()
+ splitAddress()
+ insert() + back()
+ splitAddress()
+ peekBlock() + size()
+ tagToAddress()
+ getDataPtr() + empty()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
-m_sets -m_set_info < CacheDirectoryWaiter >
Cache
- m_enabled
- m_num_accesses
- m_num_hits ReqQueueListTemplate
- m_cache_type < CacheDirectoryWaiter >
- m_fault_injector
- m_req_queue_list
+ Cache() ParametricDramDirectoryMSI Prefetcher
+ ~Cache()
+ getSetLock()
+ enqueue()
+ invalidateSingleLine() + getNextAddress()
+ dequeue()
+ accessSingleLine() + createPrefetcher()
+ front()
+ back()
+ peekSingleLine()
+ size()
+ peekBlock()
+ empty()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_cache -m_cache -m_cache -m_prev_cache_cntlrs -m_directory_waiters -m_prefetcher
::CacheMasterCntlr
NucaCache - m_cache_lock
- m_smt_lock
- m_core_id
- m_dram_cntlr
- m_memory_manager
- m_shmem_perf_model ParametricDramDirectoryMSI::TLB _writebacks
- m_home_lookup
- mshr
- m_cache_block_size - m_size
- m_l1_mshr
- m_data_access_time - m_associativity
- m_tags_access_time - m_access MemoryManagerBase - m_evicting_address
- m_data_array_bandwidth - m_miss
- m_evicting_buf
- m_queue_model - SIM_PAGE_SHIFT -m_next_level
- m_atds
- m_reads - SIM_PAGE_SIZE
- m_setlocks
- m_writes - SIM_PAGE_MASK
- m_log_blocksize
- m_read_misses
+ TLB() - m_num_sets
- m_write_misses
+ lookup() - m_prefetch_list
+ NucaCache() + allocate() - m_prefetch_next
+ ~NucaCache()
- createSetLocks()
+ read()
- getSetLock()
+ write()
- createATDs()
- accessDataArray()
- accessATDs()
-m_itlb
-m_nuca_cache -m_dtlb
-m_stlb
::MemoryManager
- m_dram_cache
- m_dram_cntlr
_lookup
_lookup
- m_core_id_master
- m_user_thread_sem
- m_enabled
CacheCntlr + MemoryManager()
+ ~MemoryManager()
+ getCacheBlockSize() -m_master
+ isInLowerLevelCache() + getCache()
+ incrementQBSLookupCost() + getL1ICache()
+ getL1DCache()
+ getDramCntlr()
+ getCacheCntlrAt()
+ setCacheCntlrAt()
+ sendMsg()
+ broadcastMsg()
+ getL1HitLatency()
+ addL1Hits()
+ enableModels()
+ disableModels()
+ getCost()
+ incrElapsedTime()
+ incrElapsedTime()
- accessTLB()
-m_memory_manager -m_cache_cntlrs
::CacheCntlr
+ loads
+ stores
+ load_misses
+ store_misses
+ loads_state
+ stores_state
+ loads_where
+ stores_where
+ load_misses_state
+ loads_prefetch
+ stores_prefetch
+ hits_prefetch
+ evict_prefetch
+ evict
and 13 more...
- m_mem_component
_lookup
- m_perfect
- m_passthrough
- m_coherent
- m_l1_mshr
- stats
- m_core_id
- m_writeback_time
- m_shared_cores
- m_core_id_master
- m_user_thread_sem
- m_shmem_perf
- m_shmem_perf_totaltime
- m_shmem_perf_numrequests
-m_next_cache_cntlr
- m_shmem_perf_model
-m_last_level
+ CacheCntlr()
+ ~CacheCntlr()
+ getCache()
+ getLock()
+ createSetLocks()
+ updateHits()
+ acquireLock()
+ releaseLock()
+ isMasterCache()
+ isFirstLevel()
+ isLastLevel()
+ isShared()
+ enable()
+ disable()
- updateCounters()
- cleanupMshr()
- transition()
- accessCache()
- trainPrefetcher()
- Prefetch()
- doPrefetch()
- getCacheState()
- getCacheState()
- setCacheState()
and 26 more...
- __walkUsageBits()
MemoryManager (Core core, Network network, ShmemPerfModel shmem_perf_model)

MemoryManager ()
UInt64 getCacheBlockSize () const
Cache getCache (MemComponent::component_t mem_component)
Cache getL1ICache ()
Cache getL1DCache ()
Cache getLastLevelCache ()
PrL1PrL2DramDirectoryMSI::DramDirectoryCache getDramDirectoryCache ()
PrL1PrL2DramDirectoryMSI::DramCntlr getDramCntlr ()
AddressHomeLookup getTagDirectoryHomeLookup ()
AddressHomeLookup getDramControllerHomeLookup ()
CacheCntlr getCacheCntlrAt (core_id_t core_id, MemComponent::component_t mem_component)
void setCacheCntlrAt (core_id_t core_id, MemComponent::component_t mem_component, CacheCntlr
cache_cntlr)
HitWhere::where_t coreInitiateMemoryAccess (MemComponent::component_t mem_component, Core-
::lock_signal_t lock_signal, Core::mem_op_t mem_op_type, IntPtr address, UInt32 offset, Byte data_buf,
UInt32 data_length, Core::MemModeled modeled)
void handleMsgFromNetwork (NetPacket &packet)
void sendMsg (PrL1PrL2DramDirectoryMSI::ShmemMsg::msg_t msg_type, MemComponent::component-
_t sender_mem_component, MemComponent::component_t receiver_mem_component, core_id_t re-
quester, core_id_t receiver, IntPtr address, Byte data_buf=NULL, UInt32 data_length=0, HitWhere-
::where_t where=HitWhere::UNKNOWN, ShmemPerf perf=NULL, ShmemPerfModel::Thread_t thread_-
num=ShmemPerfModel::NUM_CORE_THREADS)
void broadcastMsg (PrL1PrL2DramDirectoryMSI::ShmemMsg::msg_t msg_type, MemComponent-
::component_t sender_mem_component, MemComponent::component_t receiver_mem_component, core-
_id_t requester, IntPtr address, Byte data_buf=NULL, UInt32 data_length=0, ShmemPerf perf=NULL,
ShmemPerfModel::Thread_t thread_num=ShmemPerfModel::NUM_CORE_THREADS)
SubsecondTime getL1HitLatency (void)
void addL1Hits (bool icache, Core::mem_op_t mem_op_type, UInt64 hits)
void enableModels ()
void disableModels ()
core_id_t getShmemRequester (const void pkt_data)
UInt32 getModeledLength (const void pkt_data)
SubsecondTime getCost (MemComponent::component_t mem_component, CachePerfModel::Cache-
Access_t access_type)
void incrElapsedTime (SubsecondTime latency, ShmemPerfModel::Thread_t thread_num=ShmemPerf-
Model::NUM_CORE_THREADS)
void incrElapsedTime (MemComponent::component_t mem_component, CachePerfModel::CacheAccess_t
access_type, ShmemPerfModel::Thread_t thread_num=ShmemPerfModel::NUM_CORE_THREADS)
void accessTLB (TLB tlb, IntPtr address, bool isIfetch, Core::MemModeled modeled)
Private Attributes
CacheCntlr m_cache_cntlrs [MemComponent::LAST_LEVEL_CACHE+1]

NucaCache m_nuca_cache
DramCache m_dram_cache
PrL1PrL2DramDirectoryMSI::DramDirectoryCntlr m_dram_directory_cntlr
PrL1PrL2DramDirectoryMSI::DramCntlr m_dram_cntlr
AddressHomeLookup m_tag_directory_home_lookup
AddressHomeLookup m_dram_controller_home_lookup
TLB m_itlb
TLB m_dtlb
TLB m_stlb
ComponentLatency m_tlb_miss_penalty
bool m_tlb_miss_parallel
core_id_t m_core_id_master
bool m_tag_directory_present
bool m_dram_cntlr_present
Semaphore m_user_thread_sem
Semaphore m_network_thread_sem
MemComponent::component_t m_last_level_cache
bool m_enabled
CachePerfModel m_cache_perf_models [MemComponent::LAST_LEVEL_CACHE+1]
static CacheCntlrMap m_all_cache_cntlrs
6.29.1.1 MemoryManager()
ParametricDramDirectoryMSI::MemoryManager::MemoryManager (
Core core,
Network network,
ShmemPerfModel shmem_perf_model )
::TLB::lookup
ParametricDramDirectoryMSI CacheBlockInfo::getOwner
::CacheCntlr::acquireLock ::CacheCntlr::operationPermissibleinCache
::CacheCntlr::releaseLock ParametricDramDirectoryMSI
CacheBlockInfo::setCState ParametricDramDirectoryMSI ParametricDramDirectoryMSI

::CacheCntlr::getCache ::CacheCntlr::processUpgradeRep
FromDramDirectory
::MemoryManager::coreInitiateMemory ParametricDramDirectoryMSI
Access ::CacheCntlr::trainPrefetcher
PrevCache
Directory
::CacheCntlr::handleMsgFromDram ::MemoryManager::sendMsg
DramDirectory
Directory
::front
::MemoryManager::getCacheBlockSize
::MemoryManager::setCacheCntlrAt
::MemoryManager::MemoryManager
::CacheCntlr::setNextCacheCntlr
::MemoryManager::broadcastMsg
::CacheCntlr::setPrevCacheCntlrs
6.29.1.2 MemoryManager()
ParametricDramDirectoryMSI::MemoryManager::MemoryManager ( )
6.29.2.1 accessTLB()
void ParametricDramDirectoryMSI::MemoryManager::accessTLB (
TLB tlb,
IntPtr address,
bool isIfetch,
Core::MemModeled modeled ) [private]
ParametricDramDirectoryMSI CacheBlockInfo::create
::TLB::lookup
ParametricDramDirectoryMSI CacheSet::getReplacement
::MemoryManager::accessTLB ParametricDramDirectoryMSI CacheBlockInfo::setTag Index
ParametricDramDirectoryMSI ::TLB::allocate
CacheSet::find
::MemoryManager::accessTLB ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.29.2.2 addL1Hits()
void ParametricDramDirectoryMSI::MemoryManager::addL1Hits (
bool icache,
UInt64 hits ) [inline]
::MemoryManager::enableModels
::MemoryManager::addL1Hits
::MemoryManager::disableModels
6.29.2.3 broadcastMsg()
void ParametricDramDirectoryMSI::MemoryManager::broadcastMsg (
PrL1PrL2DramDirectoryMSI::ShmemMsg::msg_t msg_type,
MemComponent::component_t sender_mem_component,
MemComponent::component_t receiver_mem_component,
IntPtr address,
Byte data_buf = NULL,
UInt32 data_length = 0,
ShmemPerf perf = NULL,
ShmemPerfModel::Thread_t thread_num = ShmemPerfModel::NUM_CORE_THREADS )

::MemoryManager::broadcastMsg ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
6.29.2.4 coreInitiateMemoryAccess()
HitWhere::where_t ParametricDramDirectoryMSI::MemoryManager::coreInitiateMemoryAccess (
Core::lock_signal_t lock_signal,
IntPtr address,
UInt32 offset,
Byte data_buf,
UInt32 data_length,
Core::MemModeled modeled )
::TLB::allocate
ParametricDramDirectoryMSI ::TLB::lookup
::MemoryManager::accessTLB Cache::accessSingleLine
::CacheCntlr::accessCache Cache::insertSingleLine
::CacheCntlr::updateCounters ::CacheCntlr::getShmemPerfModel
::CacheCntlr::releaseLock ::CacheCntlr::isFirstLevel
::CacheCntlr::acquireLock ::CacheCntlr::lastLevelCache
::MemoryManager::coreInitiateMemory ::CacheCntlr::copyDataFromNextLevel
ParametricDramDirectoryMSI CacheState::readable
::CStateString
ParametricDramDirectoryMSI ParametricDramDirectoryMSI CacheState::writable

::CacheCntlr::processShmemReqFrom ::CacheCntlr::operationPermissibleinCache
PrevCache
ParametricDramDirectoryMSI ::CacheCntlr::notifyPrevLevelInsert
::CacheCntlr::Prefetch ParametricDramDirectoryMSI
Access
6.29.2.5 disableModels()
void ParametricDramDirectoryMSI::MemoryManager::disableModels ( )
::MemoryManager::disableModels ::MemoryManager::addL1Hits
6.29.2.6 enableModels()
void ParametricDramDirectoryMSI::MemoryManager::enableModels ( )
::MemoryManager::enableModels ::MemoryManager::addL1Hits
6.29.2.7 getCache()
Cache ParametricDramDirectoryMSI::MemoryManager::getCache (
MemComponent::component_t mem_component ) [inline]
::MemoryManager::getCache ::CacheCntlr::getCache
::MemoryManager::getL1ICache
::MemoryManager::getCache ::MemoryManager::getL1DCache
::MemoryManager::getLastLevelCache
6.29.2.8 getCacheBlockSize()
UInt64 ParametricDramDirectoryMSI::MemoryManager::getCacheBlockSize ( ) const [inline]
::MemoryManager::getCacheBlockSize ::MemoryManager::MemoryManager
6.29.2.9 getCacheCntlrAt()
CacheCntlr ParametricDramDirectoryMSI::MemoryManager::getCacheCntlrAt (
core_id_t core_id,
MemComponent::component_t mem_component ) [inline]
::MemoryManager::getCacheCntlrAt ::CacheCntlr::CacheCntlr
6.29.2.10 getCost()
SubsecondTime ParametricDramDirectoryMSI::MemoryManager::getCost (
CachePerfModel::CacheAccess_t access_type )
::MemoryManager::getCost
::MemoryManager::getModeledLength
6.29.2.11 getDramCntlr()
PrL1PrL2DramDirectoryMSI::DramCntlr ParametricDramDirectoryMSI::MemoryManager::getDramCntlr (
) [inline]
6.29.2.12 getDramControllerHomeLookup()
AddressHomeLookup ParametricDramDirectoryMSI::MemoryManager::getDramControllerHomeLookup ( )
[inline]
6.29.2.13 getDramDirectoryCache()
PrL1PrL2DramDirectoryMSI::DramDirectoryCache ParametricDramDirectoryMSI::MemoryManager::get-
DramDirectoryCache ( ) [inline]
6.29.2.14 getL1DCache()
Cache ParametricDramDirectoryMSI::MemoryManager::getL1DCache ( ) [inline]

::MemoryManager::getL1DCache ::MemoryManager::getCache ::CacheCntlr::getCache
6.29.2.15 getL1HitLatency()
SubsecondTime ParametricDramDirectoryMSI::MemoryManager::getL1HitLatency (
void ) [inline]
6.29.2.16 getL1ICache()
Cache ParametricDramDirectoryMSI::MemoryManager::getL1ICache ( ) [inline]

::MemoryManager::getL1ICache ::MemoryManager::getCache ::CacheCntlr::getCache
6.29.2.17 getLastLevelCache()
Cache ParametricDramDirectoryMSI::MemoryManager::getLastLevelCache ( ) [inline]

::MemoryManager::getLastLevelCache ::MemoryManager::getCache ::CacheCntlr::getCache
6.29.2.18 getModeledLength()
UInt32 ParametricDramDirectoryMSI::MemoryManager::getModeledLength (
const void pkt_data ) [inline]
6.29.2.19 getShmemRequester()
core_id_t ParametricDramDirectoryMSI::MemoryManager::getShmemRequester (
const void pkt_data ) [inline]
6.29.2.20 getTagDirectoryHomeLookup()
AddressHomeLookup ParametricDramDirectoryMSI::MemoryManager::getTagDirectoryHomeLookup ( )
[inline]
6.29.2.21 handleMsgFromNetwork()
void ParametricDramDirectoryMSI::MemoryManager::handleMsgFromNetwork (
NetPacket & packet )
::front
ParametricDramDirectoryMSI ::CacheCntlr::getLock
::CacheCntlr::processUpgradeReq CacheBlockInfo::getOwner
ToDirectory
Directory
Directory
::CacheCntlr::processInvReqFrom ParametricDramDirectoryMSI
DramDirectory ::CacheCntlr::getMemoryManager
ParametricDramDirectoryMSI ::CacheCntlr::notifyPrevLevelInsert
DramDirectory ::CacheCntlr::transition
Directory
Directory
::CacheCntlr::processUpgradeRep ::CacheCntlr::getCacheBlockSize
FromDramDirectory
::empty
::CacheCntlr::wakeUpUserThread ParametricDramDirectoryMSI
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ::CStateString
::CacheCntlr::waitForUserThread ::CacheCntlr::invalidateCacheBlock
::make_mshr
::dequeue

6.29.2.22 incrElapsedTime() [1/2]
void ParametricDramDirectoryMSI::MemoryManager::incrElapsedTime (
SubsecondTime latency,
Access
::MemoryManager::incrElapsedTime ParametricDramDirectoryMSI
Directory
Directory
::CacheCntlr::incrementQBSLookupCost ParametricDramDirectoryMSI ::CacheCntlr::handleMsgFromDram
::CacheCntlr::processInvReqFrom Directory
DramDirectory
ParametricDramDirectoryMSI DramDirectory
Directory
6.29.2.23 incrElapsedTime() [2/2]
void ParametricDramDirectoryMSI::MemoryManager::incrElapsedTime (
CachePerfModel::CacheAccess_t access_type,
6.29.2.24 sendMsg()
void ParametricDramDirectoryMSI::MemoryManager::sendMsg (
PrL1PrL2DramDirectoryMSI::ShmemMsg::msg_t msg_type,
MemComponent::component_t sender_mem_component,
MemComponent::component_t receiver_mem_component,
core_id_t receiver,
IntPtr address,
Byte data_buf = NULL,
UInt32 data_length = 0,
HitWhere::where_t where = HitWhere::UNKNOWN,
ShmemPerf perf = NULL,
Access
::CacheCntlr::insertCacheBlock PrevCache
::CacheCntlr::processShRepFromDram ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI
::CacheCntlr::processExReqToDirectory ParametricDramDirectoryMSI
Access
ToDirectory ParametricDramDirectoryMSI
Directory
Directory
DramDirectory
DramDirectory
6.29.2.25 setCacheCntlrAt()
void ParametricDramDirectoryMSI::MemoryManager::setCacheCntlrAt (
core_id_t core_id,
CacheCntlr cache_cntlr ) [inline]
::TLB::lookup
::CacheCntlr::updateUsageBits CacheBlockInfo::getUsage
ParametricDramDirectoryMSI CacheBlockInfo::clearOption
Access
::CacheCntlr::releaseLock ParametricDramDirectoryMSI
::CacheCntlr::waitForNetworkThread ParametricDramDirectoryMSI
PrevCache
::CacheCntlr::insertCacheBlock ::CacheCntlr::getCacheState
FromDramDirectory
Directory
ParametricDramDirectoryMSI ToDirectory
Directory ::MemoryManager::sendMsg
ParametricDramDirectoryMSI DramDirectory
Directory
DramDirectory
Directory
::MemoryManager::handleMsgFromNetwork ReqQueueListTemplate
::empty
::MemoryManager::setCacheCntlrAt ReqQueueListTemplate
::front
::MemoryManager::broadcastMsg
6.29.3.1 m_all_cache_cntlrs
std::map< CoreComponentType, CacheCntlr > ParametricDramDirectoryMSI::MemoryManager::m_all-

_cache_cntlrs [static], [private]
UInt32 ParametricDramDirectoryMSI::MemoryManager::m_cache_block_size [private]
6.29.3.3 m_cache_cntlrs
CacheCntlr ParametricDramDirectoryMSI::MemoryManager::m_cache_cntlrs[MemComponent::LAST_LEVE-
L_CACHE+1] [private]
6.29.3.4 m_cache_perf_models
CachePerfModel ParametricDramDirectoryMSI::MemoryManager::m_cache_perf_models[MemComponent::-
LAST_LEVEL_CACHE+1] [private]
6.29.3.5 m_core_id_master
core_id_t ParametricDramDirectoryMSI::MemoryManager::m_core_id_master [private]
6.29.3.6 m_dram_cache
DramCache ParametricDramDirectoryMSI::MemoryManager::m_dram_cache [private]
6.29.3.7 m_dram_cntlr
PrL1PrL2DramDirectoryMSI::DramCntlr ParametricDramDirectoryMSI::MemoryManager::m_dram_cntlr
[private]
6.29.3.8 m_dram_cntlr_present
bool ParametricDramDirectoryMSI::MemoryManager::m_dram_cntlr_present [private]
6.29.3.9 m_dram_controller_home_lookup
AddressHomeLookup ParametricDramDirectoryMSI::MemoryManager::m_dram_controller_home_lookup
[private]
6.29.3.10 m_dram_directory_cntlr
PrL1PrL2DramDirectoryMSI::DramDirectoryCntlr ParametricDramDirectoryMSI::MemoryManager::m_-
dram_directory_cntlr [private]
6.29.3.11 m_dtlb
TLB ParametricDramDirectoryMSI::MemoryManager::m_dtlb [private]
6.29.3.12 m_enabled
bool ParametricDramDirectoryMSI::MemoryManager::m_enabled [private]
6.29.3.13 m_itlb
TLB ParametricDramDirectoryMSI::MemoryManager::m_itlb [private]
6.29.3.14 m_last_level_cache
MemComponent::component_t ParametricDramDirectoryMSI::MemoryManager::m_last_level_cache [private]
6.29.3.15 m_network_thread_sem
Semaphore ParametricDramDirectoryMSI::MemoryManager::m_network_thread_sem [private]
6.29.3.16 m_nuca_cache
NucaCache ParametricDramDirectoryMSI::MemoryManager::m_nuca_cache [private]
6.29.3.17 m_stlb
TLB ParametricDramDirectoryMSI::MemoryManager::m_stlb [private]
6.29.3.18 m_tag_directory_home_lookup
AddressHomeLookup ParametricDramDirectoryMSI::MemoryManager::m_tag_directory_home_lookup
[private]
6.29.3.19 m_tag_directory_present
bool ParametricDramDirectoryMSI::MemoryManager::m_tag_directory_present [private]
6.29.3.20 m_tlb_miss_parallel
bool ParametricDramDirectoryMSI::MemoryManager::m_tlb_miss_parallel [private]
6.29.3.21 m_tlb_miss_penalty
ComponentLatency ParametricDramDirectoryMSI::MemoryManager::m_tlb_miss_penalty [private]
6.30 ParametricDramDirectoryMSI::MshrEntry Struct Reference 225
6.29.3.22 m_user_thread_sem
Semaphore ParametricDramDirectoryMSI::MemoryManager::m_user_thread_sem [private]
memory_manager.h
memory_manager.cc
6.30 ParametricDramDirectoryMSI::MshrEntry Struct Reference
Collaboration diagram for ParametricDramDirectoryMSI::MshrEntry:
::MshrEntry
+ t_issue
+ t_complete
Public Attributes
SubsecondTime t_issue
SubsecondTime t_complete
6.30.1.1 t_complete
SubsecondTime ParametricDramDirectoryMSI::MshrEntry::t_complete
6.30.1.2 t_issue
SubsecondTime ParametricDramDirectoryMSI::MshrEntry::t_issue
cache_cntlr.h
6.31 NucaCache Class Reference
#include <nuca_cache.h>
6.31 NucaCache Class Reference 227
Collaboration diagram for NucaCache:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_blocksize
# m_name
# m_lock
# m_cache_size
# m_ahl CacheSetInfo + getLock()
+ write_line()
+ CacheBase()
+ ~CacheBase()
+ invalidate()
+ splitAddress()
+ insert()
+ splitAddress()
+ peekBlock()
+ tagToAddress()
+ getDataPtr()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
-m_set_info -m_sets
Cache
- m_enabled
- m_num_accesses
- m_num_hits
- m_cache_type
- m_fault_injector
+ Cache()
+ ~Cache()
+ getSetLock()
+ peekSingleLine()
+ peekBlock()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_cache
NucaCache
- m_core_id
- m_memory_manager
- m_shmem_perf_model
- m_home_lookup
- m_data_access_time
- m_tags_access_time
- m_data_array_bandwidth
- m_queue_model
- m_reads
- m_writes
- m_read_misses
- m_write_misses
+ NucaCache()
+ ~NucaCache()
+ read()
+ write()
- accessDataArray()

NucaCache (MemoryManagerBase memory_manager, ShmemPerfModel shmem_perf_model, Address-
HomeLookup home_lookup, UInt32 cache_block_size, ParametricDramDirectoryMSI::CacheParameters
&parameters)
NucaCache ()
boost::tuple< SubsecondTime, HitWhere::where_t > read (IntPtr address, Byte data_buf, SubsecondTime
now, ShmemPerf perf, bool count)
boost::tuple< SubsecondTime, HitWhere::where_t > write (IntPtr address, Byte data_buf, bool &eviction,
IntPtr &evict_address, Byte evict_buf, SubsecondTime now, bool count)
SubsecondTime accessDataArray (Cache::access_t access, SubsecondTime t_start, ShmemPerf perf)
Private Attributes
core_id_t m_core_id
MemoryManagerBase m_memory_manager
ShmemPerfModel m_shmem_perf_model
AddressHomeLookup m_home_lookup
ComponentLatency m_data_access_time
ComponentLatency m_tags_access_time
ComponentBandwidth m_data_array_bandwidth
Cache m_cache
QueueModel m_queue_model
UInt64 m_reads
UInt64 m_writes
UInt64 m_read_misses
UInt64 m_write_misses
6.31.1.1 NucaCache()
NucaCache::NucaCache (
MemoryManagerBase memory_manager,
ShmemPerfModel shmem_perf_model,
AddressHomeLookup home_lookup,
ParametricDramDirectoryMSI::CacheParameters & parameters )
NucaCache::NucaCache CacheBase::parseAddressHash
6.31.1.2 NucaCache()
NucaCache::NucaCache ( )
6.31.2.1 accessDataArray()
SubsecondTime NucaCache::accessDataArray (
Cache::access_t access,
SubsecondTime t_start,
ShmemPerf perf ) [private]
NucaCache::read
NucaCache::accessDataArray
NucaCache::write
6.31.2.2 read()
boost::tuple< SubsecondTime, HitWhere::where_t > NucaCache::read (

IntPtr address,
Byte data_buf,
SubsecondTime now,
ShmemPerf perf,
bool count )
NucaCache::read Cache::peekSingleLine CacheSet::find
6.31.2.3 write()
boost::tuple< SubsecondTime, HitWhere::where_t > NucaCache::write (

IntPtr address,
Byte data_buf,
bool & eviction,
IntPtr & evict_address,
Byte evict_buf,
SubsecondTime now,
bool count )
CacheSet::insert CacheSet::getReplacement
Index
NucaCache::write CacheBase::tagToAddress
6.31.3.1 m_cache
Cache NucaCache::m_cache [private]
UInt32 NucaCache::m_cache_block_size [private]
6.31.3.3 m_core_id
core_id_t NucaCache::m_core_id [private]
6.31.3.4 m_data_access_time
ComponentLatency NucaCache::m_data_access_time [private]
6.31.3.5 m_data_array_bandwidth
ComponentBandwidth NucaCache::m_data_array_bandwidth [private]
6.31.3.6 m_home_lookup
AddressHomeLookup NucaCache::m_home_lookup [private]
6.31.3.7 m_memory_manager
MemoryManagerBase NucaCache::m_memory_manager [private]
6.31.3.8 m_queue_model
QueueModel NucaCache::m_queue_model [private]
6.31.3.9 m_read_misses
UInt64 NucaCache::m_read_misses [private]
6.31.3.10 m_reads
UInt64 NucaCache::m_reads [private]
6.31.3.11 m_shmem_perf_model
ShmemPerfModel NucaCache::m_shmem_perf_model [private]
6.31.3.12 m_tags_access_time
ComponentLatency NucaCache::m_tags_access_time [private]
6.31.3.13 m_write_misses
UInt64 NucaCache::m_write_misses [private]
6.31.3.14 m_writes
UInt64 NucaCache::m_writes [private]
nuca_cache.h
nuca_cache.cc
6.32 ParametricDramDirectoryMSI::Prefetch Class Reference
Collaboration diagram for ParametricDramDirectoryMSI::Prefetch:
::Prefetch
Public Types
enum prefetch_type_t { NONE, OWN, OTHER }
6.32.1.1 prefetch_type_t
enum ParametricDramDirectoryMSI::Prefetch::prefetch_type_t
6.33 Prefetcher Class Reference 233
Enumerator
NONE
OWN
OTHER
cache_cntlr.h
6.33 Prefetcher Class Reference
#include <prefetcher.h>
Inheritance diagram for Prefetcher:
Prefetcher
+ getNextAddress()
GhbPrefetcher
- m_prefetchWidth
- m_prefetchDepth SimplePrefetcher
- m_lastAddress
- core_id
- m_ghbSize
- shared_cores
- m_ghbHead
- n_flows
- m_generation
- flows_per_core
- m_ghb
- num_prefetches
- m_tableSize
- stop_at_page
- m_tableHead
- n_flow_next
- m_ghbTable
- m_prev_address
- INVALID_DELTA
- INVALID_INDEX + SimplePrefetcher()
+ getNextAddress()
+ GhbPrefetcher()
+ getNextAddress()
+ ~GhbPrefetcher()
Collaboration diagram for Prefetcher:
Prefetcher
+ getNextAddress()
virtual std::vector< IntPtr > getNextAddress (IntPtr current_address, core_id_t core_id)=0
static Prefetcher createPrefetcher (String type, String configName, core_id_t core_id, UInt32 shared_cores)
6.33.1.1 createPrefetcher()
Prefetcher Prefetcher::createPrefetcher (
String type,
String configName,
core_id_t core_id,
UInt32 shared_cores ) [static]
Prefetcher::createPrefetcher
6.34 PrL1CacheBlockInfo Class Reference 235
virtual std::vector<IntPtr> Prefetcher::getNextAddress (

IntPtr current_address,
core_id_t core_id ) [pure virtual]
Implemented in GhbPrefetcher, and SimplePrefetcher.
Prefetcher::getNextAddress ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::CacheCntlr::trainPrefetcher ::MemoryManager::coreInitiateMemory
Access
PrevCache
prefetcher.h
prefetcher.cc
6.34 PrL1CacheBlockInfo Class Reference
#include <pr_l1_cache_block_info.h>
Inheritance diagram for PrL1CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
PrL1CacheBlockInfo
+ PrL1CacheBlockInfo()
Collaboration diagram for PrL1CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
PrL1CacheBlockInfo

PrL1CacheBlockInfo (IntPtr tag=0, CacheState::cstate_t cstate=CacheState::INVALID)
PrL1CacheBlockInfo ()
6.34.1.1 PrL1CacheBlockInfo()
PrL1CacheBlockInfo::PrL1CacheBlockInfo (
IntPtr tag = 0,
CacheState::cstate_t cstate = CacheState::INVALID ) [inline]
PrL1CacheBlockInfo::PrL1CacheBlockInfo ( ) [inline]
pr_l1_cache_block_info.h
6.35 PrL2CacheBlockInfo Class Reference
#include <pr_l2_cache_block_info.h>
Inheritance diagram for PrL2CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
PrL2CacheBlockInfo
- m_cached_loc_bitvec
+ getCachedLoc()
+ setCachedLoc()
+ clearCachedLoc()
+ getCachedLocBitVec()
+ invalidate()
+ clone()
Collaboration diagram for PrL2CacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
PrL2CacheBlockInfo
- m_cached_loc_bitvec
+ getCachedLoc()
+ setCachedLoc()
+ clearCachedLoc()
+ getCachedLocBitVec()
+ invalidate()
+ clone()
PrL2CacheBlockInfo (IntPtr tag=0, CacheState::cstate_t cstate=CacheState::INVALID)

PrL2CacheBlockInfo ()
MemComponent::component_t getCachedLoc ()
void setCachedLoc (MemComponent::component_t cached_loc)
void clearCachedLoc (MemComponent::component_t cached_loc)
UInt32 getCachedLocBitVec ()
void invalidate ()
void clone (CacheBlockInfo cache_block_info)
Private Attributes
UInt32 m_cached_loc_bitvec
PrL2CacheBlockInfo::PrL2CacheBlockInfo (
IntPtr tag = 0,
PrL2CacheBlockInfo::PrL2CacheBlockInfo ( ) [inline]
PrL2CacheBlockInfo
::getCachedLoc
::~PrL2CacheBlockInfo ::setCachedLoc
PrL2CacheBlockInfo
::clearCachedLoc
6.35.2.1 clearCachedLoc()
void PrL2CacheBlockInfo::clearCachedLoc (
MemComponent::component_t cached_loc )
::clearCachedLoc ::~PrL2CacheBlockInfo
6.35.2.2 clone()
void PrL2CacheBlockInfo::clone (
Reimplemented from CacheBlockInfo.
PrL2CacheBlockInfo
::clone
6.35.2.3 getCachedLoc()
MemComponent::component_t PrL2CacheBlockInfo::getCachedLoc ( )
::getCachedLoc ::~PrL2CacheBlockInfo
6.35.2.4 getCachedLocBitVec()
UInt32 PrL2CacheBlockInfo::getCachedLocBitVec ( ) [inline]
PrL2CacheBlockInfo
::invalidate
PrL2CacheBlockInfo
::getCachedLocBitVec CacheBlockInfo::getTag
PrL2CacheBlockInfo
::clone
void PrL2CacheBlockInfo::invalidate (
void ) [virtual]
PrL2CacheBlockInfo
::invalidate
::invalidate ::getCachedLocBitVec
6.35.2.6 setCachedLoc()
void PrL2CacheBlockInfo::setCachedLoc (
MemComponent::component_t cached_loc )
::setCachedLoc ::~PrL2CacheBlockInfo
6.35.3.1 m_cached_loc_bitvec
UInt32 PrL2CacheBlockInfo::m_cached_loc_bitvec [private]
pr_l2_cache_block_info.cc
6.36 ReqQueueListTemplate< T_Req > Class Template Reference 245
6.36 ReqQueueListTemplate< T_Req > Class Template Reference
#include <req_queue_list_template.h>
Inheritance diagram for ReqQueueListTemplate< T_Req >:
< T_Req >
- m_req_queue_list
+ ReqQueueListTemplate()
+ enqueue()
+ dequeue()
+ front()
+ back()
+ size()
+ empty()
< CacheDirectoryWaiter >
< CacheDirectoryWaiter >
- m_req_queue_list
+ enqueue()
+ dequeue()
+ front()
+ back()
+ size()
+ empty()
Collaboration diagram for ReqQueueListTemplate< T_Req >:
< T_Req >
- m_req_queue_list
+ enqueue()
+ dequeue()
+ front()
+ back()
+ size()
+ empty()
ReqQueueListTemplate ()
ReqQueueListTemplate ()
void enqueue (IntPtr address, T_Req shmem_req)
T_Req dequeue (IntPtr address)
T_Req front (IntPtr address)
T_Req back (IntPtr address)
UInt32 size (IntPtr address)
bool empty (IntPtr address)
Private Attributes
std::map< IntPtr, std::queue< T_Req > > m_req_queue_list
6.36.1.1 ReqQueueListTemplate()
template<class T_Req>
ReqQueueListTemplate< T_Req >::ReqQueueListTemplate ( ) [inline]
< CacheDirectoryWaiter
::ReqQueueListTemplate
>::empty
6.36.1.2 ReqQueueListTemplate()
ReqQueueListTemplate< T_Req >::ReqQueueListTemplate ( ) [inline]
::~ReqQueueListTemplate
>::empty
6.36.2.1 back()
template<class T_Req >

T_Req ReqQueueListTemplate< T_Req >::back (
IntPtr address )
::back
>::~ReqQueueListTemplate
6.36.2.2 dequeue()

T_Req ReqQueueListTemplate< T_Req >::dequeue (
IntPtr address )
Directory
::dequeue
>::empty
6.36.2.3 empty()

bool ReqQueueListTemplate< T_Req >::empty (
IntPtr address )
Directory
::empty
>::dequeue
6.36.2.4 enqueue()
void ReqQueueListTemplate< T_Req >::enqueue (
IntPtr address,
T_Req shmem_req )

Access
::enqueue
>::empty
6.36.2.5 front()

T_Req ReqQueueListTemplate< T_Req >::front (
IntPtr address )
Directory
::front
>::empty
6.36.2.6 size()

UInt32 ReqQueueListTemplate< T_Req >::size (
IntPtr address )

Access
::size
>::empty
6.36.3.1 m_req_queue_list
std::map<IntPtr, std::queue<T_Req> > ReqQueueListTemplate< T_Req >::m_req_queue_list [private]
req_queue_list_template.h
6.37 SharedCacheBlockInfo Class Reference
#include <shared_cache_block_info.h>
Inheritance diagram for SharedCacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
+ SharedCacheBlockInfo()
+ ~SharedCacheBlockInfo()
+ invalidate()
+ clone()
6.37 SharedCacheBlockInfo Class Reference 251
Collaboration diagram for SharedCacheBlockInfo:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
+ SharedCacheBlockInfo()
+ ~SharedCacheBlockInfo()
+ invalidate()
+ clone()
SharedCacheBlockInfo (IntPtr tag=0, CacheState::cstate_t cstate=CacheState::INVALID)

SharedCacheBlockInfo ()
void invalidate ()
void clone (CacheBlockInfo cache_block_info)
6.37.1.1 SharedCacheBlockInfo()
SharedCacheBlockInfo::SharedCacheBlockInfo (
IntPtr tag = 0,
6.37.1.2 SharedCacheBlockInfo()
SharedCacheBlockInfo::SharedCacheBlockInfo ( ) [inline]
::invalidate
::~SharedCacheBlockInfo CacheBlockInfo::getTag
::clone
6.37.2.1 clone()
void SharedCacheBlockInfo::clone (
::clone
6.37 SharedCacheBlockInfo Class Reference 253
void SharedCacheBlockInfo::invalidate (
void ) [virtual]
::invalidate
PrevCache ::CacheCntlr::processMemOpFromCore ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
SharedCacheBlockInfo ParametricDramDirectoryMSI
::invalidate ::CacheCntlr::doPrefetch ParametricDramDirectoryMSI
::~SharedCacheBlockInfo
shared_cache_block_info.h
shared_cache_block_info.cc
6.38 SimplePrefetcher Class Reference
#include <simple_prefetcher.h>
Inheritance diagram for SimplePrefetcher:
Prefetcher
+ getNextAddress()
SimplePrefetcher
- core_id
- shared_cores
- n_flows
- flows_per_core
- num_prefetches
- stop_at_page
- n_flow_next
- m_prev_address
+ SimplePrefetcher()
+ getNextAddress()
6.38 SimplePrefetcher Class Reference 255
Collaboration diagram for SimplePrefetcher:
Prefetcher
+ getNextAddress()
SimplePrefetcher
- core_id
- shared_cores
- n_flows
- flows_per_core
- num_prefetches
- stop_at_page
- n_flow_next
- m_prev_address
+ SimplePrefetcher()
+ getNextAddress()
SimplePrefetcher (String configName, core_id_t core_id, UInt32 shared_cores)

virtual std::vector< IntPtr > getNextAddress (IntPtr current_address, core_id_t core_id)
Private Attributes
const core_id_t core_id

const UInt32 shared_cores
const UInt32 n_flows
const bool flows_per_core
const UInt32 num_prefetches
const bool stop_at_page
UInt32 n_flow_next
std::vector< std::vector< IntPtr > > m_prev_address
6.38.1.1 SimplePrefetcher()
SimplePrefetcher::SimplePrefetcher (
String configName,
core_id_t core_id,
UInt32 shared_cores )
std::vector< IntPtr > SimplePrefetcher::getNextAddress (

IntPtr current_address,
core_id_t core_id ) [virtual]
Implements Prefetcher.
6.38.3.1 core_id
const core_id_t SimplePrefetcher::core_id [private]
6.38.3.2 flows_per_core
const bool SimplePrefetcher::flows_per_core [private]
6.38.3.3 m_prev_address
std::vector<std::vector<IntPtr> > SimplePrefetcher::m_prev_address [private]
6.38.3.4 n_flow_next
UInt32 SimplePrefetcher::n_flow_next [private]
6.39 GhbPrefetcher::TableEntry Struct Reference 257
6.38.3.5 n_flows
const UInt32 SimplePrefetcher::n_flows [private]
6.38.3.6 num_prefetches
const UInt32 SimplePrefetcher::num_prefetches [private]
6.38.3.7 shared_cores
const UInt32 SimplePrefetcher::shared_cores [private]
6.38.3.8 stop_at_page
const bool SimplePrefetcher::stop_at_page [private]
simple_prefetcher.h
simple_prefetcher.cc
6.39 GhbPrefetcher::TableEntry Struct Reference
Collaboration diagram for GhbPrefetcher::TableEntry:
GhbPrefetcher::TableEntry
+ ghbIndex
+ delta
+ generation
+ TableEntry()
TableEntry ()
Public Attributes
UInt32 ghbIndex
SInt64 delta
UInt32 generation
6.39.1.1 TableEntry()
GhbPrefetcher::TableEntry::TableEntry ( ) [inline]
6.39.2.1 delta
SInt64 GhbPrefetcher::TableEntry::delta
6.39.2.2 generation
UInt32 GhbPrefetcher::TableEntry::generation
6.39.2.3 ghbIndex
UInt32 GhbPrefetcher::TableEntry::ghbIndex
ghb_prefetcher.h
6.40 ParametricDramDirectoryMSI::TLB Class Reference 259
6.40 ParametricDramDirectoryMSI::TLB Class Reference
#include <tlb.h>
Collaboration diagram for ParametricDramDirectoryMSI::TLB:
CacheBlockInfo
+ BitsUsedOffset
- m_tag
- m_cstate
- m_owner
- m_used
- m_options
- option_names
+ CacheBlockInfo()
+ ~CacheBlockInfo()
+ invalidate()
+ clone()
+ isValid()
+ getTag()
+ getCState()
+ setTag()
+ setCState()
+ getOwner()
+ setOwner()
+ hasOption()
+ setOption()
+ clearOption()
+ getUsage()
+ updateUsage()
+ updateUsage()
+ create()
+ getOptionName()
#m_cache_block_info
_array
CacheSet
+ m_coming_EW_type
+ m_block_op
# m_blocks
# m_blocksize
# m_name
# m_lock
# m_cache_size
# m_ahl CacheSetInfo
+ getLock()
+ write_line()
+ CacheBase()
+ ~CacheBase()
+ invalidate()
+ splitAddress()
+ insert()
+ splitAddress()
+ peekBlock()
+ tagToAddress()
+ getDataPtr()
+ getName()
+ getBlockSize()
+ getNumSets()
+ createCacheSet()
+ parsePolicyType()
-m_set_info -m_sets
Cache
- m_enabled
- m_num_accesses
- m_num_hits
- m_cache_type
- m_fault_injector
+ Cache()
+ ~Cache()
+ getSetLock()
+ peekSingleLine()
+ peekBlock()
+ updateCounters()
+ updateHits()
+ enable()
+ disable()
-m_cache
ParametricDramDirectoryMSI::TLB
- m_size
- m_associativity
- m_access
- m_miss
- SIM_PAGE_SHIFT -m_next_level
- SIM_PAGE_SIZE
- SIM_PAGE_MASK
+ TLB()
+ lookup()
+ allocate()

TLB (String name, String cfgname, core_id_t core_id, UInt32 num_entries, UInt32 associativity, TLB next-
_level)
bool lookup (IntPtr address, SubsecondTime now, bool allocate_on_miss=true)

void allocate (IntPtr address, SubsecondTime now)
Private Attributes
UInt32 m_size
Cache m_cache
TLB m_next_level
UInt64 m_access
UInt64 m_miss
static const UInt32 SIM_PAGE_SHIFT = 12

static const IntPtr SIM_PAGE_SIZE = (1L << SIM_PAGE_SHIFT)
static const IntPtr SIM_PAGE_MASK = (SIM_PAGE_SIZE - 1)
6.40.1.1 TLB()
ParametricDramDirectoryMSI::TLB::TLB (
String name,
String cfgname,
core_id_t core_id,
UInt32 num_entries,
TLB next_level )
6.40 ParametricDramDirectoryMSI::TLB Class Reference 261
6.40.2.1 allocate()
void ParametricDramDirectoryMSI::TLB::allocate (
IntPtr address,
SubsecondTime now )
CacheBlockInfo::setTag Index
::TLB::allocate
CacheSet::find
ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI ParametricDramDirectoryMSI
::TLB::allocate ::TLB::lookup ::MemoryManager::accessTLB ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.40.2.2 lookup()
bool ParametricDramDirectoryMSI::TLB::lookup (
IntPtr address,
SubsecondTime now,
bool allocate_on_miss = true )
ParametricDramDirectoryMSI CacheBlockInfo::create
::TLB::lookup
ParametricDramDirectoryMSI CacheBlockInfo::setTag Index
::TLB::allocate
CacheSet::find
::TLB::lookup ::MemoryManager::accessTLB ::MemoryManager::setCacheCntlrAt ::MemoryManager::MemoryManager
Access
6.40.3.1 m_access
UInt64 ParametricDramDirectoryMSI::TLB::m_access [private]
UInt32 ParametricDramDirectoryMSI::TLB::m_associativity [private]
6.40.3.3 m_cache
Cache ParametricDramDirectoryMSI::TLB::m_cache [private]
6.40.3.4 m_miss
UInt64 ParametricDramDirectoryMSI::TLB::m_miss [private]
6.40.3.5 m_next_level
TLB ParametricDramDirectoryMSI::TLB::m_next_level [private]
6.40.3.6 m_size
UInt32 ParametricDramDirectoryMSI::TLB::m_size [private]
6.40.3.7 SIM_PAGE_MASK
const IntPtr ParametricDramDirectoryMSI::TLB::SIM_PAGE_MASK = (SIM_PAGE_SIZE - 1) [static],

[private]
6.41 ParametricDramDirectoryMSI::Transition Class Reference 263
6.40.3.8 SIM_PAGE_SHIFT
const UInt32 ParametricDramDirectoryMSI::TLB::SIM_PAGE_SHIFT = 12 [static], [private]
6.40.3.9 SIM_PAGE_SIZE
const IntPtr ParametricDramDirectoryMSI::TLB::SIM_PAGE_SIZE = (1L << SIM_PAGE_SHIFT) [static],

[private]
tlb.h
tlb.cc
6.41 ParametricDramDirectoryMSI::Transition Class Reference
Collaboration diagram for ParametricDramDirectoryMSI::Transition:
::Transition
Public Types
enum reason_t {
REASON_FIRST = 0, CORE_RD = REASON_FIRST, CORE_WR, CORE_RDEX,
UPGRADE, EVICT, BACK_INVAL, COHERENCY,
NUM_REASONS }
6.41.1.1 reason_t
enum ParametricDramDirectoryMSI::Transition::reason_t
Enumerator
REASON_FIRST
CORE_RD
CORE_WR
CORE_RDEX
UPGRADE
EVICT
BACK_INVAL
COHERENCY
NUM_REASONS
cache_cntlr.h
Chapter 7
File Documentation
7.1 cache.cc File Reference
#include "simulator.h"
#include "cache.h"
#include "log.h"
Include dependency graph for cache.cc:
cache.cc
simulator.h cache.h
cache_set.h utils.h hash_map_set.h cache_perf_model.h shmem_perf_model.h core.h fault_injection.h
cstring lock.h random.h cache_block_info.h log.h
cache_base.h cache_state.h
fixed_types.h cassert
7.2 cache.h File Reference
#include "cache_base.h"
#include "cache_set.h"
#include "cache_block_info.h"
#include "utils.h"
#include "hash_map_set.h"
#include "cache_perf_model.h"
#include "shmem_perf_model.h"
#include "log.h"
#include "core.h"
266 File Documentation
#include "fault_injection.h"
Include dependency graph for cache.h:
cache.h
cache_block_info.h lock.h random.h cstring log.h
cache_state.h cache_base.h
cassert fixed_types.h
This graph shows which files directly or indirectly include this file:
cache.h
cache.cc cache_cntlr.h tlb.h
memory_manager.h nuca_cache.h tlb.cc
cache_cntlr.cc nuca_cache.cc memory_manager.cc
Classes
class Cache
Functions
template<class T >
UInt32 moduloHashFn (T key, UInt32 hash_fn_param, UInt32 num_buckets)
7.2.1 Function Documentation
7.3 cache_atd.cc File Reference 267
7.2.1.1 moduloHashFn()
template<class T >
UInt32 moduloHashFn (
T key,
UInt32 hash_fn_param,
UInt32 num_buckets )
7.3 cache_atd.cc File Reference
#include "cache_atd.h"
#include "pr_l1_cache_block_info.h"
#include "stats.h"
#include "config.hpp"
#include "rng.h"
Include dependency graph for cache_atd.cc:
cache_atd.cc
cache_atd.h stats.h config.hpp rng.h
core.h unordered_map cache_set.h pr_l1_cache_block_info.h
lock.h random.h log.h cstring cache_block_info.h
7.4 cache_atd.h File Reference
#include "fixed_types.h"
#include "core.h"
#include <unordered_map>
Include dependency graph for cache_atd.h:
cache_atd.h
cache_set.h core.h unordered_map
cache_block_info.h log.h cstring lock.h random.h
cache_atd.h
cache_atd.cc cache_cntlr.cc
Classes
class ATD
7.5 cache_base.cc File Reference
#include "utils.h"
#include "log.h"
#include "rng.h"
#include "address_home_lookup.h"
7.6 cache_base.h File Reference 269
Include dependency graph for cache_base.cc:
cache_base.cc
cache_base.h utils.h log.h rng.h address_home_lookup.h
fixed_types.h
7.6 cache_base.h File Reference
Include dependency graph for cache_base.h:
cache_base.h
fixed_types.h
cache_base.h
cache_block_info.h cache_base.cc
shared_cache_block
cache_set.h pr_l1_cache_block_info.h pr_l2_cache_block_info.h
_info.h
shared_cache_block
cache_set_mru.h cache_set_plru.h cache_set_random.h cache_set_round_robin.h cache_set_nmru.h cache_set_nru.h cache_set_lru.h cache.h cache_block_info.cc cache_atd.h pr_l2_cache_block_info.cc
_info.cc
cache_set_mrut.h cache_set_mru.cc cache_set_plru.cc cache_set_random.cc cache_set_round_robin.cc cache_set_nmru.cc cache_set_nru.cc cache_set_ew_lru.h cache_set_lru.cc cache_set_srrip.h cache.cc tlb.h cache_cntlr.h cache_atd.cc
cache_set_mrut.cc cache_set_ew_lru.cc cache_set_ew_srrip.h cache_set_srrip.cc tlb.cc memory_manager.h nuca_cache.h
cache_set.cc cache_set_ew_srrip.cc memory_manager.cc cache_cntlr.cc nuca_cache.cc
Classes
class CacheBase
Cache_Base class.
Macros
#define k_KILO 1024
#define k_MEGA (k_KILOk_KILO)
#define k_GIGA (k_KILOk_MEGA)
7.6.1 Macro Definition Documentation
7.6.1.1 k_GIGA
#define k_GIGA (k_KILOk_MEGA)
7.6.1.2 k_KILO
#define k_KILO 1024
7.6.1.3 k_MEGA
#define k_MEGA (k_KILOk_KILO)
7.7 cache_block_info.cc File Reference
#include "shared_cache_block_info.h"
#include "log.h"
Include dependency graph for cache_block_info.cc:
cache_block_info.cc
shared_cache_block
pr_l1_cache_block_info.h pr_l2_cache_block_info.h log.h
_info.h
cache_block_info.h mem_component.h
7.8 cache_block_info.h File Reference 271
7.8 cache_block_info.h File Reference
#include "cache_state.h"
Include dependency graph for cache_block_info.h:
cache_block_info.h
cache_block_info.h
shared_cache_block
pr_l2_cache_block_info.h pr_l1_cache_block_info.h cache_set.h
_info.h
shared_cache_block
cache_block_info.cc pr_l2_cache_block_info.cc cache.h cache_atd.h cache_set_plru.h cache_set_mru.h cache_set_round_robin.h cache_set_random.h cache_set_nru.h cache_set_nmru.h cache_set_lru.h
_info.cc
cache_cntlr.h cache.cc tlb.h cache_atd.cc cache_set_plru.cc cache_set_mru.cc cache_set_mrut.h cache_set_round_robin.cc cache_set_random.cc cache_set_nru.cc cache_set_nmru.cc cache_set_ew_lru.h cache_set_lru.cc cache_set_srrip.h
memory_manager.h nuca_cache.h tlb.cc cache_set_mrut.cc cache_set_ew_lru.cc cache_set_ew_srrip.h cache_set_srrip.cc
cache_cntlr.cc memory_manager.cc nuca_cache.cc cache_set.cc cache_set_ew_srrip.cc
Classes
class CacheBlockInfo
class CacheCntlr
7.9 cache_cntlr.cc File Reference
#include "cache_cntlr.h"
#include "log.h"
#include "memory_manager.h"
#include "core_manager.h"
#include "fault_injection.h"
#include "hooks_manager.h"
#include "cache_atd.h"
#include "shmem_perf.h"
#include <cstring>
Include dependency graph for cache_cntlr.cc:
cache_cntlr.cc
C:/Users/Nora S. Almaayouf C:/Users/Nora S. Almaayouf C:/Users/Nora S. Almaayouf C:/Users/Nora S. Almaayouf C:/Users/Nora S. Almaayouf C:/Users/Nora S. Almaayouf
/Documents/NetBeansProjects /Documents/NetBeansProjects /Documents/NetBeansProjects /Documents/NetBeansProjects /Documents/NetBeansProjects /Documents/NetBeansProjects
memory_manager.h hit_where.h /Sniper/sniper-6.1/common/core directory.h /Sniper/sniper-6.1/common/core /Sniper/sniper-6.1/common/core /Sniper/sniper-6.1/common/core req_queue_list_template.h /Sniper/sniper-6.1/common/core dram_perf_model.h dram_cntlr_interface.h /Sniper/sniper-6.1/common/core coherency_protocol.h core_manager.h simulator.h config.hpp hooks_manager.h shmem_perf.h
/memory_subsystem/pr_l1_pr_l2 /memory_subsystem/pr_l1_pr_l2 /memory_subsystem/pr_l1_pr_l2 /memory_subsystem/pr_l1_pr_l2 /memory_subsystem/pr_l1_pr_l2 /memory_subsystem/pr_l1_pr_l2
_dram_directory_msi/dram_directory_cache.h _dram_directory_msi/req_queue_list.h _dram_directory_msi/shmem_req.h _dram_directory_msi/shmem_msg.h _dram_directory_msi/dram_cntlr.h _dram_directory_msi/shmem_perf.h
../pr_l1_pr_l2_dram ../pr_l1_pr_l2_dram
cache_cntlr.h _directory_msi/dram _directory_msi/dram memory_manager_base.h
_directory_cntlr.h _cntlr.h
../pr_l1_pr_l2_dram shared_cache_block
cache_atd.h cache.h stats.h boost/tuple/tuple.hpp setlock.h contention_model.h prefetcher.h req_queue_list_template.h address_home_lookup.h semaphore.h subsecond_time.h
_directory_msi/shmem_msg.h _info.h
fault_injection.h core.h unordered_map cache_set.h shmem_perf_model.h vector queue map mem_component.h
cstring log.h lock.h cache_base.h
fixed_types.h
Namespaces
Macros
#define MYLOG(...) {}
Functions
char ParametricDramDirectoryMSI::CStateString (CacheState::cstate_t cstate)

const char ParametricDramDirectoryMSI::ReasonString (Transition::reason_t reason)
MshrEntry ParametricDramDirectoryMSI::make_mshr (SubsecondTime t_issue, SubsecondTime t_-
complete)
Variables
Lock iolock
7.9.1.1 MYLOG
#define MYLOG(
... ) {}
7.9.2 Variable Documentation
7.9.2.1 iolock
Lock iolock
7.10 cache_cntlr.h File Reference 273
7.10 cache_cntlr.h File Reference
#include "core.h"
#include "cache.h"
#include "prefetcher.h"
#include "../pr_l1_pr_l2_dram_directory_msi/shmem_msg.h"
#include "mem_component.h"
#include "semaphore.h"
#include "lock.h"
#include "setlock.h"
#include "contention_model.h"
#include "req_queue_list_template.h"
#include "stats.h"
#include "subsecond_time.h"
#include "boost/tuple/tuple.hpp"
Include dependency graph for cache_cntlr.h:
cache_cntlr.h
shared_cache_block ../pr_l1_pr_l2_dram
prefetcher.h cache.h req_queue_list_template.h address_home_lookup.h semaphore.h setlock.h contention_model.h stats.h subsecond_time.h boost/tuple/tuple.hpp
_info.h _directory_msi/shmem_msg.h
vector mem_component.h core.h utils.h hash_map_set.h cache_perf_model.h fault_injection.h cache_set.h shmem_perf_model.h map queue
cache_block_info.h lock.h cstring random.h log.h
cache_cntlr.h
memory_manager.h nuca_cache.h
cache_cntlr.cc memory_manager.cc nuca_cache.cc
Classes
class ParametricDramDirectoryMSI::Transition
class ParametricDramDirectoryMSI::Prefetch
class ParametricDramDirectoryMSI::CacheParameters
class ParametricDramDirectoryMSI::CacheCntlrList
class ParametricDramDirectoryMSI::CacheDirectoryWaiter
struct ParametricDramDirectoryMSI::MshrEntry
class ParametricDramDirectoryMSI::CacheMasterCntlr
class ParametricDramDirectoryMSI::CacheCntlr
Namespaces
Macros
#define PREFETCH_MAX_QUEUE_LENGTH 32
#define PREFETCH_INTERVAL SubsecondTime::NS(1)
Typedefs
typedef ReqQueueListTemplate< CacheDirectoryWaiter > ParametricDramDirectoryMSI::CacheDirectory-

WaiterMap
typedef std::unordered_map< IntPtr, MshrEntry > ParametricDramDirectoryMSI::Mshr
7.10.1.1 PREFETCH_INTERVAL
#define PREFETCH_INTERVAL SubsecondTime::NS(1)
7.10.1.2 PREFETCH_MAX_QUEUE_LENGTH
#define PREFETCH_MAX_QUEUE_LENGTH 32
7.11 cache_set.cc File Reference
#include "cache_set_lru.h"
#include "cache_set_ew_lru.h"
#include "cache_set_ew_srrip.h"
#include "cache_set_mrut.h"
#include "cache_set_mru.h"
#include "cache_set_nmru.h"
#include "cache_set_nru.h"
#include "cache_set_plru.h"
#include "cache_set_random.h"
#include "cache_set_round_robin.h"
#include "cache_set_srrip.h"
#include "log.h"
#include "config.h"
7.12 cache_set.h File Reference 275
Include dependency graph for cache_set.cc:
cache_set.cc
cache_set_ew_srrip.h cache_set_mrut.h simulator.h config.h config.hpp
cache_set_ew_lru.h cache_set_srrip.h cache_set_mru.h cache_set_plru.h cache_set_round_robin.h
cache_set_lru.h cache_set_nmru.h cache_set_nru.h cache_set_random.h
cache_set.h
log.h cache_block_info.h lock.h random.h cstring
7.12 cache_set.h File Reference
#include "lock.h"
#include "random.h"
#include "log.h"
#include <cstring>
Include dependency graph for cache_set.h:
cache_set.h
cache_block_info.h lock.h random.h log.h cstring
cache_set.h
cache.h cache_atd.h cache_set_lru.h cache_set_mru.h cache_set_nmru.h cache_set_nru.h cache_set_plru.h cache_set_random.h cache_set_round_robin.h
cache.cc cache_cntlr.h tlb.h cache_atd.cc cache_set_srrip.h cache_set_lru.cc cache_set_ew_lru.h cache_set_mrut.h cache_set_mru.cc cache_set_nmru.cc cache_set_nru.cc cache_set_plru.cc cache_set_random.cc cache_set_round_robin.cc
nuca_cache.h memory_manager.h tlb.cc cache_set_ew_srrip.h cache_set_srrip.cc cache_set_ew_lru.cc cache_set_mrut.cc
nuca_cache.cc memory_manager.cc cache_cntlr.cc cache_set_ew_srrip.cc cache_set.cc
Classes
class CacheSetInfo
class CacheSet
Cache_Set class.
7.13 cache_set_ew_lru.cc File Reference
#include "cache_set_ew_lru.h"
#include "log.h"
#include "stats.h"
Include dependency graph for cache_set_ew_lru.cc:
cache_set_ew_lru.cc
cache_set_ew_lru.h stats.h
cache_set_lru.h
cache_set.h
7.14 cache_set_ew_lru.h File Reference
7.15 cache_set_ew_srrip.cc File Reference 277
Include dependency graph for cache_set_ew_lru.h:
cache_set_ew_lru.h
cache_set_lru.h
cache_set.h
cache_set_ew_lru.h
cache_set.cc cache_set_ew_lru.cc
Classes
class CacheSetEWLRU
struct CacheSetEWLRU::ew_array
7.15 cache_set_ew_srrip.cc File Reference
#include "cache_set_ew_srrip.h"
#include "log.h"
Include dependency graph for cache_set_ew_srrip.cc:
cache_set_ew_srrip.cc
cache_set_ew_srrip.h simulator.h config.hpp
cache_set_srrip.h
cache_set_lru.h
cache_set.h
7.16 cache_set_ew_srrip.h File Reference
7.17 cache_set_lru.cc File Reference 279
Include dependency graph for cache_set_ew_srrip.h:
cache_set_srrip.h
cache_set_lru.h
cache_set.h
cache_set.cc cache_set_ew_srrip.cc
Classes
class CacheSetEWSRRIP
7.17 cache_set_lru.cc File Reference
#include "log.h"
#include "stats.h"
Include dependency graph for cache_set_lru.cc:
cache_set_lru.cc
cache_set_lru.h stats.h
cache_set.h
7.18 cache_set_lru.h File Reference
Include dependency graph for cache_set_lru.h:
cache_set_lru.h
cache_set.h
7.19 cache_set_mru.cc File Reference 281
cache_set_lru.h
cache_set_ew_lru.h cache_set_srrip.h cache_set_lru.cc
cache_set_ew_lru.cc cache_set_srrip.cc cache_set_ew_srrip.h
Classes
class CacheSetInfoLRU
class CacheSetLRU
7.19 cache_set_mru.cc File Reference
#include "log.h"
Include dependency graph for cache_set_mru.cc:
cache_set_mru.cc
cache_set_mru.h
cache_set.h
7.20 cache_set_mru.h File Reference
Include dependency graph for cache_set_mru.h:
cache_set_mru.h
cache_set.h
cache_set_mru.h
cache_set_mrut.h cache_set_mru.cc
cache_set.cc cache_set_mrut.cc
Classes
class CacheSetMRU
7.21 cache_set_mrut.cc File Reference
#include "cache_set_mrut.h"
7.22 cache_set_mrut.h File Reference 283
#include "log.h"
Include dependency graph for cache_set_mrut.cc:
cache_set_mrut.cc
cache_set_mrut.h
cache_set_mru.h
cache_set.h
log.h cache_block_info.h lock.h random.h cstring
7.22 cache_set_mrut.h File Reference
Include dependency graph for cache_set_mrut.h:
cache_set_mrut.h
cache_set_mru.h
cache_set.h
cache_set_mrut.h
cache_set.cc cache_set_mrut.cc
Classes
class CacheSetMRUT
7.23 cache_set_nmru.cc File Reference
#include "cache_set_nmru.h"
#include "log.h"
7.24 cache_set_nmru.h File Reference 285
Include dependency graph for cache_set_nmru.cc:
cache_set_nmru.cc
cache_set_nmru.h
cache_set.h
7.24 cache_set_nmru.h File Reference
Include dependency graph for cache_set_nmru.h:
cache_set_nmru.h
cache_set.h
cache_set_nmru.h
cache_set.cc cache_set_nmru.cc
Classes
class CacheSetNMRU
7.25 cache_set_nru.cc File Reference
#include "cache_set_nru.h"
#include "log.h"
Include dependency graph for cache_set_nru.cc:
cache_set_nru.cc
cache_set_nru.h
cache_set.h
7.26 cache_set_nru.h File Reference 287
7.26 cache_set_nru.h File Reference
Include dependency graph for cache_set_nru.h:
cache_set_nru.h
cache_set.h
cache_set_nru.h
cache_set.cc cache_set_nru.cc
Classes
class CacheSetNRU
7.27 cache_set_plru.cc File Reference
#include "cache_set_plru.h"
#include "log.h"
Include dependency graph for cache_set_plru.cc:
cache_set_plru.cc
cache_set_plru.h
cache_set.h
7.28 cache_set_plru.h File Reference
Include dependency graph for cache_set_plru.h:
cache_set_plru.h
cache_set.h
7.29 cache_set_random.cc File Reference 289
cache_set_plru.h
cache_set.cc cache_set_plru.cc
Classes
class CacheSetPLRU
7.29 cache_set_random.cc File Reference
#include "cache_set_random.h"
#include "log.h"
#include <time.h>
Include dependency graph for cache_set_random.cc:
cache_set_random.cc
cache_set_random.h time.h
cache_set.h
7.30 cache_set_random.h File Reference
Include dependency graph for cache_set_random.h:
cache_set_random.h
cache_set.h
cache_set_random.h
cache_set.cc cache_set_random.cc
Classes
class CacheSetRandom
7.31 cache_set_round_robin.cc File Reference
#include "cache_set_round_robin.h"
7.32 cache_set_round_robin.h File Reference 291
Include dependency graph for cache_set_round_robin.cc:
cache_set_round_robin.cc
cache_set.h
7.32 cache_set_round_robin.h File Reference
Include dependency graph for cache_set_round_robin.h:
cache_set.h
cache_set.cc cache_set_round_robin.cc
Classes
class CacheSetRoundRobin
7.33 cache_set_srrip.cc File Reference
#include "log.h"
Include dependency graph for cache_set_srrip.cc:
cache_set_srrip.cc
cache_set_srrip.h simulator.h config.hpp
cache_set_lru.h
cache_set.h
7.34 cache_set_srrip.h File Reference 293
7.34 cache_set_srrip.h File Reference
Include dependency graph for cache_set_srrip.h:
cache_set_srrip.h
cache_set_lru.h
cache_set.h
cache_set_srrip.h
cache_set_ew_srrip.h cache_set_srrip.cc
Classes
class CacheSetSRRIP
7.35 cache_state.h File Reference
#include <cassert>
Include dependency graph for cache_state.h:
cache_state.h
cache_state.h
cache_block_info.h
shared_cache_block
cache_set.h pr_l1_cache_block_info.h pr_l2_cache_block_info.h
_info.h
shared_cache_block
cache_set_random.h cache_set_mru.h cache_set_round_robin.h cache_set_nmru.h cache_set_nru.h cache_set_plru.h cache_set_lru.h cache_atd.h cache.h cache_block_info.cc pr_l2_cache_block_info.cc
_info.cc
cache_set_random.cc cache_set_mrut.h cache_set_mru.cc cache_set_round_robin.cc cache_set_nmru.cc cache_set_nru.cc cache_set_plru.cc cache_set_ew_lru.h cache_atd.cc cache_set_lru.cc cache_set_srrip.h tlb.h cache.cc cache_cntlr.h
cache_set_mrut.cc cache_set_ew_lru.cc cache_set_ew_srrip.h cache_set_srrip.cc tlb.cc nuca_cache.h memory_manager.h
cache_set.cc cache_set_ew_srrip.cc nuca_cache.cc memory_manager.cc cache_cntlr.cc
Classes
class CacheState
7.36 ghb_prefetcher.cc File Reference
#include "ghb_prefetcher.h"
#include <algorithm>
7.37 ghb_prefetcher.h File Reference 295
Include dependency graph for ghb_prefetcher.cc:
ghb_prefetcher.cc
ghb_prefetcher.h simulator.h config.hpp algorithm
prefetcher.h
fixed_types.h vector
7.37 ghb_prefetcher.h File Reference
Include dependency graph for ghb_prefetcher.h:
ghb_prefetcher.h
prefetcher.h
ghb_prefetcher.h
ghb_prefetcher.cc prefetcher.cc
Classes
class GhbPrefetcher
struct GhbPrefetcher::GHBEntry
struct GhbPrefetcher::TableEntry
7.38 memory_manager.cc File Reference
#include "core_manager.h"
#include "memory_manager.h"
#include "nuca_cache.h"
#include "dram_cache.h"
#include "tlb.h"
#include "log.h"
#include "dvfs_manager.h"
#include "itostr.h"
#include "instruction.h"
#include "distribution.h"
#include "topology_info.h"
#include <algorithm>
Include dependency graph for memory_manager.cc:
memory_manager.cc
core_manager.h memory_manager.h nuca_cache.h dram_cache.h simulator.h dvfs_manager.h itostr.h instruction.h config.hpp distribution.h topology_info.h algorithm
tlb.h memory_manager_base.h _directory_msi/dram _directory_msi/dram cache_cntlr.h hit_where.h
cache.h address_home_lookup.h semaphore.h setlock.h contention_model.h stats.h req_queue_list_template.h prefetcher.h subsecond_time.h boost/tuple/tuple.hpp
utils.h hash_map_set.h cache_perf_model.h fault_injection.h cache_set.h shmem_perf_model.h core.h mem_component.h queue map vector
log.h random.h cache_block_info.h lock.h
Namespaces
7.39 memory_manager.h File Reference 297
Macros
#define MYLOG(...) {}
7.38.1.1 MYLOG
#define MYLOG(
... ) {}
7.39 memory_manager.h File Reference
#include "memory_manager_base.h"
#include "../pr_l1_pr_l2_dram_directory_msi/dram_directory_cntlr.h"
#include "../pr_l1_pr_l2_dram_directory_msi/dram_cntlr.h"
#include "../pr_l1_pr_l2_dram_directory_msi/shmem_msg.h"
#include "semaphore.h"
#include <map>
Include dependency graph for memory_manager.h:
memory_manager.h
memory_manager_base.h cache_cntlr.h _directory_msi/dram _directory_msi/dram
setlock.h contention_model.h stats.h boost/tuple/tuple.hpp cache.h req_queue_list_template.h prefetcher.h address_home_lookup.h semaphore.h subsecond_time.h
mem_component.h shmem_perf_model.h fault_injection.h cache_set.h utils.h hash_map_set.h cache_perf_model.h core.h map queue vector
cache_block_info.h lock.h cstring random.h log.h
memory_manager.h
cache_cntlr.cc memory_manager.cc
Classes
class ParametricDramDirectoryMSI::MemoryManager
Namespaces
Typedefs
typedef std::pair< core_id_t, MemComponent::component_t > ParametricDramDirectoryMSI::Core-

ComponentType
typedef std::map< CoreComponentType, CacheCntlr > ParametricDramDirectoryMSI::CacheCntlrMap
7.40 nuca_cache.cc File Reference
#include "nuca_cache.h"
#include "memory_manager_base.h"
#include "stats.h"
#include "queue_model.h"
#include "shmem_perf.h"
Include dependency graph for nuca_cache.cc:
nuca_cache.cc
nuca_cache.h memory_manager_base.h config.hpp queue_model.h shmem_perf.h
hit_where.h cache_cntlr.h
prefetcher.h req_queue_list_template.h address_home_lookup.h semaphore.h setlock.h contention_model.h cache.h boost/tuple/tuple.hpp subsecond_time.h stats.h
vector queue map shmem_perf_model.h core.h cache_set.h hash_map_set.h cache_perf_model.h fault_injection.h utils.h mem_component.h pr_l1_cache_block_info.h
lock.h log.h random.h cstring cache_block_info.h
7.41 nuca_cache.h File Reference
#include "hit_where.h"
#include "boost/tuple/tuple.hpp"
Include dependency graph for nuca_cache.h:
nuca_cache.h
cache_cntlr.h hit_where.h
subsecond_time.h setlock.h contention_model.h req_queue_list_template.h stats.h cache.h prefetcher.h address_home_lookup.h semaphore.h boost/tuple/tuple.hpp
queue map core.h utils.h cache_set.h hash_map_set.h cache_perf_model.h fault_injection.h shmem_perf_model.h vector mem_component.h
log.h random.h cstring lock.h cache_block_info.h
7.42 pr_l1_cache_block_info.h File Reference 299
nuca_cache.h
memory_manager.cc nuca_cache.cc
Classes
class NucaCache
7.42 pr_l1_cache_block_info.h File Reference
Include dependency graph for pr_l1_cache_block_info.h:
cache_block_info.h
cache_atd.cc cache_block_info.cc nuca_cache.cc
Classes
class PrL1CacheBlockInfo
7.43 pr_l2_cache_block_info.cc File Reference
#include "log.h"
Include dependency graph for pr_l2_cache_block_info.cc:
pr_l2_cache_block_info.cc
pr_l2_cache_block_info.h log.h
7.44 pr_l2_cache_block_info.h File Reference 301
7.44 pr_l2_cache_block_info.h File Reference
Include dependency graph for pr_l2_cache_block_info.h:
cache_block_info.cc pr_l2_cache_block_info.cc
Classes
class PrL2CacheBlockInfo
7.45 prefetcher.cc File Reference
#include "log.h"
#include "simple_prefetcher.h"
#include "ghb_prefetcher.h"
Include dependency graph for prefetcher.cc:
prefetcher.cc
simulator.h config.hpp log.h simple_prefetcher.h ghb_prefetcher.h
prefetcher.h
7.46 prefetcher.h File Reference
#include <vector>
Include dependency graph for prefetcher.h:
prefetcher.h
7.47 req_queue_list_template.h File Reference 303
prefetcher.h
cache_cntlr.h ghb_prefetcher.h simple_prefetcher.h
memory_manager.h nuca_cache.h ghb_prefetcher.cc prefetcher.cc simple_prefetcher.cc
Classes
class Prefetcher
7.47 req_queue_list_template.h File Reference
#include <map>
#include <queue>
#include "log.h"
Include dependency graph for req_queue_list_template.h:
map queue log.h
cache_cntlr.h
Classes
class ReqQueueListTemplate< T_Req >
7.48 shared_cache_block_info.cc File Reference
#include "log.h"
7.49 shared_cache_block_info.h File Reference 305
Include dependency graph for shared_cache_block_info.cc:
shared_cache_block
_info.cc
shared_cache_block
log.h
_info.h
7.49 shared_cache_block_info.h File Reference
Include dependency graph for shared_cache_block_info.h:
shared_cache_block
_info.h
shared_cache_block
_info.h
shared_cache_block
cache_block_info.cc cache_cntlr.h
_info.cc
Classes
class SharedCacheBlockInfo
7.50 simple_prefetcher.cc File Reference 307
7.50 simple_prefetcher.cc File Reference
#include "simple_prefetcher.h"
#include <cstdlib>
Include dependency graph for simple_prefetcher.cc:
simple_prefetcher.cc
simple_prefetcher.h simulator.h config.hpp cstdlib
prefetcher.h
Variables
const IntPtr PAGE_SIZE = 4096

const IntPtr PAGE_MASK = (PAGE_SIZE-1)
7.50.1 Variable Documentation
7.50.1.1 PAGE_MASK
const IntPtr PAGE_MASK = (PAGE_SIZE-1)
7.50.1.2 PAGE_SIZE
const IntPtr PAGE_SIZE = 4096
7.51 simple_prefetcher.h File Reference
Include dependency graph for simple_prefetcher.h:
simple_prefetcher.h
prefetcher.h
simple_prefetcher.h
prefetcher.cc simple_prefetcher.cc
Classes
class SimplePrefetcher
7.52 tlb.cc File Reference
#include "tlb.h"
#include "stats.h"
7.53 tlb.h File Reference 309
Include dependency graph for tlb.cc:
tlb.cc
tlb.h stats.h
cache.h
cache_block_info.h random.h cstring lock.h log.h
Namespaces
7.53 tlb.h File Reference
#include "cache.h"
Include dependency graph for tlb.h:
tlb.h
cache.h
cache_block_info.h random.h cstring lock.h log.h
tlb.h
memory_manager.cc tlb.cc
Classes
class ParametricDramDirectoryMSI::TLB
Namespaces

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Sniper Multi-Core Simulator

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1.1 Namespace List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Class List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4.1 File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.1 ParametricDramDirectoryMSI Namespace Reference . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.2 Typedef Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1.3 Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.1 ATD Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.1.1 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1.2 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1.3 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Cache Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2.1 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2.2 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2.3 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3 CacheBase Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3.2 Member Enumeration Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3.3 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.4 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.4.5 splitAddress() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.3.4.6 splitAddress() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.3.5 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.4 CacheBlockInfo Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.4.1 Member Typedef Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.4.2 Member Enumeration Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.4.3 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.4.4 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.4.4.16 updateUsage() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.4.4.17 updateUsage() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.4.5 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5 CacheCntlr Class Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.5.1 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.6 ParametricDramDirectoryMSI::CacheCntlr Class Reference . . . . . . . . . . . . . . . . . . . . . 51

6.6.1 Constructor & Destructor Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.6.2 Member Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.6.2.15 getCacheState() [1/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.6.2.16 getCacheState() [2/2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.6.3 Friends And Related Function Documentation . . . . . . . . . . . . . . . . . . . . . . . . 96

6.6.4 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.6.4.27 m_last_remote_hit_where . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.28 m_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.29 m_mem_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.30 m_memory_manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.31 m_network_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.32 m_next_cache_cntlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.33 m_next_level_read_bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.6.4.34 m_passthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.35 m_perfect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.36 m_prefetch_on_prefetch_hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.37 m_shared_cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.38 m_shmem_perf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.39 m_shmem_perf_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.40 m_shmem_perf_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.41 m_shmem_perf_numrequests . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.6.4.42 m_shmem_perf_totaltime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.6.4.43 m_shmem_req_source_map . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.6.4.44 m_tag_directory_home_lookup . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.6.4.45 m_user_thread_sem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.6.4.46 m_writeback_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.6.4.47 mshr_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102