Counters

Special sequential circuits (FSMs) that sequence though a

set outputs.
Examples:
binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001,
EECS150 - Digital Design gray code counter:
Lecture 18 - Counters 000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110,
one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010,
BCD counter: 0000, 0001, 0010, , 1001, 0000, 0001
October 24, 2002 pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...
John Wawrzynek Moore machines with ring structure to STD:
S0
S3 S1
S2

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What are they used? Controller using Counters

Examples from this semester: Bit-serial multiplier:
Clock divider circuits shiftA
A register
16MHz 64 carry
shiftB
FA D-FF

B register shiftHI shiftLOW

reset
Network packet parser/filter control. sum
0
1
HI register LOW register

selectSum

Bit-serial multiplier control circuitry (from HW) Control Algorithm:

repeat n cycles { // outer (i) loop
repeat n cycles{ // inner (j) loop
In general: counters simplify controller design by
shiftA, selectSum, shiftHI
providing a specific number of cycles of action, }
shiftB, shiftHI, shiftLOW, reset
sometimes used in with a decoder to generate a sequence of control Note: The occurrence of a control
} signal x means x=1. The absence
signals. of x means x=0.

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 Controller using Counters Controller using Counters
State Transition Diagram: Controller circuit Outputs:
Assume presence of two implementation:
counters. An i counter for the
CEi = q2
outer loop and j counter for
inner loop. IDLE START CEj = q1
IDLE q0
CEi,CEj START RSTi = q0
START S R
RST i RSTj = q2
CLK RST
TCj
TC i INNER shiftA = q1
CE counter TC TC i
<inner contol> TCi
INNER q1
shiftB = q2
CEi,CEj S R
creset shiftLOW = q2
TC is asserted when the counter OUTER
reaches it maximum count value. <outer contol> shiftHI = q1 + q2
CEi,CEj TC j
CE is clock enable. The counter reset = q2
RSTj
increments its value on the rising q2 selectSUM = q1
TCj OUTER
edge of the clock if CE is asserted.
S R

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How do we design counters? Ripple counters

A3 A2 A 1 A0
For binary counters (most common case) incrementer circuit would 0000 Each stage is 2 of
work: previous.
1 0001
0010 Look at output
+ waveforms:
0011
register 0100 time
CLK
0101 A0
0110 A1
In Verilog, a counter is specified as: x = x+1; 0111 A2
This does not imply an adder 1000 A3
An incrementer is simpler than an adder 1001
And a counter is simpler yet. 1010 Often called
1011 asynchronous
In general, the best way to understand counter design is to think of 1100 counters.
them as FSMs, and follow general procedure. But before that ... 1101 A T flip-flop is a
1110 toggle flip-flop.
1111 Flips it state on
cycles when T=1.
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 Synchronous Counters Synchronous Counters
All outputs change with clock edge. How do we extend to n-bits?
a+ = a Extrapolate c+: d+ = d abc, e+ = e abcd
Binary Counter Design: c b a c + b+ a+ b+ = a b
Start with 3-bit version and 0 0 0 0 0 1
0 0 1 0 1 0 cb
generalize: 0 1 0 0 1 1 a 00 01 11 10 a+ b+ c+ d+
0 1 1 1 0 0 0 0 0 1 1
1 0 0 1 0 1 1 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1 a b c d
c+ = ac + abc + bc
1 1 1 0 0 0 = c(a+b) + c(ab) Has difficulty scaling (AND gate inputs grow with n)
= c(ab) + c(ab)
CE TC
= c ab
a+ b+ c+ d+
a+ b+ c+

a b c d

a b c
CE is count enable, allows external control of counting,
TC is terminal count, is asserted on highest value, allows
cascading, external sensing of occurrence of max value.
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Synchronous Counters Up-Down Counter

CE TC
a+ b+ c+ d+

a b c d
How does this one scale? Generation of TC signals very similar to
/ Delay grows n generation of carry signals in adder. c b a c + b+ a+
Parallel Prefix circuit reduces delay: 0 0 0 1 1 1
0 0 1 0 0 0
a b c d e f g h
0 1 0 0 0 1
0 1 1 0 1 0
1 0 0 0 1 1
1 0 1 1 0 0
log2n
1 1 0 1 0 1
1 1 1 1 1 0
Down-count

log2n

TC a TC b TC c TC c TC d TC e TC f TC g
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 Odd Counts Ring Counters
Extra combinational logic can be Alternative: one-hot counters What are these good for?
added to terminate count before 0001, 0010, 0100, 1000, 0001,
max value is reached: 4
q3 q2 q1 q0
Example: count to 12
load 4-bit binary TC
4-bit binary D Q D Q D Q D Q
reset counter S R S R S R S R
counter
reset 0 0 0 0

= 11 ?
Self-starting version:
q3 q2 q1 q0

D Q D Q D Q D Q

= 11 ?

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Ring Counters Johnson Counter

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 Register Summary Shift-registers
All registers (this semester) Parallel load shift register:
based on Flip-flops:
q3 q2 q1 q0

D Q D Q D Q D Q
S R S R S R S R

reset 0 0 0 0

d3 d2 d1 d0

Load-enable is a popular option:

q3 q2 q1 q0

D Q D Q D Q D Q
Parallel-to-serial converter
S R S R S R S R
Also, works as Serial-to-parallel converter, if q values are
reset 0 0 0 0
0 0 0 0
Xilinx flip-flops employ a clock connected out.
enable (CE) for same purpose.
1 1 1 1 Also get used as controllers (ala ring counters)
load

d3 d2 d1 d0
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Universal Sift-register

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