Вы находитесь на странице: 1из 4

CMOS Low Noise Amplifier Design

Optimization Technique
Trung-Kien Nguyen, Nam-Jin Oh, Hyung-Chul Choi, Kuk-Ju Ihm, and Sang-Gug Lee
Information and Communications University
119 Munjiro, Yuseong-gu, Daejeon, 305-714 South Korea
ntkienvn@icu.ac.kr

Abstract terminal of the cascode transistor to that of common


source transistor. The description of the methodology for
In this paper, a set up noise parameter expression and
LNA design optimization and the proposed LNA are
the third order intermodulation product expression (IM3)
discussed in detail in section 2 and 3, respectively. The
for a power-constrained simultaneous noise and input
proposed LNA for 5 GHz WLAN applications is
matching low noise amplifier design optimization
fabricated based on 0.18 Pm CMOS technology.
technique are introduced. Based on these expressions,
Measured results show 20 dB power gain, 1.5 dB NF and
the methodology to design LNA to archive the power-
5 dBm IIP3. The proposed LNA dissipates the DC
constrained simultaneous noise and input matching as
current of 3 mA at supply voltage of 2.5 V.
well as satisfy the linearization condition is explained. In
additional, the power gain is enhanced by using a very 2. Methodology for Low Noise Amplifier Design
simple positive feedback. The proposed LNA for 5GHz
A. Noise Optimization Analysis
WLAN applications is fabricated based on 0.18 Pm
CMOS technology. Measured results show 20 dB power Figure 1-a shows the schematic of a cascode LNA
gain, 1.5 dB NF and 5 dBm IIP3. The proposed LNA topology that is adopted to explain the PCSNIM LNA
dissipates DC current of 3 mA at supply voltage of 2.5 design technique. The LNA shown in Fig. 1-a differs by
V. one additional capacitor Cex in comparison with the
typical cascode LNA.
1. Introduction
With the recent proliferation of wireless transceiver id
Vbias
applications, there is an extensive effort to develop low M2
cost, highly integrated RF circuits. CMOS has become a Matching Circuit
competitive technology for radio transceiver
Lg
implementa-tion due to the technology scaling, higher M1
level of integrability, lower cost, etc. [1]. In typical
receiver architectures, a low noise amplifier (LNA) is the Zs' Cex
Rs
one of the most critical blocks that determines the vs Ls
sensitivity of wireless receiver systems [2-[4]. Normally, (a)
LNA design involves the tradeoff between noise figure
(NF), gain, linearity and power consumption. Lg Matching Circuit id
Consequently, the goal of LNA design is to achieve +
simultaneous noise and input matching at any given
Zs' vgs
amount of power dissipation as well as satisfy the Rs
Cex gg Cgs gmvgs
2 2
linearization conditions. The LNA design optimization ing ind
-
technique proposed in [4] can be applied for power- 2
vns
Zs Zin
constrained simultaneous noise and input matching. Ls
However, as discussed in [4], the fully potential of this (b)
technique is not provided clearly. This paper attempts to Fig. 1. Simple cascode LNA to adopt the PCSNIM technique
analyze and provide clear and perspe-ctive understanding (a) and its small-signal equivalent circuit (b)
one of the LNA design optimization techniques, namely This LNA topology was first introduced in [3] as a
power-constrained simultaneous noise and input solution to reduce the noise figure of the LNA at low
matching technique. The analyses are based on the noise power dissipation, however, the potential and the
parameter expressions and the expression for the third theoretical analysis as a power-constrained (i.e., low
order intermodulation product (IM3). By using those power) simultaneous noise and input matchable LNA
expressions, the design principle, advantages and topology has not been recognized. Fig. 1-b shows the
practical limitation for the mentioned LNA technique are simplified small-signal equivalent circuit of the cascode
explained. In additional, in this paper, the power gain of amplifier shown in Fig. 1-a for the noise analysis. In Fig.
the LNA is improved by using simple positive feedback 1-b, the effects of common-gate transistor M2 on the
technique. The simple positive feedback is implemented noise and frequency response are neglected [2]. The
by one additional capacitor connected from drain noise parameter expressions for a circuit with series
feedback, shown in Fig. 1-b, can be obtained by applying g m Ls
Re[Z s ] (9)
the Kickoffs law [1]. The results are simple enough to Ct
provide useful insights as shown below [5] 1
sLs   Im Z s (10)
sCt
2


1  s 2C L  L 1 | c | D G eff As mentioned above, for the advanced CMOS
t g s 5J

technology parameters, (8) is approximately equal to
J g
(10). Therefore, (10) can be dropped, which means that
1
d 0
(1)
2
F 1 2 2
Geff for the given value of Ls, the imaginary value of the
gm Rs  sCt Rs 1 | c | D

5J optimum noise impedance becomes approximately equal

DG to that of the input impedance with opposite sign. Now

5 m
 eff 1  c 2 g sC 2 R2  sL2
t s g

then, the design parameters that can satisfy (7)-(9) are
VGS, W (or Cgs), Ls, and Cex. Since there are three
2 Z equations and four unknowns, (7)-(9) can be solved for
Fmin 1  JG ( 1 | c |2 ) (2)
5 ZT an arbitrary value of Zs, by fixing the value of one of the
C design parameters that can be the power dissipation or
G G
D  j t D c VGS. In other word, this LNA design optimization
5J ( 1  c )
2 Cgs 5J
technique allows to design simultaneous noise and input
Zopt  sLs (3)
2
2
matching at any given amount of power dissipation.
DG C G
ZCgs  t D c
2 5J B Linearity Analysis
5J ( 1  c ) C gs
J 1 In RF circuit design, the linearity is another important
Rn (4) aspect to consider. Since LNA is the first block in the
D gm
typical receiver system, the linearity of the LNA is
where Ct = Cgs1+Cex
commonly estimated by the third order intermodulation
As can be seen from (2) and (4), Fmin and Rn are not
product. Two signals of adjacent channels AsinZ1 and
affected by the addition of Cex. In other word, by using
Cex, the minimum noise figure and the noise resistance AsinZ2 will generate products IM3 such as Asin(2Z1-Z2)
expressions for power-constrained simultaneous noise and Asin(2Z2-Z1) at the output of nonlinear circuit. IM3
and input matching technique are the same as those in usually calculated in the literature as the ratio of intermo-
[3]. From Fig. 1-(b), the input impedance of the LNA is dulation of the third order and the response magnitude of
given by the fundamental frequency which is given by
1 g L 3 2 A3 2Z1  Z2
Z in sLs   m s (5) IM 3 A (11)
sCt Ct 4 A1 Z
In (5), the source degeneration generates real part at where A1, A3 are the first order and third order coefficient
the input impedance. This is important because there is of Volterra series.
no real part in the input impedance without degeneration
Lg Matching Circuit gm2
while there is in the optimum noise impedance. id
Therefore, Ls helps to reduce the discrepancy between Zin
+
the real parts of the optimum noise impedance and the vgs
Zs' Cex Cgs Yo1
LNA input impedance. Furthermore, from (5), the Rs gm1vgs
vin
imaginary part of Zin is changed by sLs, and this is vs -
Zs
followed by nearly the same change in Zopt in (3),
Ls
especially with advanced technology considering the
value of c is higher than 0.4 (e.g., c | 0.5 with 0.25 Pm
Fig. 2 Circuit model for nonlinear analysis
technology), and D becomes lower than 1 [6].
Now, for the circuit shown in Fig. 1-(a), the conditions For linearity analysis purpose, the equivalent small
that allow the simultaneous noise and input matching are signal circuit of LNA in Fig. 1 is depicted in Fig. 2.
G Now, M2 can be considered and modeled by the series
D 2 trans-conductance gm2, assuming rds2 >> Rout. In this case,
5J ( 1  c )
Re[Z s ] (7) the effects of the Cgs2 and Cgd1 have been neglected. The
Ct
2
output admittance seen at the drain of M1, Yo1, is added in
D 2G G
ZC gs  D c the model with the purpose to identify the output
2 5J
5J ( 1  c ) C gs
contribution. Using the Kickoffs law in the model of
C G Fig. 6 the input signal can be written as
j t D c vin s vgs a1 s  id a2 s (12)
Cgs 5J
 sLs Im Z s (8)
2
Where a1 s sCt Z in  sLs  1 (13)
D 2G C G
ZC gs  t D c Y
5J ( 1  c ) C gs
2
5J a2 s sLs 1  o1 (14)

gm2
When the effective mobility reduction is taken into The qualitative description of the proposed design
account, the current between the source and drain process would be as follows. First, choose the DC bias,
terminals of the transistor M1 is given as VGS, for example the bias point that provides minimum

Wvsat Cox Vgs  Vt
2
Po Fmin. Second, choose the transistor size, W, based on the
I ds (15) power constraint, PD. Third, choose the additional
V  V
gs P t 1  2 Lvsat capacitance, Cex, as well as the degeneration inductance,
where P1 # Po  2 LvsatT and Vgs VGS  vgs Ls, to satisfy (7), (9), and s2CtLs = -1 conditions (as
Here, VGS is the DC bias voltage of the transistor, vgs is mentioned, to improve the linearity of circuit the
the small signal between gate and source, and vsat is the condition s2CtLs = -1 need to be satisfied). With the given
carrier velocity saturation. Using (12), the Volterra series Ls the condition Im[Zin*] = Im [Zopt] is automatically
expression of id is derived as satisfied. At this point, the simultaneous noise and input
matching is achieved. As the last step, if there exists any
id A1 s vin  A2 s1 ,s2 vin2  A3 s1 ,s2 ,s3 vin3 (16)
mismatch between Zin and Zs, as shown in Fig. 1 (b), an
Here the coefficients of order higher than three are impedance matching circuit can be added.
ignored. Usually, the adjacent channel frequencies Z1 This design optimization technique suggest that, by
and Z2 providing the intermodulation products are very using an additional capacitor, Cex, the LNA can be
close to the fundamental frequency Z therefore s | s1 | s2 designed to archive power-constrained simultaneous
can be assumed. The |IM3| at (2Z1 - Z2) is noise and input matching as well as satisfy the
A2 A1 s
3 linearization condition. The limitations of the PCSNIM
IM 3 a1 s 3 g3  2 g 22 B (17) technique are high Rn and low effective cut-off
2 g m3 1
frequency. High Rn can be a serious limitation for the
B 2'sLs 's a2 ' s A1 's  2sLs 2s a2 2s A1 2s (18) practical high yield LNA design.
g m1
A1 s (19) 3. Gain Enhancement Technique and Proposed LNA
a1 s  g m1a2 s
One of the simple ways to improve the power gain of
4 K P0 L2vsat
2
4 K P0 L2vsat
2
g2 3
, g3 4
(20) LNA is using positive feedback. In this paper, the

Vgs  Vt P1  2 Lvsat

Vgs  Vt P1  2 Lvsat
positive feedback is realized by Cf shown in Fig. 3-a.
This phenomenon can be understood by another point of
's s1  s2
view as the form of oscillator. In Fig. 3-a, Cgs1, Cf, and
where g2 and g3 are the second and third degree M2 constitutes an oscillator topology with inductive
coefficients of the transistor nonlinear Taylor expansion. termination at the output [1]. The effect of the positive
The B coefficient is the second-order interaction of the feedback will increase maximum available gain of the
products 2Z, Z1-Z2, and Z2-Z1. A1(s) is the transcon- cascode amplifier at high frequencies. Note that no
ductance of the circuit. Substituting (19) into (17), it additional active device is used therefore no more DC
shows the dependence of |IM3| with inverse of the term power is dissipated and no noise is contributed. The limit
3
Y to amount of feedback is governed by stability
sCt Rin  sLs g m1 1  o1 (21) consideration. To ensure the stability condition, Gtol must
g m 2
always positive. This technique is first introduced in [7];
As can be seen in (17), the linearity can be improved by however, the reported results are simulation-based only.
using different ways. Revising (17), the |IM3| can be This paper tries to realize this idea in term of measured
lowered with the reduction of a1(s), g3, or with the results. The simplified proposed LNA is shown in Fig. 3-
increase (21). As shown in (13), with inductive b. The proposed LNA is implemented by combining the
degeneration the s2CtLs term will cancel the 1 term, PCSNIM design technique described in previous section
and as a result a1(s) is reduced. This indicates that the and the gain enhancement technique shown in Fig. 3-a.
selected topology is more adequate to keep the |IM3| In the Fig. 3-b, the simple Lo-Co network represents the
small in comparison with resistive and capacitive output-matching network and Lo is implemented by off
degeneration topology, where such cancellation does not chip inductor.
exist. The joint effect of g3 and g2 coefficients in |IM3| is VDD VDD
inversely dependent on the bias (Vgs-Vt), indicating that
the linearity can be improved by increasing gate source Lo Co RFout Lo Co RFout
voltage. However, increasing the gate source voltage will
increase the power dissipation. With large Yo1 and gm1 Vbias Vbias
M1 M2
values and small gm2 value (21) is increased such that the Cf Cf
linearity will be increased. For the same reason, any
Cgs1 Lg
increase in Ct, preserving the matching condition in the M1
input circuit, also improves the linearity. i1 RFin Cex
C. Design Consideration Ls
In this section, the overall consideration for LNA (a) (b)
design to obtain power-constrained simultaneous noise Fig. 3 Gain enhancement technique and the proposed LNA
and input matching as well as linearization is described.
4. Measurement Results In this paper, a very simple and insightful set of noise
parameter expressions and the third order intermodu-
To demonstrate the potential of power-constrained
lation product for the power-constrained simultaneous
simultaneous noise and input matching optimization
technique and the gain enhancement technique, the noise and input matching LNA design optimization
current dissipation of the proposed LNA is fixed at 3 technique is newly introduced. Based on those expres-
mA. Three LNA versions are fabricated based on 0.18 sions, the design principle, advantage, and the limitation
Pm CMOS technology, the first circuit is simple cascode for the power-constrained simultaneous noise and input
inductive degeneration topology, the second one simple matched technique are explained. To demonstrate the
cascode with Cex and the third one is the proposed LNA potential of this design technique, the proposed LNA is
shown in Fig. 3. Note that, all the circuits are designed at designed and optimized for 5 GHz WLAN applications.
the same power dissipation. A Comparison of measured The measured results show good agreement with
NF results are shown in Fig. 4. As can be shown in Fig. theoretical analysis.
4, by using the power-constrained simultaneous noise 40
and input matching technique, the obtained NF is lower
than that for the case of simple cascode inductive 10 Fundamental
degeneration. The main reason of the improvement in NF

Output Power [dBm]


can be understood as the discrepancy between real parts
-20
of input and noise matching conditions
3.5 -50

3 IM3
-80
Noise Figure [dB]

2.5
With Cex
Without Cex -110
2 -40 -30 -20 -10 0 10
Input Power [dBm]
1.5
Fig. 6 IIP3 of the proposed folded cascode LNA
1

0.5
4 4.5 5 5.5 6 6.5
Freq [GHz] (a) (b)
Fig. 4 Measured NF of LNAs
(c)
25

20
Power Gain [dB]

15
Fig. 7 Microphotograph of the three LNA: (a) simple cascode,
(b) simple cascode includes Cex, and (c) proposed LNA
10
With Cf
Without Cf References
5
[1] B. Razavi, CMOS technology characterization for analog and RF
design, IEEE Journal of Solid- State Circuits, Vol. 34, pp. 268-276,
0 March 1999.
[2] S. P. Voinigescu et al., A Scalable High-Frequency Noise Model for
4 4.5 5 5.5 6 6.5 Bipolar Transistors with Application Optimal Transistor Sizing for
Freq [GHz] Low-Noise Amplifier Design, IEEE J. Solid- state Circuits, Vol. 32,
pp 1430-1439, Sep 1997.
Fig. 5 Measured power gain of LNAs [3] D. K. Shaeffer et al., A 1.5V, 1.5 GHz CMOS Low Noise Amplifier,
IEEE Journal of Solid-Stage Circuits, Vol. 32, pp 745-758, May 1997.
Fig. 5 shows the measured results comparison of two [4] G. Girlando et al., Noise Figure and Impedance matching in RF
LNAs simple cascode and proposed LNA shown in Fig. Cascode Amplifiers, IEEE Transaction on Circuits and Systems-II,
3-b. As can be seen from Fig. 5, the power gain is Vol. 46, pp. 1388-1396, Nov. 1999.
[5] Trung-Kien Nguyen, et al., CMOS Low Noise Amplifier Design
improved by 3 dB compare to that of simple cascode Optimization Techniques, Accepted to be published on IEEE
topology. Fig. 6 shows the measured result of input third Transactions on Microwave Theory and Technique, May 2004.
order intermodulation product of the proposed LNA. The [6] G. Knoblinger et al., A New Model for Thermal Channel Noise of
Deep-Submiron MOSFET and its Applications in RF-IC Design,
proposed LNA has power gain of 20 dB, NF of 1.5 dB at IEEE Journal of Solid- State Circuits, Vol. 36, pp. 831-837, May
5.25 GHz and IIP3 of 5 dBm. The microphotograph of 2001.
the three circuits is shown in Fig. 7. [7] K. L. Chan, et al., 1.5 V 1.8 GHz Bandpass Amplifier, IEE
Symposium of Circuits Devices and Systems pp. 331-333, Dec. 2000.
5. Conclusion