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OPA2604
SBOS006A SEPTEMBER 2000 REVISED DECEMBER 2015
Simplified Schematic
(8)
V+
(+)
(3, 5)
()
Distortion
(2, 6) Output (1, 7)
Rejection
Stage* VO
Circuitry*
(4)
V
* Patents Granted:
#5053718, 5019789
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2604
SBOS006A SEPTEMBER 2000 REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 14
2 Applications ........................................................... 1 8.1 Application Information............................................ 14
3 Description ............................................................. 1 8.2 Typical Applications ................................................ 14
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 20
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 20
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 20
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 21
6.2 ESD Ratings ............................................................ 4 10.3 Power Dissipation ................................................. 21
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 22
6.4 Thermal Information .................................................. 4 11.1 Device Support .................................................... 22
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ....................................... 22
6.6 Typical Characteristics .............................................. 6 11.3 Community Resources.......................................... 23
7 Detailed Description ............................................ 10 11.4 Trademarks ........................................................... 23
7.1 Overview ................................................................. 10 11.5 Electrostatic Discharge Caution ............................ 23
7.2 Functional Block Diagram ....................................... 10 11.6 Glossary ................................................................ 23
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 13 Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
P and D Packages
8-Pin PDIP and SOIC
Top View
Output A 1 8 V+
In A 2 7 Output B
+In A 3 6 In B
V 4 5 +In B
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 Output A O Output channel A
2 In A I Inverting input channel A
3 +In A I Noninverting input channel A
4 V I Negative power supply
5 +In B I Noninverting input channel B
6 In B I Inverting input channel B
7 Output B O Output channel B
8 V+ I Positive power supply
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Power supply voltage 25 V
Input voltage (V)1 (V+)+1 V
Output short-circuit to ground Continuous
Operating temperature 40 100 C
Junction temperature 150 C
Lead temperature (soldering, 10 s) AP 300 C
Lead temperature (soldering, 3 s) AU 260 C
Tstg Storage temperature 40 125 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
1 0.1
Measurement BW = 80kHz See Distortion Measurements
See Distortion Measure- for description of test method.
VO = ments for description of VO
3.5Vrms
0.1 1k test method.
1kW
0.01
THD + N (%)
THD + N (%)
f = 1kHz
G = 100V/V
0.01 Measurement BW = 80kHz
G = 10V/V 0.001
0.001
G = 1V/V
0.0001 0.0001
20 100 1k 10k 20k 0.1 1 10 100
Frequency (Hz) Output Voltage (Vp-p)
Figure 1. Total Harmonic Distortion + Noise vs Frequency Figure 2. Total Harmonic Distortion + Noise
vs Output Voltage
120 0 1k 1k
100
45
Voltage Noise (nV/ Hz)
40
G 135 10 10
20
0 180
Current Noise
20 1 1
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)
Figure 3. Open-Loop Gain and Phase vs Frequency Figure 4. Input Voltage and Current Noise Spectral Density
vs Frequency
100nA 10nA 10nA 1nA
100 10
Input 100 10
Offset Current
10 1
Input
Offset Current
1 0.1 10 1
75 50 25 0 25 50 75 100 125 15 10 5 0 5 10 15
Ambient Temperature (C) Common-Mode Voltage (V)
Figure 5. Input Bias and Input Offset Current vs Figure 6. Input Bias and Input Offset Current
Temperature vs Input Common-Mode Voltage
VS = 24VDC
110
VS = 15VDC
100
100
10 VS = 5VDC
90
1 80
0 1 2 3 4 5 15 10 5 0 5 10 15
Time After Power Turn-On (min) Common-Mode Voltage (V)
Figure 7. Input Bias Current vs Time from Power Turnon Figure 8. Common-Mode Rejection vs Common-Mode
Voltage
120 120
CMR
100
110
CMR
AOL, PSR, CMR (dB)
PSR, CMR (dB)
80
100
PSR +PSR
60
AOL
90
40
80
20
PSR
0 70
10 100 1k 10k 100k 1M 10M 5 10 15 20 25
Frequency (Hz) Supply Voltage (V S)
Figure 9. Power Supply and Common-Mode Rejection Figure 10. AOL, PSR, and CMR vs Supply Voltage
vs Frequency
28 33 28 30
Slew Rate
Gain-Bandwidth (MHz)
Gain-Bandwidth (MHz)
24 29 24 25
Gain-Bandwidth Slew Rate
Slew Rate (V/s)
20 25 20 20
Gain-Bandwidth
G = +100
16 21 16 15
12 17 12 10
5 10 15 20 25 75 50 25 0 25 50 75 100 125
Supply Voltage (V S) Temperature (C)
Figure 11. Gain-Bandwidth and Slew Rate Figure 12. Gain-Bandwidth and Slew Rate vs Temperature
vs Supply Voltage
3 RL = 1k
0.01% 120
2
0.1% VO =
100 A
20Vp-p B
1
RL Measured
Output
0 80
1 10 100 1000 10 100 1k 10k 100k
Closed-Loop Gain (V/V) Frequency (Hz)
Figure 13. Settling Time vs Closed-Loop Gain Figure 14. Channel Separation vs Frequency
30 14
VS = 15VDC
Output Voltage (Vp-p)
12
10
VS = 5VDC
10
8
0 6
10k 100k 1M 10M 75 50 25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (C)
Figure 15. Maximum Output Voltage Swing vs Frequency Figure 16. Supply Current vs Temperature
+100
Output Voltage (mV)
+10
Output Voltage (V)
FPO
Bleed to edge
10 100
0 5 10 0 1ms ms 2
Time (s) Time (s)
Figure 17. Large-Signal Transient Response Figure 18. Small-Signal Transient Response
Figure 19. Short Circuit Current vs Temperature Figure 20. Power Dissipation vs Supply Voltage
1.4
qJ-A = 90C/W
1.2 Soldered to
Total Power Dissipation (W)
Circuit Board
1.0 (see text)
0.8
0.6
Maximum
0.4 Specified Operating
Temperature
0.2 85C
0
0 25 50 75 100 125 150
Ambient Temperature (C)
7 Detailed Description
7.1 Overview
The OPA2604 is a dual, FET-input operational amplifier designed for enhanced AC performance. Low distortion,
low noise, and wide bandwidth provide superior performance in high quality audio and other applications
requiring dynamic performance.
(8)
V+
(+)
(3, 5)
()
Distortion
(2, 6) Output (1, 7)
Rejection
Stage* VO
Circuitry*
(4)
V
* Patents Granted:
#5053718, 5019789
R1 R2
SIG. DIST.
GAIN GAIN R1 R2 R3
1
2 1 101 5k 50
R3 VO = 10Vp-p
OPA2604 10 101 500 5k 500
(3.5Vrms)
100 101 50 5k
Generator Analyzer
Output Input
* Measurement BW = 80kHz
Validity of this technique can be verified by duplicating measurements at high gain or high frequency, where the
distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with the Audio Precision System One, which simplifies such repetitive measurements. The measurement
technique can, however, be performed with manual distortion measurement instruments.
(a) (b)
CC
820pF 1
2
OPA2604 eo
1 RC
2
OPA2604 eo
ei 750 CC CL
0.47F 5000pF
CL
5000pF R2 RC
CC = 120 X 1012 CL ei
2k 10
R2
RC =
4CL X 1010 1
CL X 103
CC =
RC
(c) (d)
R1 R2 R1 R2
10k 10k 2k 2k
CC
RC
20
24pF
CC
1 RC 1
2 0.22F 2
OPA2604 eo OPA2604 eo
ei 25 ei
CL CL
50 5000pF R2 5000pF
CC = CL RC =
R2 2CL X 1010 (1 + R2/R1)
C L X 103
CC =
RC
(e) (f)
R2 R1 R2
e1
2k 2k 2k
R1
RC
ei 1
2 20 1
2
2k eo eo
OPA2604 OPA2604
CC
RC 0.22F
20 CL CL
5000pF 5000pF
CC R3 R4
0.22F e2
R2 2k 2k
RC =
2CL X 1010 (1 + R2/R1) R2
RC =
2C L X 1010 (1 + R2/R1)
CL X 103
CC =
RC C L X 103
CC =
RC
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
R4 C5
2.94 k 1 nF
R1 R3 Output
590 499 +
Input OPA2604
C2
39 nF
Gain (db)
-20
-40
-60
100 1k 10k 100k 1M
Frequency (Hz)
3.92 k 1.33 k Output
+
OPA627
3.92 k 1000 pF
+
Input
3.92 k
OPA2604
+
+
OPA2604 1000 pF
3.48 k
1000 pF
I-Out DAC R1
C2
2k 2200pF 1
2
1 R2 R3 OPA2604 VO
2
COUT OPA2604
2.94k 21k
C3 Low-pass
470pF 2-pole Butterworth
~ COUT f3dB = 20kHz
* C1 =
2p R1 fc
R1 = Feedback resistance = 2k
fc = Crossover frequency = 8MHz
1 10k 10k
2
7.87k OPA2604
1
2
VIN 100pF OPA2604 VO
G=1
+
1
2
7.87k OPA2604
100kHz Input Filter 10k 10k
G = 101
1 (40dB)
2
OPA2604
Piezoelectric
Transducer
1M*
10
5 C1*
PCM63
20-bit 6
1
D/A 2
9 OPA2604 VO = 3Vp
Converter
To low-pass
filter.
8.2.7 Using the Dual OPA2604 Op Amp to Double the Output Current to a Load
1/2 OPA2604
A2
I2
R4
1/2 OPA2604
R3 51
51
A1 IL = I1 + I2
i1
VIN R2
VOUT Load
R1
VOUT = VIN (1 + R2/R1)
Figure 31. Using the Dual OPA2604 Op Amp to Double the Output Current to a Load
22k
C3
R1 R2 R3 100pF
VIN 1
2
2.7k 22k 10k OPA2604 VO
C1 C2
3000pF 2000pF
fp = 20kHz
10 Layout
VIN A + VIN B +
RG VOUT A RG VOUT B
RF RF
(Schematic Representation)
Output A V+ GND
RF Output B
GND -In A Output B
RG RF
VIN A +In A -In B GND
RG
V +In B VIN B
NOTE
These files require that either the TINA software (from DesignSoft) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 9-Apr-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA2604AP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type OPA2604AP
& no Sb/Br)
OPA2604APG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type OPA2604AP
& no Sb/Br)
OPA2604AU ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2604AU
OPA2604AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2604AU
OPA2604AU/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2604AU
OPA2604AUE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2604AU
OPA2604AUG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2604AU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 9-Apr-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Automotive: OPA2604-Q1
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
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