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IN HARVARD ARCHITECTURE
CYCLE 1 : COMPLETE THE PREVIOUS INSTRUCTIONS AND READ THE PRESENT
INSTRUCTION.
CYCLE 2 : EXECUTE , READ DATA MEMORY AND STORE IN ACCUMULATOR. READ
NEXT INSTRUCTION.
31 X 32-BIT REGISTERS
5 STAGE PIPE-LINING
FETCH
THE PROCESSOR READS THE INSTRUCTION FROM INSTRUCTION MEMORY.
DECODE
THE PROCESSOR READS THE SOURCE OPERANDS FROM THE REGISTER
FILE AND DECODES THE INSTRUCTION TO PRODUCE THE CONTROL SIGNALS.
EXECUTE
THE PROCESSOR PERFORMS A COMPUTATION WITH THE ALU.
MEMORY
THE PROCESSOR READS OR WRITES DATA MEMORY.
WRITE
THE PROCESSOR WRITES THE RESULT TO THE REGISTER FILE, WHEN
APPLICABLE.
FLEXIBLE CACHE DESIGN
HARVARD CACHE ARCHITECTURE
SIZES CAN BE 4 KB TO 128 KB INCREASING IN POWERS OF 2
I & D CACHES CAN HAVE INDEPENDENT SIZES
LINE LENGTH FIXED AT 8 WORDS
FIXED 4 WAY SET ASSOCIATION
ZERO WAIT STATE ACCESSES
CRITICAL WORD FIRST CACHE LINE FILL
NON BLOCKING
ADVANTAGES OF ARM 9
IEC2015088 IMM2015008
IEC2015089 IBM2015001
IMM2015002 IBM2015002
IMM2015006
PREPARED BY
IEC2015086 IMM2015001
QUESTIONS ARE WELCOMED