THE UNIVERSITY OF DANANG

DANANG UNIVERSITY OF TECHNOLOGY

Center Of Excellence
http://www.ece.dut.edu.vn

THE FINAL EXAM - ECE271

(Closed textbook; Duration: 120 minutes)

1. (40)
2. (30) THIEN has designed an entertainment system and now wants to incorporate a fault
warning system. Since the system is able to provide audio and video signals to a number of
locations, its important to be able to indicate a fault to any of those locations as well.

As a first step, the maximum number of remote locations to

which the annunciation information can be sent must be
determined. At each remote location, the signal is buffered
or isolated using an SN 74LS04 inverter as shown in the
accompanying logic diagram. When the output of the driver
gate SN 74LS241 is a logical 0, the warning LED is
illuminated and current flows as shown by the arrow in the
figure. When the output of the driver gate is a logical 1, the
warning LED is off only a small current flows through the
LED in the same direction.
Please determine the maximum number of SN 74LS04 gates, N, that can be driven if
the driver, buffer, and LED have the following characteristics.
SN 74LS04 IIL = -400 A,
IIH = 20 A
SN 74LS241 IOL = 24 mA for VOL = 0.2V
IOH = -15 mA for VOH = 3.5V
LED current ON = 10 mA
OFF = 50 A

3. (30 points) You've just been hired by the Really Fast Design Company to replace an
engineer who designed the following circuit. This circuit is intended to provide an output
signal on QC with a frequency of 500 KHz. However, the signal QC had a frequency of 1
MHz instead. The flip flops have the following characteristics: dHL = 20ns, dLH = 10ns
where dHL and dLH are the high to low and low to high propagation delays respectively.

QC

Vcc
SET
J Q
C

SET SET
K CLR
Q
D Q J Q
c lo c k
A B
4 M Hz Q K Q
CLR CLR

a. Can you explain why? Please use a timing diagram as necessary for illustration.
b. How would you modify the design to work properly?