Objectives

Processor and Describe structural units of a processor.

p
Memory Organization Explain various types of memory devices and
their uses.
Asst. Prof. Suree Pumrin, Ph.D. Explain concept of memory map.
Semester
Se este 1/2553
/ 553
Select
S l t ththe appropriate
i t processor, microcontroller,
i t ll
or DSP.
Organize the chosen processor, memories, and
interfacing circuit.
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Topics Structural Units in a Processor (1)

Structure units of processor
Memory
M blocks
bl k ffor th
the d
data-structures
t t t and
d data
d t
set elements
Concept of memory map
g
Device registers and addresses of I/O devices
Direct memory access
Memories and I/O devices interface circuit

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 Structural Units in a Processor (2)
1) Internal and external buses interconnect the processor
internal units with system memories, I/O devices and
all o
a other
e sys
system
e e elements
e e s
2) Address, data and control buses
3) MDR (memory data register) holds the accessed byte
or wordd
4) MAR (memory address register) holds the address
5) BIU (Bus Interface Unit)
6) Program Counter or Instruction Pointer and Stack
Pointer

Figure 2.1 Block Diagram of structural units at a processor

in an embedded system.
system
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Structural Units in a Processor (3) Structural Units in a Processor (4)

7) ARS (Application Register Set): Set of on-chip 12) Instruction, Data and Branch Target Caches and
registers for use in the application program. associated PFCU (Prefetch control unit) for pre-
8) Register window-
window a subset of registers with each fetching the instructions
instructions, data and next branch target
subset storing static variables and status words of a instructions, respectively.
routine.
9) Changing windows helps in fast context-switching in a 13) AOU (Atomic Operations Unit ) An instruction is broken
program. into number of processor-instructions called atomic
10) ALU and FLPU (Arithmetic and Logic operations Unit p
operations ((AOs),), AOU finishes the AOs before an
and Floating Points operations Unit). FLPU associates interrupt of the process occurs - Prevents problems
a FLP register set for operations. arising out of incomplete processor-operations on the
11) Register set is also called file and associates ALU or shared
h dd data
t iin th
the programs
FLPU.

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 Structural Units in a Processor (5) Processor Performance
14) Advanced Processing units (i) MAC, bit reversal and
shifter units, VLIW processing unit in a DSP, (ii) Units
1) MIPS Million Instructions Per Second
for multistage pipeline processing,
processing multi
multi-line
line 2) MFLOPS Million Floating Point
superscalar processing to boost the processing Operations Per Second
speeds much higher than one instruction per clock
cycle. 3) Dhrystone/s
Dh t / Number
N b off titimes a
benchmark program called Dhrystone
program can run per second.[1MIPS
d [1MIPS =
1757 Dhrystone/s

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Processor Selection Processor Selection

in Embedded System (1) in Embedded System (2)
9) On-chip DMA controller
1) Instruction Cycle Time 10) Interrupt System
2) Processing Performance per sec per W 11) Advanced Processing Units
3) Internal Bus Width 12) Harvard or Princeton Architectures for
4) Caches and multi-way caches memory organization
i ti
5) On-chip RAM and ROM 13) RISC or CISC or RISC core with CISC like
6) Interrupt System instruction set
7) Requirement of Floating Point instructions 14) On-chip compiler
8) Requirement of Bit Manipulations instruction 15) AOs feasibility
needs 16) IO Mapped IO space like 80x86 or Memory
mapped IOs
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 Real-Time Control of a Robot
Motor needs signal at the rate of 50 to
100 ms only.y Program
g size is also
limited. Low MIPS performance
Processor Selection Examples: suffices. Therefore,, Microcontroller
8051, 68HC11, 68HC12 are the best
choice.
[Refer Example 2.2 pp. 63 for details]

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Voice Data Compression N t

Network
kSSwitching
it hi S System
t

Voice signals are 64kbps. High MIPS Transfer rates of 100 Mbps from a switch
performance needed. On-chip
p p memory y are needed.
needed RISC architecture for high
does not suffice for the resulting data. MIPS needed. Exemplary processors
Therefore,, an exemplary
p yp processor needed are Power PC or ARM7.
ARM7
needed is 80x86 or a DSP
[Refer Example 2.4 pp. 64 for details]
[Refer Example 2.3
2 3 pp.
pp 63-64 for details]

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 Real Time Video Processing Software Concept
- Needs fast frame compression
- Use of a DSP with advanced Processing
units MACs needed.
- Multiprocessor system having TMS
DSP, SHARC, TigerSHARC, ARM9 or
PowerPC processors needed. [Refer
Example 2.5
2 5 pp.
pp 64 for details]

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Memory of a Computer System

Von Neumann Architecture

Memory Selection Examples

Harvard Architecture

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 A t
Automatic
ti Washing
W hi M Machine
hi Data Acquisition System
S
Needs
N d mass manufacturing
f t i th therefore
f
masked ROM, needs EEPROM for Data acquired to be stored at the flash
current machine status, RAM for (for example 128 kB) ; Needs about 8
y, A
variables and stack only, kB ROM or EPROM for program
Microcontroller on-chip 256 byte RAM, memory, 512 B RAM
4 kB ROM and 128 byte EEPROM [Refer Example 2.7a pp. 70 for details]
suffice [Refer Example 2.6a pp. 69 for
details]

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Set-top Box System Di it l camera

Digital

Large ROM as well as large RAM, 16kB 1024 color camera images need 64 kB
EEPROM for phone and messages ROM 32 MB flash
ROM, flash, and 1 MB RAM.
RAM
memory - Camera with 1 GB memory stick can
record
d iimage andd sounddbboth
h ffor
several minutes.

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 Functions, Processes
Functions Processes, Data and
Stacks of Memoryy

Memory Allocation To Program Segment wise memory allocation in four

Segments and Blocks segments; Code, Data, Stack and Extra
(for examples,
examples image
image, String)

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Segments and Paging at the Differentt Data

Diff D t Structures
St t att the
th
Memory Memoryy Blocks (1)
( )
1)) Stacks Return addresses on the
nested calls, Sets of LIFO (Last In First
Out)) retrievable data,, Saved Contexts of
the tasks as the stacks

Figure 2.2 (a) The segment types and pages in an exemplary

program

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 Differentt Data
Diff D t Structures
St t att the
th
Memoryy Blocks (2)
( )
2) Arrays One dimensional or
multidimensional
l idi i l
3) Queues Sets of FIFO (First In First
Out) retrievable data; Circular Queue
Figure 2.3 An example of
(Example a Printer Buffer); Block
(Example-
different stack structures at the Queue (Example- a network stack)
memory blocks.

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Differentt Data
Diff D t Structures
St t att the
th
Memoryy Blocks (3)
( )
4) Table
5) Look up Table Look-up-table
Look up table row
Figure 2.4 An array at first column points to another memory
a memory block.
block block of a data structure data
6) List: In a list element, a data structure
off an item
it also
l points
i t tto the
th nextt item
it
7)) Process Control Block [[Refer Chapter p
8]

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 Memory Map

Map to show the program and data

allocation of the addresses to ROM, RAM,
EEPROM or Fl Flash
h iin th
the system
t

Figure 2.5
2 5 Four memory allocation maps
maps.
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D i Add
Device Addresses M
Map P t d I/O vs Memory
Ported M Mapped
M d I/O

Device control and status addresses

and port address remains constant
and are not re-locatable in a program
as the glue circuit (hardware) to
accesses these is fixed during the
circuit
i it d design.
i

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 M
Memory Mapped
M d I/O P t d I/O
Ported
In memory mapped I/O, for example, in In I/O mapped I/O (Ported I/O), for example,
8051 microcontroller, the devices have in 80x86 processor, the devices have the
the addresses for processor-accesses addresses for processor-accesses that
that are not distinct from the memory are distinct from the memory and are
and are accessed with same set of accessed by distinct set of instructions
instructions [R f Example
[Refer E l 2.16
2 16 for
f a Serial
S i l Li
Line
Device on pp. 87-88]

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DMA (Di
(Directt M
Memory A
Access)) Interfacing the processor
processor, memory
memory,
Controller and devices

External Devices can directlyy write and read The p

processor,, memory y and devices are
into the blocks of RAM using the DMA interfaced (glued) together using a
controller when the buses are not in use
controller, programmable
p g circuit like GAL or FPGA.
of the processor The circuit consists of the address
decoders
decode s as pe
per the
e memory
e oya andd de
device
ce
addresses allocated and the needed
latches multiplexers/ demultiplexers

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 Exercise
1. What are the common structure units in most
processors?
2. What are the special structural units in processors for
digital camera systems, real-time
real time video processing
systems, speech compression systems, voice
compression systems, and video games?
3. What do you mean by device registers and device
address?

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