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VIGNAN UNIVERSITY

Minor - D. Electronics & Communication Engg. L T P To C


3 1 - 4 4

EC302 DIGITAL SIGNAL PROCESSING

Objective of the Course :


The objective of the course is to Introduce the student the concepts and
methods, which are used in digital signal processing. Students will learn
algorithms used in digital signal processing, which can be implemented in
laboratory by Matlab.

UNIT - I
Introduction: Review of Signals and Systems, linear shift invariant systems,
stability, and causality. Linear constant coefficient difference equations. Frequency
domain representation of discrete time signals and systems, Review of Z-
Transform and properties, Discrete fourier representation of periodic sequences.

UNIT - II
Discrete Fourier Transform: Discrete Fourier transforms, Properties of DFT,
linear convolution of sequences using DFT, Computation of DFT.
Fast Fourier Transform: Fast Fourier transforms (FFT) - Radix-2 decimation in
time and decimation in frequency FFT Algorithms, Inverse FFT, Radix-4, Split
Radix FFT algorithms, Overlap and add methods.

UNIT - III
IIR & FIR Filter Design: IIR System Function, Analog filter approximations
Butter worth and Chebyshev, Design of IIR Digital filters from analog filters,
Analog-to- Digital transformations. FIR System function, Characteristics of FIR
Digital Filters, frequency response. Design of FIR Digital Filters using Window
Techniques, Frequency Sampling technique, Comparison of IIR & FIR filters.

UNIT - IV
Realization of Filters: Basic structure of IIR & FIR, Structures for FIR Systems,
Direct form structure, cascade form structure, frequency sampling structure,
structures for FIR systems, Direct form structure, signal flow graphs and
transposed structures, cascade form structures, parallel form structures, Lattice
and Lattice Ladder structures.

UNIT - V
Introduction to DSP Processors: Introduction to programmable DSPs:
Multiplier and Multiplier Accumulator (MAC), Modified Bus Structures and Memory

Computer Science and Engineering 152


VIGNAN UNIVERSITY

Access schemes in DSPs Multiple access memory, multiport memory, VLIW


Architecture, Pipelining, Special addressing modes, On-Chip Peripherals.
Architecture of TMS 320C6X- Introduction, Bus Structure, Central Arithmetic
Logic Unit, Auxiliary Registrar, Index Registrar, Auxiliary Registger Compare
Register, Block Move Address Register, Parallel Logic Unit,Memory mapped
registers, program controller, Some flags in the status registers, On- chip reg-
isters, On-chip peripherals

TEXT BOOKS :
1. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing,
Principles, Algorithms and Applications, Pearson Education / PHI, 2007.
2. A.V.Oppenheim and R.W. Schaffer, Discrete Time Signal Processing,
PHI, 1997.
3. Avtar Singh and S. Srinivasan, Digital Signal Processing, Thomson
Publications, 2004.
4. B.Venkataramani, M.Bhaskar, Digital Signal Processors Architecture,
Programming and Applications, Tata McGraw Hill, 2002.

REFERENCE BOOKS :
1. Ramesh Babu, Digital Signal Processing, Scitech, 2003.
2. M H Hayes, Digital Signal Processing : Schaums Outlines, TATA
McGraw Hill, 2007.
3. Alan V. Oppenheim, Ronald W. Schafer, Digital Signal Processing,
PHI, 2006.
4. Salivahanan, Vallavaraj, Gnanapriya, Digital Signal processing, TMH,
2000.

Computer Science and Engineering 153