IEEE-ICSE2014 Proc.
2014, Kuala Lumpur, Malaysia
Memristor To Control Delay Of Delay Element
Siti Musliha Ajmal Binti Mokhtar
Faculty of Electrical Engineering
Universiti Teknologi MARA (UiTM)
Selangor, Malaysia
Abstract In this work, a SPICE memristor model is
combined with CMOS element in order to use the memristor
resistance to regulate delay of a current starved inverter. Since
memristor resistance changes according to supply voltage, the
changes of memristor resistance have been studied and
demonstrated using a memristor spice model. A pulse signal is
supplied to the memristor to control the resistance of the
memristor where the resistance changes according to the pulse
width. Due to changes of resistance the current also changes and
regulates the delay of delay element. The proposed SPICE model
and CMOS combination is important for other memristor
application studies.
Keywords memristor; memristor spice model; memristor
application; memristor resistance
I. INTRODUCTION
The theory of memristor is originally reported by Leon
Chua in 1971 [1-2]. However, memristor remains as theory
only until the first physical memristor model is realized by
Stan William and his group from HP lab [3-4]. The team has
built a nanoscale TiO2 device that share one common point
with memristor, it also exhibits pinched hysteresis loop.
William also explains about memristor switching mechanism
in the paper. Since the memristor physical model discovery,
researchers have been trying to understand the new device and
develop its potential applications.
Memristor is used as non-volatile memory device in work
[5-6] with high density and speed as fast as DRAM.
Memristor switching ability is applied in logic circuit [7]
where the resistance is represented as logical states. In
nueromorphic system, memristor mimics the role of synapses,
where each device may interact with other devices throughout
the system [8]. Several programmable analog circuits
demonstrating memristor based programming of threshold,
gain, and frequency are proposed in work [9]. Another
example of memristor-based programmable resistance is
reported in work [10].
However, despite such various memristor applications,
memristor is not yet available in current market due to the cost
and technical difficulties in fabrication nanoscale device. Few
papers [11-13] have proposed SPICE macro model to analyze
the behavior of memristor. Although these spice models are
accurate and the parameters are changeable, they are only
intended to exhibit memristor behavior and not applicable for
memristor application. In order to study various applications
978-1-4799-5760-6/14/$31.00 2014 IEEE
Wan Fazlida Hanim Abdullah
Faculty of Electrical Engineering
Universiti Teknologi Mara (UiTM)
Selangor, Malaysia
of memristor, emulators of memristor have to be developed
such in work [9, 14-16]. Most memristor emulator circuits are
built using CMOS elements and only take the importance of
exhibiting pinch off behavior of the memristor. However,
since memristor emulators use CMOS elements, they are
process dependent and only exhibit memristor pinched off
behavior that comparable to memristor found by HP lab. It is
hard to adjust the behavior of memristor for any other
fabricated memristor behavior.
In this work, a SPICE memristor model is used to exhibit
memristor behavior and combined with CMOS element in
order to use the behavior for memristor application. Since
memristor resistance changes according to supply voltage, the
resistance of memristor is used to regulate the delay of a delay
element. The idea to control memristor resistance is using
pulse signal that increases the resistance according to pulse
width. The current from memristor is copied to current mirrors
using an opamp and resistor. A capacitor stores charge in
order to keep the resistance information when voltage supply
is zero. The voltage from capacitor, Vc is converted into
control current, Ic. The control current, Ic then regulates the
delay of the delay element.
This paper is divided into 5 sessions including the
introduction and conclusion. Session 2 briefly explains on the
study of memristor variable resistance that is demonstrated
using a memristor spice model. Next, session 3 explains on
memristor spice model combined with CMOS element to for
memristor application. Session 4 describes on memristor to
control the delay of delay element that consists of a current
starved inverter.
II. MEMRISTOR SPICE MODEL AND VARIABLE RESISTANCE
One of distinguished memristor feature is the ability to
change its resistance when voltage/current is supplied to the
memristor. In this session, the resistance of memristor is
studied using memristor spice model. To demonstrate
memristor SPICE model behaviour, a SPICE model of
memristor is adopted from [12].
A. Resistance of Memristor Spice Model
First, the memristor spice model is simulated to get the
current-voltage (I-V) characteristic of the memristor. Based on
relation between the memristor voltages and current from the
ohms law, the memristor resistance is
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 IEEE-ICSE2014 Proc. 2014, Kuala Lumpur, Malaysia
v(t ) R MEM ( x)i (t )
The resistance is calculated by dividing voltage over current
from equation 1. To demonstrate the memristor behavior and
to get the resistance value, memristor spice model from [3] is
adopted with spice model parameters as RON=100, ROFF =16k,
RINIT =11k, D=10N, uv=10F and p=10. Fig 1 and Fig 2 shows I-V
characteristic of the spice model and the resistance value
based on I-V derivation. For easier explanation, the resistance
range is only when supply voltage increase from 0 to 1.2 V.
Fig. 1. I-V characteristic of memristor spice model adopted from [13]. Supply
voltage is 1 V and frequency is 1 Hz.
Fig. 2. Resistance of memristor from I-V characteristic data where R= V/I.
Fig. 3: TiO2 thin film memristor structure
(1) Fig 3 illustrates the conceptual view of single memristor
structure: a thin titanium dioxide (TiO2) between two metal
wires (Pt). The inside TiO2 thin film has formed into bilayer.
The first layer is pure titanium oxide layer. It retains its natural
form as an insulator. It is also indicated as undoped region and
has high resistance. The second layer is oxygen deficient
titanium oxide (TiO2-x) layer. It has higher conductivity due to
existence of positively charged oxygen vacancies, thus it acts
as a conductor. It is also indicated as doped region and has low
resistance. When voltage increase from 0V to 1.2V, the oxygen
vacancies in the doped TiO2-x layer are repelled, moving them
towards the undoped TiO2 layer. As a result, the boundary
between the two materials moves, causing an increase in the
percentage of the conducting TiO2-x layer thus the resistance
decreases. This is how a memristor varies its resistance
according to the voltage supply.
B. Memristor Variable Resistance by Pulse Signal
As stated before, memristor resistance changes according to
supply voltage. Two main factors that control the memristor
resistance are the amplitude of the voltage supply and times
memristor is supplied with voltage. Fig 2 shows how the
resistance changes when amplitude of voltage supply changes.
The other factor, time of voltage supplied to memristor is
shown in Fig 4. Here, 1.2 V voltage supply is applied to the
memristor for 3 sec. Graph shows that resistance decreases
over times.
One way to control memristor resistance is proposed in
work [10] where pulse signal input is applied to memristor to
regulate the memristor resistance. According to [17],
memristor resistance change rate depends on the number of
pulse, pulse amplitude, and pulse width. High number of pulse,
high pulse amplitude value and wide pulse width result in
higher resistance. Therefore, to control the memristor
resistance, it is achievable by regulating these three factors. A
pulse input voltage is applied to the memristor spice model to
demonstrate the resistance changes. In Fig 5, pulse input
voltage with different widths is applied to the memristor.
Smaller pulse width results in smaller resistance change rate
and otherwise. Therefore, in this work, pulse input voltage is
applied to memristor to control its resistance.
Fig. 4. Resistance changes over time where 1.2V voltage applied to
memristor.
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 IEEE-ICSE2014 Proc. 2014, Kuala Lumpur, Malaysia

then copied using current mirror, consists of transistor M1-M3.

In order to keep the programmed memristor resistance RMEM
before new resistance input is presented, the charge from iMEM
is stored by capacitor C1. Fig 7 shows voltage at capacitor C1,
Vc. Since memristor model cannot retain its current when input
voltage is 0, the resistance information is kept as charge that
stored by the capacitor.

IV. MEMRISTOR TO CONTROL DELAY OF DELAY ELEMENT

Using the memristor model combined with opamp, resistor
and capacitor, new memristor application as delay element is
proposed. The proposed design in shown is Fig 8.
Fig 5. Memristor resistance changes for pulse input voltage. Pulse width: (a)
75ms, (b) 50ms and (c) 25ms

III. MEMRISTOR MODEL COMBINED WITH CMOS ELEMENT

The circuit of memristor model with CMOS is shown in
Fig 6. As explain before, memristor resistance change rate
increases according to width of pulse signal. Since resistance
changes, memristor current iMEM also change. The memristor
current and resistor R1 generates opamp input voltage.

vin (t ) iMEM (t ) R1 (2)

Fig 8. Memristor spice model with CMOS element to control delay of a current
starved inverter.

First, voltage from capacitor, Vc is converted into control

current, Ic. The control current, Ic then regulates the delay of
the delay element. Here, the delay element consists of current
starved inverter. The gate voltage of M24 and M26 control the
amount of current flow to middle inverter that has parasitic
capacitor, C3. The delay is determined by size of capacitor and
amount of (dis)charging current, IDS as shown in equation (3).
VTN
t delay C (3)
I DS
Fig 6. Memristor spice model with CMOS element for memristor application.
Current from memristor is copy to the current mirror using opamp.
I DS I C (4)

As shown in above equation, delay is regulated by

controlling IDS since C is constant value when transistor in
saturation region. Assuming circuit is in saturation region with
no channel length modulation, the IC is shown below.
1 W
I C n COX VC VTH
2
(5)
2 L
Equation (5) is inserted in equation (3) to roughly estimate the
delay.
VTN
t delay C (6)
1 W
Fig. 7. Voltage capacitor, VC for three different pulse widths. Pulse width: (a)
75ms, (b) 50ms and (c) 25ms.
n COX VC VTH 2

2 L
Equation 6 shows how memristor regulates delay of delay
Resistor R2 is to convert input voltage into an opamp input element. Result for the delay element with memristor is shown
current iin . The opamp input current acts as current source and in Fig. 9 (a), (b) and (c). There are three different outputs

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 IEEE-ICSE2014 Proc. 2014, Kuala Lumpur, Malaysia
according to three different pulse width of supply voltage that
applied to the memristor. In fig 9 (a) pulse width of supply
voltage is 25ms and output signal takes longest time to
generate full output signal. In fig 9 (b) pulse width of supply
voltage is 50ms and output signal takes shorter time to generate
full output signal. In fig 9 (c) pulse width of supply voltage is
75ms and output signal takes shortest time to generate full
output signal. The small pulse width of voltage supply results
in small resistance change rate and therefore the current
produce by memristor is small. Thus, voltage at capacitor, Vc
is small. According to equation (6), since Vc is small, the delay
is bigger and otherwise.
(a)
(b)
(c)
Fig 9. Memristor spice model with CMOS element to control delay of a current
starved inverter. Pulse width: (a) 75ms, (b) 50ms and (c) 25ms.
V. CONCLUSION
In this work, resistance changes of memristor has been
studied and demonstrated using a SPICE memristor model.
One way to control the resistance is using pulse signal for
voltage input that applied to the memristor. A small width of
pulse input results in small memristor change rate. Next,
memristor is combined with opamp, resistor and capacitor to
regulate delay of a current starved inverter. The proposed
SPICE model and CMOS combination is important for
memristor application that works together with CMOS
elements.
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ACKNOWLEDGMENT (Heading 5)
The authors would like to thank the Ministry of Science,
Technology and Innovation (MOSTI) and the Research
Management Institute of Universiti Teknologi MARA (UiTM)
for providing the financial support under the Science Fund
grant (100-RMI/SF 16/6/2 (31/2012).
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