module ram_asincron

(adresa,
data_in,
data_out,
write_en,
clk ) ;

input [6:0] adresa;

input [7:0] data_in;
output [7:0] data_out;
input write_en, clk;

reg [7:0] memory [0:127] ;

always @ (posedge clk)

if(write_en==0)
memory [adresa] <= data_in;

assign data_out = memory[adresa];

endmodule