Electronicadigitalaplicada 150322055612 Conversion Gate01

Electrnica
Digital
Aplicada
Pedro J. Sotorro Ruiz

Diciembre 2013
Electrnica Digital Aplicada
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ndice general:
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Captulo 1.- Presentacin
Captulo 2.- Conceptos y Elementos bsicos

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Captulo 3.- Dispositivos combinacionales
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Captulo 4.- Dispositivos secuenciales
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Captulo 5.- Dispositivos computacionales
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Captulo 6.- Dispositivos de Memoria
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Captulo 7.- Dispositivos Perifricos

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1.1.- Objetivos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2
1.2.- Sobre la Electrnica Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2
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1.3.- Sistemas Digitales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3
1.4.- Tecnologas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4
1.5.- Sobre las referencias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6
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1.1.- Objetivos
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De todos es sabido que la adquisicin de conocimiento es un proceso
acumulativo: lo que eres capaz de aprender ahora est soportado por lo que ya sabes.
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Este hecho es muy importante y marca todo el proceso de aprendizaje en cualquier
materia. La Electrnica Digital es una tcnica que no escapa a este proceso, por eso
es muy importante disponer de unas bases slidas.
El objetivo de este documento es que el lector pueda realizar una aproximacin
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de la parte terica de la Electrnica Digital y la realidad industrial de la misma. Para
ello, tras una breve introduccin a la tcnica en cada captulo, pasamos a utilizar
dispositivos reales disponibles en el mercado. Es por eso que este documento es, en
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parte, una recopilacin de dispositivos digitales tpicos para la realizacin de circuitos
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digitales avanzados.
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1.2.- Sobre la Electrnica Digital

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La Electrnica Digital es una tcnica y como tal consta de una serie de reglas que
actualmente son bien conocidas y eso ayuda mucho a su comprensin.
Afortunadamente disponemos de muy buena documentacin bibliogrfica y no tiene
sentido ampliar en este sentido.
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Por otro lado, la Electrnica Digital se fundamenta en tres apartados: Electricidad,

Electrnica de conmutacin y lgebra binaria. Por eso es necesario disponer de:
Conocimientos amplios de las bases de Electricidad ya que sern utilizados
permanentemente. Ms concretamente es necesario tener conocimientos
de la teora de circuitos.
Conocimientos en el rea de Electrnica de Conmutacin, que es un caso
particular de Electrnica Analgica en cuanto que los transistores trabajan
nicamente en las zonas de corte y saturacin.
Conocimientos del lgebra binaria ya que es la base de casi todas las
aplicaciones reales.
En ningn caso, podemos olvidar que:

La Electrnica es una rama de una ciencia ms extensa denominada
Electricidad y sus bases son las mismas. Por eso en muchos casos
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tendremos que utilizar conceptos de electricidad ya que los esquemas son

elctricos aunque los denominamos electrnicos para diferenciarlos.
La Electrnica Digital (ED) es un caso particular de la Electrnica Analgica
(EA) de la que procede cuando los elementos activos (transistores) trabajan
nicamente en la zona de corte y de saturacin, no utilizando la zona activa
como se hace en EA. Sin embargo, para pasar del estado de corte al de
saturacin y viceversa, los transistores necesitan pasar por la zona activa de
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funcionamiento. Esto nos traer ciertos problemas que analizaremos
detalladamente.
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Los comentarios de los apartados anteriores son importantes en los casos
reales ya que afectan al comportamiento de los elementos. Sin embargo,
nosotros suponemos, inicialmente, que no afecta para nada el trnsito por
la zona activa y slo trabajamos en las de corte y saturacin. Esta es una
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simplificacin muy importante para avanzar en la comprensin de las bases
y de los elementos bsicos de ED. Ms adelante veremos que la circuitera
real no puede eludir la existencia de la zona lineal y, como consecuencia, el
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1.3.- Sistemas Digitales
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Los Sistemas Electrnicos Digitales son siempre complejos. Se basan en

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conceptos simples agrupados de determinadas formas para obtener los resultados que
se pretenden. Como en toda tcnica, en ED se definen los elementos bsicos y sobre
estas definiciones se construyen los elementos complejos. Un simil mecnico puede
ser el de un dispositivo complejo como el motor de un vehculo que se basa en
elementos simples como ejes, ruedas, palancas, etc.
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En el caso que nos atae, Electrnica Digital, la forma de construir es idntica;

unos elementos de base y el apilamiento ordenado de estos elementos da lugar a
sistemas ms complejos. Los elementos de base son simples y fciles de entender
mientras que las reglas de construccin son algo ms complejas, pero en ningn caso
dejan de ser tcnicas.
Esta filosofa de construccin es la que utilizamos para obtener los Sistemas
Electrnicos Digitales Complejos. Utilizando elementos bien conocido y disponibles en
el mercado, los agrupamos para obtener nuestro objetivo. Esta tcnica es similar a la
que utilizan los bricoleros: utilizando los medios disponibles hacemos nuevas cosas.
La tcnica DIY (Do It Yourself) o HTM (Hazlo T Mismo) la utilizamos aqu en el
sentido de construir las distintas partes de un sistema electrnico digital con
dispositivos ya existentes y conocidos. Todos los elementos necesarios para hacer
esto ya deben de ser conocidos cuando se aborda el estudio de los SBM (Sistemas
Basados en Microprocesadores, una asignatura del 2 cuatrimestre). En estos sistemas
no hay circuitos nuevos sino configuraciones nuevas, es decir, formas diferentes de
conexin de los elementos disponibles para formar un nuevo elemento y algunos
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conceptos nuevos.
Por ello, es necesario conocer los circuito bsicos. Este conocimiento implica la
rpida identificacin del grfico que lo representa y la asociacin con su
funcionamiento por medio de los correspondientes cronogramas funcionales. Como se
ver ms adelante, conforme los elementos adquieren complejidad funcional, su
esquema electrnico deja de ser importante y adquiere un papel fundamental su
cronograma funcional. Esto es as hasta tal punto que los fabricantes de sistemas
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medianamente complejos no suministran ms que un pequeo diagrama de bloques
junto a una breve descripcin funcional y su cronograma.
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Por medio de la tcnica HTM construimos elementos cada vez ms complejos
siempre en base a los elementos fundamentales que se describen en los captulos que
siguen.
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1.4.- Tecnologas
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Para la realizacin de los diferentes circuitos digitales que se vern en los
captulos siguientes se utilizan diferentes tecnologas. La figura 1.1 resume una
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coleccin de tecnologa utilizadas por Texas Instruments para realizar sus circuitos
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digitales. En esta figura podemos ver que las tensiones de funcionamiento son de 1.8V,
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3.3V, 5V y 10V. Dentro de cada valor de tensin encontramos diferentes dispositivos

(columnas) y diferentes tecnologas (filas) cuya nomenclatura son los acrnimos (con
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excepciones) que la definen como sigue:

1.8V AUC - Advanced Ultra-Low-Voltage CMOS Logic
AUP - Advanced Ultra-Low-Power CMOS Logic 5V AC - Advanced CMOS Logic
ACT - Advanced CMOS Logic
3.3V ALVC - Advanced Low-Voltage CMOS AHC - Advanced High-Speed CMOS
Technology AHCT - Advanced High-Speed CMOS
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AVC - Advanced Very-Low-Voltage CMOS Logic FCT - Fast CMOS Technology

LV-A - Low-Voltage CMOS Technology HC - High-Speed CMOS Logic
LV-AT - Low-Voltage CMOS Technology HCT - High-Speed CMOS Logic
LVC - Low-Voltage CMOS Technology ABT - Advanced BiCMOS Technology
ALB - Advanced Low-Voltage BiCMOS ABTE - Advanced BiCMOS Technology /
ALVT - Advanced Low-Voltage CMOS Technology Enhanced Transceiver Logic
LVT - Low-Voltage BiCMOS Technology BCT - BiCMOS Technology
CB3Q - Low-Voltage, High-Bandwidth Bus Switch ALS - Advanced Low-Power Schottky Logic
Technology AS - Advanced Schottky Logic
CB3T - Low-Voltage, Translator Bus Switch F - Fast Logic
Technology
LS - Low-Power Schottky Logic
CBTLV - Low-Voltage Crossbar Technology
S - Schottky Logic
GTL - Gunning Transceiver Logic
TTL - Transistor-Transistor Logic
GTLP - Gunning Transceiver Logic Plus
CBT - Crossbar Technology
TS - TI Switch
CBT-C - CBT with Undershoot Protection
TVC - Translation Voltage Clamp
FB - Backplane Transceiver Logic
VME - VME Bus Products
TS - TI Switch
10V CD4000 - CMOS
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Figura 1.1. Familias de circuitos digitales.
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Estas nomenclatura son de este fabricante. Otros fabricantes tienen otras que
pueden no coincidir con este caso. Sin embargo las que coinciden tienen las mismas
caractersticas bsicas y suelen ser compatibles.
Las distintas familias de circuitos presentan distintas caractersticas no solo en la
tensin de alimentacin sino en otros parmetros como los tiempos de conmutacin
retardos, consumos, etc. En cada ocasin debemos seleccionar la tecnologa que
mejor responda a las caractersticas especfica de nuestro diseo.
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1.5.- Sobre las referencias
Al final de cada captulo se ha incluido un conjunto de referencias que no son ms
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(ni menos) que las hojas de caractersticas suministradas por los fabricantes de los
dispositivos tomados como ejemplos. Hay que hacer notar que esta referencias pueden
estar recortadas en cuanto a que se han eliminado las pginas referidas a
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caractersticas mecnicas, embalajes, codificacin y temas no relacionados
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exclusivamente con Electrnica Digital. De esta forma se han ahorrado muchas
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pginas que no resultan tiles en este momento.
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Adems de las referencias en cada captulo, hay tres referencias comunes a libros
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ya publicados que forman la base y son los siguientes:
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1. Fundamentos de Sistemas Digitales, Thomas L. Floyd, Edicin 7, Prentice

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Hall. ISBN: 84-205-2994-X.

2. Sistemas Basados en Microprocesadores, Pedro J. Sotorro, Eduardo Ruiz
y Juan M. Romero, UMA 2004, ISBN: 84-9749-009-5. Reimpresin 2013 en
Copicentro.
3. Diseo Prctico de SBM, Pedro J. Sotorro, Eduardo Ruiz, 2001, ISBN: 84-
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699-4314-6. Reimpresin 2013 Copicentro.

El primero de ellos es el ms clsico utilizado en las Universidades Espaolas
mientras que los otros dos est especficamente desarrollados para la docencia de
SBM en la UMA. En la referencia 2 se describe el funcionamiento de un :P desde su
interior, permitiendo al alumno construir su propio sistema.
NOTA: Todas las referencias citadas son propiedad de los correspondientes
autores.
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Captulo 2.- Conceptos y Elementos bsicos
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2.1.- Conceptos bsicos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
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2.1.1.- Nomenclatura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.1.2.- Niveles digitales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3
2.1.3.- Representacin grfica de los niveles digitales . . . . . . . . . . . . 2.4
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2.1.4.- Representacin grfica de los buses . . . . . . . . . . . . . . . . . . . . 2.5
2.1.5.- Tipos de salida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6
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2.2.- Componentes bsicos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7
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2.3.- Dispositivos especiales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10
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2.4.- Referencias del captulo 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13
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Tema 2.- Conceptos y Elementos bsicos

Como se ha descrito en el apartado anterior, la tcnica DIY utiliza elementos
simples para construir otros ms complejos. Es por ello que en este apartado vamos
a recordar los elementos bsicos que utilizaremos as como algunos conceptos
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necesarios y su realizacin electrnica.
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2.1.- Conceptos bsicos
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Empezamos por describir algunos conceptos bsicos que deben de ser conocidos
para poder avanzar en el resto de temas:
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2.1.1.- Nomenclatura
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adPara poder entendernos con facilidad necesitamos definir el protocolo que vamos
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a utilizar. Al igual que en otras especialidades, en ED existe un argot propio que es

necesario conocer para no confundir los conceptos. En lo que sigue hacemos una
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introduccin a la nomenclatura que utilizamos en este documento y que se

corresponde con la habitual en ED. Cuando sea posible, describiremos la
nomenclatura en Espaol y en Ingls para que se vea la correlacin entre las
expresiones. No se trata de hacer un diccionario sino de describir la forma de hacer las
cosas.
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Niveles digitales: Es muy habitual representarlos por los smbolos numricos 1"
y 0" pero tcnicamente es ms correcto utilizar las letras H (High) para el nivel
alto o 1" y L (Low) para el nivel bajo o 0". De hecho el la informacin tcnica
profesional se utiliza esta ltima nomenclatura. Como se ver mas adelante,
tambin utilizamos un pseudo nivel que denominamos triestado (three state)y que
se representa con la letra Z.
Seales: Una seal se identifica por medio de una o varias letras que constituye
su nombre. Conviene que el nombre de las seales tenga relacin con su funcin.
Lo ms usual es utilizar una palabra o un acrnimo que nos recuerde para lo que
se utiliza la seal. Por ejemplo, en SED se utiliza muchas seales que se
denominan /RD (ReaD, lectura), /WR (WRite , escritura), /CS (Chip Select,
seleccin de dispositivo),... Aunque podemos asignar cualquier otro nombre, los
utilizados habitualmente presentan la ventaja de ser fcilmente comprendidos.
V1.0 2.2
Como podemos ver, en los nombre de las seales citadas antes hay una barra /
delante del nombre. Esto es para indicar que el estado activo de esta seal es el
nivel L. Por lo tanto, el nivel H es el estado de reposo. Esta nomenclatura se
utiliza en seales que actan o controlan algo. En seales que forman parte de
un conjunto numrico (un dato binario), esta barra no se pone ya que no es
relevante.
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Buses: Para nosotros un BUS es un conjunto de seales homogneas o no. En
los sistemas digitales complejos es muy frecuente agrupar las seales en buses.
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Cada una de las seales de un bus tiene su propio nombre que es necesario
identificar con vista a que cualquier lector del documento que sea pueda entender
las explicaciones, los cronogramas o los esquemas, segn correspondan.
Los nombres de las seales dentro de un bus se establecen con el mismo criterio
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que se ha descrito en el apartado anterior. Sin embargo, cuando el conjunto de
todas las seales de un bus forman una nica informacin (tpicamente
numrica), que es el caso de los buses homogneos, los nombres de las seales
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suelen tener una raz comn y un nmero asociado que las distingue unas de
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otras. As por ejemplo, un bus de direcciones de 16 bits se suele denominar
ABUS y sus seales se denominan A15, A14, A13, ..., A3, A2, A1 y A0. Observar
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que la numeracin va de n-1 hasta 0 ya que la primera combinacin vlida es el
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0 y no el 1. De hecho, el sistema de numeracin decimal no va de 1 a 10 sino de
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0 a 9. El nmero 10 es una combinacin de dos smbolos numricos y no forma

parte de la base.
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2.1.2.- Niveles digitales

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En electrnica digital trabajamos con dos valores elctricos que identificamos con
los smbolos 1 y 0 y que habitualmente asociamos con un valor alto y un valor
bajo de la tensin respectivamente en el punto que se trata. Esto no es
estrictamente cierto y por eso el ttulo de este apartado habla de Niveles y no de
valores. Los niveles son un conjunto de valores para los cuales se cumple la
condiciones funcionales.
Nivel bajo (L) o 0" digital: Concretamente, hablando de un sistema que

funciona a 5V (entre 0 y 5V), el smbolo binario 0" se representa
elctricamente por medio de un conjunto de valores de tensin entre 0.0V
y 0.4V para las tensiones de entrada y entre 0.0V y 0.8V para las tensiones
de salida. As pues, cuando la salida de un circuito digital est en el estado
bajo, elctricamente esta salida tiene una tensin comprendida entre 0.0V
y 0.4V y se denomina VoL. Cuando en una entrada tenemos un nivel bajo,
la tensin en ella ha de estar comprendida entre 0.0V y 0.8V y se denomina
ViL. As, por ser ViLmax > VoLmax, se asegura un margen de error de 0.4V
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(mnimo).
Nivel alto (H) o 1" digital: De forma similar a lo dicho en el prrafo

anterior, los valores de tensiones para el nivel alto a la tensin de
alimentacin de 5V) son de 2.0V a 5.0V para el nivel alto de entrada (ViH) y
3.0V a 5.0V para el nivel alto de salida (VoH). En este caso el margen de
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seguridad es de 1V (VoH - ViH).
Cuando los niveles de tensin digitales tienen otros valores (3.3V, 12V, etc),
las definiciones de los niveles alto y bajo son diferentes.
Ap git ic Tercer nivel digital: Se denomina as al estado de desconexin de la

salida de un circuito. Hay multitud de ocasiones en que es necesario
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desconectar la salida de un dispositivo y esto se hace por medio de una
seal que controla este estado. Como es fcil de comprobar no se trata
realmente de un estado digital en s mismo ya que por el hecho de estar
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a embargo es muy cmodo utilizar la expresin de tercer nivel y como tal lo
utilizaremos teniendo claro su concepto. Este tercer nivel recibe el nombre
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de desconexin lgica (no fsica) o triestado (Three state) y se representa
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2.1.3.- Representacin grfica de los niveles digitales

En Electrnica Digital, como en otras ciencias, se trabaja mucho con grficos
porque las descripciones funcional verbal es realmente complicada de hacer.
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La representacin grfica de las distintas combinaciones funcionales posibles de

las seales de un dispositivo puede ser muy compleja y ello depende de la
funcionalidad del propio dispositivo. Sin embargo estas representaciones grficas
denominadas cronogramas, describen la evolucin de las seales a lo largo del
tiempo de una forma simple.
Un cronograma no es ms que la representacin en el eje del tiempo (eje x) de
la evolucin de los valores digitales de las seales que tiene un dispositivo digital.
En s mismo, los cronogramas definen la funcionalidad de los dispositivos desde
el punto de vista de la circuitera (hardware).
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Figura 2.1. Representacin grfica de los niveles en una seal digital.
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En la figura 2.1 se han representado los niveles de una seal que evoluciona
entre los tres niveles citados antes: durante los intervalos A y D, la seal se
encuentra a nivel alto H; durante el intervalo B, la seal se encuentra a nivel bajo
L y durante los intervalos C y E, la seal se encuentra en desconexin Z.
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2.1.4.- Representacin grfica de los buses
Dado que un bus es un conjunto de seales, cuando el bus es homogneo (todas
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las seales estn relacionadas formando una sola informacin), el conjunto del bus se
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representa de una forma simplificada como se ha representado en la figura 2.2. En la
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figura 2.2a) se ha representado un bus tpico de direcciones compuesto de 16 seales

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(A15 - A0) sin triestado. En esta figura hay marcadas 5 zonas: las zonas 2 y 4
representan los intervalos de cambios en el bus. No significa que todas las seales del
bus cambien de nivel, con que haya una sola seal que lo haga ya ha cambiado el
conjunto (el valor numrico representado por las seales del bus) y por lo tanto esta
es su representacin. Observar que entre la zona 1 y la 3 slo cambia un bit (A0 pasa
de L a H), mientras que entre la zona 3 y la 5 cambian bastantes bits. Es por esto por
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lo que entre las dos lneas de la representacin se coloca el valor del conjunto de
seales (valor del bus) durante ese periodo de tiempo. Observar que los valores se
indican en hexadecimal, nunca en decimal ni en binario. Durante los intervalos de
trnsito (2 y 4) no es conocido el valor del bus. Estos intervalos de trnsito son muy
Figura 2.2. Cronograma de buses homogneos. a) bus sin desconexin, b)

bus con desconexin.
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cortos (alguna decena de ns) pero eso no les resta importancia y por eso hay que
representarlos.
La figura 2.2 b) representa un bus con triestado (desconexin). Es el caso tpico
de un bus de datos de un SBM. Los intervalos de tiempo 2, 4, 6 y 8 representan los
intervalos en los que el contenido del bus est cambiando. Su valor es desconocido.
En los intervalos 1 y 9 el bus se encuentra desconectado y se representa por medio
de una lnea horizontal entre el nivel H y el nivel L (este es el nivel Z citado antes). En
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los intervalos 3, 5 y 7 el valor del bus es estable y en la figura se ha colocado su valor
numrico. Observar que los valores se indican en hexadecimal, nunca en decimal ni
en binario.
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2.1.5.- Tipos de salida
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Las etapas de salida de un circuito digital presentan tres tipos de salida cuyas
caractersticas funcionales son muy diferentes y por ello se utilizan para aplicaciones
especficas.
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Salida Totem-Pole: El circuito de salida con dos transistores representado en
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la figura 2.3 recibe el nombre de Totem.Pole. Este tipo de salida tiene como
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caracterstica que la seal procedente de l presenta siempre baja impedancia ya
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se encuentre a nivel H o a nivel L. Esto es importante para asegurar los niveles

digitales correctos en la mayora de las aplicaciones. Es por eso que casi todas
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las etapas de salida disponen de este tipo de salida.

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Figura 2.3. Esquema

elctrico de la etapa de
salida Totem-Pole.
En la figura 2.3 se puede ver el esquema elctrico de esta etapa. La seal

procedente de la etapa anterior (que es la que realiza la funcin digital que le
corresponda) llega a esta etapa de salida haciendo que slo uno de los
transistores de salida T3 y T4 se mantenga en conduccin en cada nivel.
Salida en colector abierto: Es tipo de salida es el mostrado en la figura 2.4. En

ella podemos ver que la seal de salida se conecta directamente al colector y en
l no hay otras conexiones. Este tipo de salida se utiliza en algunas ocasiones
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pero no es la ms frecuente en ED.
Figura 2.4. Esquema elctrico

de la etapa de salida en
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colector abierto.
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Salida triestado: Es el tipo de salida que permite disponer del estado de
desconexin citado anteriormente. La figura 2.5 muestra el esquema de este tipo
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de salida que dispone de una seal de control adicional que permite desconectar
lgicamente (no fsicamente) el dispositivo sin realizar una desconexin fsica.
Este tipo de salida se utiliza mucho en SBM en donde las conexiones por medio
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de buses es muy frecuente.
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Figura 2.5. Esquema elctrico de la

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etapa de salida Totem-Pole con

desconexin (triestado).
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2.2.- Componentes bsicos

En lo que sigue describimos los elementos bsicos ya conocidos por todos y su
realizacin por medio de circuitos electrnicos. En todos los casos hacemos uso de
referencias a las hojas de caractersticas suministradas por algunos fabricantes para
poder contrastar la informacin.
Inversor: En electrnica digital, un inversor es un dispositivo cuyo valor elctrico

de salida es el inverso (desde el punto de vista binario), es decir que si a su
entrada hay un 1", a su salida hay un 0" y si en su entrada es 0", en su salida
V1.0 2.7
hay un 1". Como sabemos, esto se representa por medio de una tabla de verdad
como sigue:
E S
Figura 2.6. Cronograma del
0 1
inversor.
1 0
a
donde E es la seal de entrada y S es la seal de salida.
Tambin podemos representar su funcionamiento por medio de un
cronograma como el de la figura 2.6. La figura 2.7 muestra un esquema
Ap git ic
electrnico que realiza la funcin inversin. En esta figura tambin podemos ver
el smbolo que se utiliza para representarlo.
Di n
lic l Figura 2.7. Esquema de
un inversor digital y
a
a su smbolo
r
ad
t
ec
Ver la referencia 74LS04.
AND: El funcionamiento de una funcin AND de dos entradas (A y B) se describe

por medio de la tabla de verdad y el cronograma siguiente:
El
A B Salida
0 0 0
Figura 2.8. Cronograma
0 1 0
de la funcin AND.
1 0 0
1 1 1
donde la salida slo toma el valor binario 1" cuando en ambas entradas tenemos
un valor binario 1". La figura 2.9 muestra un esquema electrnico que realiza
esta funcin digital y su representacin.
V1.0 2.8
a
Ap git ic Figura 2.9. Esquema elctrico de una funcin AND de dos entradas y su
smbolo.
Di n
lic l
a
a
r
NAND: Esta es una funcin cuya tabla de verdad (para dos entradas) es:
ad
t
ec
A B S
0 0 1
0 1 1
1 0 1
1 1 0
Figura 2.10. Smbolo y cronograma de una funcin
NAND.
El
Como puede verse, es la funcin inversa de la funcin AND. Su circuito se

puede realizar conectando en serie el circuito de la funcin AND y el del inversor
vistos antes. Su representacin es la que se muestra en la figura 2.10, donde
tambin se ha representado un cronograma de funcionamiento.
OR: La funcin OR de dos entradas se define por medio de la tabla de verdad

siguiente:
A B S
0 0 0 Figura 2.11. Tabla de verdad,
0 1 1 smbolo y cronograma de la
1 0 1 funcin OR.
1 1 1
V1.0 2.9
La figura 2.11 muestra el smbolo que la representa y un cronograma de

funcionamiento. La figura 2.12 muestra un esquema elctrico que realiza esta
funcin lgica.
a
Figura 2.12. Esquema elctrico de
una funcin OR de dos entradas
Ap git ic
Di n
lic l
a
a
NOR: Esta funcin es la complementaria (inversa) de la funcin OR. Su tabla de
r
verdad y cronograma funcional es:
ad
t
A B S
ec
0 0 1 Figura 2.13. Tabla de verdad,

smbolo y cronograma de la
0 1 0
funcin NOR.
1 0 0
1 1 0
El
La figura 2.13 contiene el smbolo y un cronograma funcional de una puerta

NOR. Ver la referencia 74LS02.
XOR: Esta funcin lgica se define por medio de su tabla de verdad y el

cronograma siguiente:
A B S
0 0 0 Figura 2.14. Tabla de vardad y
0 1 1 cronograma de la funcin XOR
1 0 1
1 1 0
El esquema lgico de esta funcin es el representado en la figura 2.15 junto

a su smbolo.
V1.0 2.10
Figura 2.15. Esquema lgico y

smbolo de la funcin XOR.
a
Ver la referencia 74HCT86.
Ap git ic
2.3.- Dispositivos especiales
Di n
Por dispositivos especiales entendemos aquellos que no siendo pertenecientes
a la realizacin de los conceptos bsicos de funciones booleanas, son necesarios para
aplicaciones en general y en SBM en particular.
lic l
a
a
Amplificador binario unidireccional: Se trata de un dispositivo que amplifica la
seal binaria. Como no se puede amplificar en tensin ya que los valores de los
r
ad
niveles digitales se establecen por tensin, se amplifica en corriente. Es decir son
t
dispositivos que son capaces de suministrar una alta corriente frente a los
dispositivos normales. El trmino alta corriente se ha situado entre comillas ya
ec
que en electrnica digital una corriente alta puede ser de tan solo unas decenas
de miliamperios. De hecho los dispositivos que vemos a continuacin suministran
a su salida unos 24 mA.
Dispositivo 74LS244: La figura 2.16 es el esquema digital de este
dispositivo.
El
V1.0 2.11
a
Figura 2.16. Esquema digital
del dispositivo 74LS244.
Ap git ic
Di n
lic l
a
a
r
En esta figura podemos ver que el dispositivo se compone de dos partes
ad
independientes. Cada una de ellas consta de cuatro amplificadores digitales con
t
salida triestado. Si vemos en la referencia 74LS244, veremos que el fabricante lo

ec
denomina como Octal Buffers And Line Drivers With 3-state Outputs, lo que
significa que se trata de un conjunto de ocho amplificadores digitales con salida
triestado. Atencin a la palabra buffer que tiene muchos significados dentro de
la ED. De hecho estos dispositivos se utilizan mucho para hacer las interfases con
los buses de un SBM.
Dispositivo 74LS240: Es similar al dispositivo 74LS244 pero tiene la salida
El
invertida respecto a la entrada. Ver la referencia 74LS244.
V1.0 2.12
Amplificador binario bidireccional: Se trata de un dispositivo amplificados como

el caso del 74LS244 pero que adems permite que las seales fluyan en los dos
sentidos posibles un una conexin (no simultneamente). El dispositivo mas
clsico es el 74LS245, cuyo esquema digital lo podemos ver en la figura 2.17.
a
Ap git ic
Di n
lic l del dispositivo 74LS245.
a
a
r
ad
t
ec
El
En esta figura podemos ver que adems de una seal para controlar la
desconexin del dispositivo (/OE) tambin hay una seal para controlar el sentido
de la informacin (DIR), de tal que si DIR = H la informacin fluye de los
terminales An hacia los terminales Bn y si DIR = L la informacin fluye desde los
terminales Bn hacia los terminales An. A esto se denomina bidireccional.
Observando la figura y comparndola con la del 74LS244 (figura 2.16), podemos
concluir que este dispositivo se basa en disponer de dos 74LS244 conectados en
oposicin y con un control de activacin.
V1.0 2.13
2.4.- Referencias del captulo 2
a
Ap git ic
Di n
lic l
a
a
r
ad
t
ec
El
V1.0 2.14

SDLS025B DECEMBER 1983 REVISED OCTOBER 2003
D Package Options Include Plastic D Also Available as Dual 2-Input

Small-Outline (D, NS, PS), Shrink Positive-NAND Gate in Small-Outline (PS)
Small-Outline (DB), and Ceramic Flat (W) Package
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
SN5400 . . . J PACKAGE
SN54LS00, SN54S00 . . . J OR W PACKAGE
a
SN7400, SN74S00 . . . D, N, OR NS PACKAGE
SN74LS00 . . . D, DB, N, OR NS PACKAGE SN74LS00, SN74S00 . . . PS PACKAGE
(TOP VIEW) (TOP VIEW)
Ap git ic
1A 1 14 VCC 1A 1 8 VCC
1B 2 13 4B 1B 2 7 2B
1Y 3 12 4A 1Y 3 6 2A
2A 4 11 4Y GND 4 5 2Y
2B 5 10 3B
Di n
2Y 6 9 3A
GND 7 8 3Y
lic l SN5400 . . . W PACKAGE SN54LS00, SN54S00 . . . FK PACKAGE
a
a (TOP VIEW) (TOP VIEW)
VCC
NC
1B
1A
4B
1A 1 14 4Y
r
1B 2 13 4B
ad 1Y 3 12 4A 1Y 4
3 2 1 20 19
18 4A
t
VCC 4 11 GND NC 5 17 NC
2Y 5 10 3B 2A 6 16 4Y
ec
2A 6 9 3A NC 7 15 NC
2B 7 8 3Y 2B 8 14 3B
9 10 11 12 13
GND
2Y
3Y
3A
NC
NC No internal connection
El
description/ordering information
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function
Y = A B or Y = A + B in positive logic.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

! "#$ ! %#&'" ($) Copyright 2003, Texas Instruments Incorporated
(#"! " !%$""! %$ *$ $! $+! !#$! %(#"! "%' / 0121 '' %$$! $ $!$(
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ #'$!! *$,!$ $() '' *$ %(#"! %(#"
$!. '' %$$!) %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE
PART NUMBER MARKING
SN7400N SN7400N
PDIP N Tube SN74LS00N SN74LS00N
a
SN74S00N SN74S00N
Tube SN7400D
7400
Tape and reel SN7400DR
Ap git ic
Tube SN74LS00D
SOIC D LS00
Tape and reel SN74LS00DR
0C
0 C to 70C
70 C Tube SN74S00D
S00
Tape and reel SN74S00DR
Di n
SN7400NSR SN7400
SOP NS Tape and reel SN74LS00NSR 74LS00
SN74S00NSR 74S00
lic l SOP PS Tape and reel

SN74LS00PSR
SN74S00PSR
LS00
S00
a
a SSOP DB Tape and reel SN74LS00DBR
SNJ5400J
LS00
SNJ5400J
r
CDIP J Tube SNJ54LS00J SNJ54LS00J
ad SNJ54S00J SNJ54S00J
t
SNJ5400W SNJ5400W
55C to 125C
ec
CFP W Tube SNJ54LS00W SNJ54LS00W

SNJ54S00W SNJ54S00W
SNJ54LS00FK SNJ54LS00FK
LCCC FK Tube
SNJ54S00FK SNJ54S00FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
El
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H H L
L X H
X L H
logic diagram, each gate (positive logic)
A
Y
B
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

schematic
00
VCC
4 k 1.6 k 130
a
A
B Y
Ap git ic 1 k
GND
Di n
LS00 S00
lic l VCC VCC
a
a 20 k 8 k 120 2.8 k 900 50
r
ad
t
A
3.5 k
ec
B A
Y
12 k Y B
4 k
500 250
El
1.5 k 3 k
GND
GND
Resistor values shown are nominal.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: 00, S00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
LS00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
a
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Ap git ic
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
Di n
recommended operating conditions (see Note 3)
SN5400 SN7400
UNIT
lic l MIN NOM MAX MIN NOM MAX
a
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH
VIL
a High-level input voltage
Low-level input voltage
2
0.8
2
0.8
V
V
r
IOH High-level output current 0.4 0.4 mA
ad
IOL Low-level output current 16 16 mA
t
TA Operating free-air temperature 55 125 0 70 C

ec
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN5400 SN7400
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
El
VIK VCC = MIN, II = 12 mA 1.5 1.5 V

VOH VCC = MIN, VIL = 0.8 V, IOH = 0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 A
IIL VCC = MAX, VI = 0.4 V 1.6 1.6 mA
IOS VCC = MAX 20 55 18 55 mA
ICCH VCC = MAX, VI = 0 V 4 8 4 8 mA
ICCL VCC = MAX, VI = 4.5 V 12 22 12 22 mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

SN5400
FROM TO SN7400
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 11 22
A or B Y RL = 400 , CL = 15 pF ns
tPHL 7 15
a
SN54LS00 SN74LS00
UNIT
MIN NOM MAX MIN NOM MAX
Ap git ic
VCC
VIH
VIL
IOH
Supply voltage
High-level input voltage
High-level output current
4.5
2
5 5.5
0.7
0.4
4.75
2
5 5.25
0.8
0.4
V
V
V
mA
Di n
lic l Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
a
a
otherwise noted)
r
ad
PARAMETER TEST CONDITIONS
SN54LS00
TYP
SN74LS00
TYP
UNIT
t
MIN MAX MIN MAX

ec
VOH VCC = MIN, VIL = MAX, IOH = 0.4 mA 2.5 3.4 2.7 3.4 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOL VCC = MIN, VIH = 2 V V
IOL = 8mA 0.35 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7V 20 20 A
IIL VCC = MAX, VI = 0.4 V 0.4 0.4 mA
El
IOS VCC = MAX 20 100 20 100 mA

ICCH VCC = MAX, VI = 0 V 0.8 1.6 0.8 1.6 mA
ICCL VCC = MAX, VI = 4.5 V 2.4 4.4 2.4 4.4 mA

SN54LS00
FROM TO SN74LS00
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 9 15
A or B Y RL = 2 k, CL = 15 pF ns
tPHL 10 15


SN54S00 SN74S00
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
a
IOH High-level output current 1 1 mA
Ap git ic

otherwise noted)
Di n
SN54S00 SN74S00
lic l VOH VCC = MIN, VIL = 0.8 V, IOH = 1 mA 2.5 3.4 2.7 3.4 V
a
a VOL
II
IIH
VCC = MIN,
VCC = MAX,
VCC = MAX,
VIH = 2 V,
VI = 5.5 V
VI = 2.7 V
IOL = 20 mA 0.5
1
50
0.5
1
50
V
mA
A
r
IIL VCC = MAX, VI = 0.5V 2 2 mA
ad IOS
t
VCC = MAX 40 100 40 100 mA

ec


SN54S00
El
FROM TO SN74S00
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 3 4.5
A or B Y RL = 280 , CL = 15 pF ns
tPHL 3 5
tPLH 4.5
A or B Y RL = 280 , CL = 50 pF ns
tPHL 5

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL
a
CL
From Output RL (see Note A) 1 k
Under Test (see Note B) From Output Test
CL Under Test Point
Ap git ic
(see Note A) CL
(see Note A) S2
LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

Di n
FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS
3V
High-Level Timing
Pulse 1.5 V 1.5 V Input 1.5 V
lic l tw th
0V
a
a
Low-Level 1.5 V 1.5 V Data
tsu
1.5 V 1.5 V
3V
r
Pulse Input
0V
ad VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

t
PULSE DURATIONS SETUP AND HOLD TIMES

ec
Output 3V
Control
(low-level 1.5 V 1.5 V
3V
Input 1.5 V 1.5 V enabling) 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 1.5 V
In-Phase VOH (see Notes C 1.5 V
El
Output 1.5 V 1.5 V and D) VOL + 0.5 V

(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase VOH Waveform 2 VOH 0.5 V
Output (see Notes C 1.5 V
1.5 V 1.5 V 1.5 V
(see Note D) and D)
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series
54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms

El
ec
t
Di n r
Ap git ic
lic l a a
ad
a
El
ec
t
Di n r
Ap git ic
lic l a a
ad
a
El
ec
t
Di n r
Ap git ic
lic l a a
ad
a
El
ec
t
Di n r
Ap git ic
lic l a a
ad
a
El
ec
t
Di n r
Ap git ic
lic l a a
ad
a

SDLS029C DECEMBER 1983 REVISED JANUARY 2004
D Dependable Texas Instruments Quality and SN5404 . . . J PACKAGE

Reliability SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404, SN74S04 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
description/ordering information
These devices contain six independent inverters. 1A 1 14 VCC
1Y 2 13 6A
a
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
Ap git ic
GND 7 8 4Y
SN5404 . . . W PACKAGE
(TOP VIEW)
Di n
1A 1 14 1Y
2Y 2 13 6A
2A 3 12 6Y
lic l VCC 4 11 GND
a
3A 5 10 5Y
a 3Y
4A
6
7
9
8
5A
4Y
r
ad SN54LS04, SN54S04 . . . FK PACKAGE
t
(TOP VIEW)
VCC
NC
ec
1Y
1A
6A
3 2 1 20 19
2A 4 18 6Y
NC 5 17 NC
2Y 6 16 5A
NC 7 15 NC
3A 8 14 5Y
El
9 10 11 12 13
3Y
4Y
4A
GND
NC
NC No internal connection
!" #!$% &"' Copyright 2004, Texas Instruments Incorporated
&! #" #" (" " ") !" #&! #% -./.010 %% #"" " ""&
&& *+' &! #", &" ""%+ %!&" !%" ("*" "&' %% (" #&! #&!
", %% #""' #", &" ""%+ %!&" ", %% #""'

ORDERABLE TOP-SIDE
TA PACKAGE
PART NUMBER MARKING
Tube SN7404N SN7404N
Tube SN74S04N SN74S04N
Tube SN7404D
a
7404
Tape and reel SN7404DR
Tube SN74LS04D
SOIC D LS04
0C
0 C to 70C
70 C Tape and reel SN74LS04DR
Ap git ic
Tube SN74S04D
S04
Tape and reel SN74S04DR
Tape and reel SN7404NSR SN7404
Di n
Tape and reel SN74S04NSR 74S04
SSOP DB Tape and reel SN74LS04DBR LS04
Tube SN5404J SN5404J
lic l Tube
Tube
SNJ5404J
SN54LS04J
SNJ5404J
SN54LS04J
a
a CDIP J
Tube
Tube
SN54S04J
SNJ54LS04J
SN54S04J
SNJ54LS04J
r
55C
55 C to 125
125C
C Tube SNJ54S04J SNJ54S04J
ad Tube SNJ5404W SNJ5404W

t

ec
Tube SNJ54S04W SNJ54S04W

Tube SNJ54LS04FK SNJ54LS04FK
LCCC FK
Tube SNJ54S04FK SNJ54S04FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
El
(each inverter)
INPUT OUTPUT
A Y
H L
L H

logic diagram (positive logic)
1A 1Y
2A 2Y
a
3A 3Y
4A 4Y
Ap git ic 5A
6A
5Y
6Y
Di n
Y=A
lic l
a
a
r
ad
t
ec
El

schematics (each gate)

04
VCC
4 k 1.6 k 130
a
Input A
Ap git ic Output Y
Di n
1 k
lic l GND
a
a LS04 S04
r
VCC VCC
ad
t
20 k 8 k 120 2.8 k 50
900
ec
Input
A 3.5 k Output
Input 4 k Output Y
A Y
El
12 k
250
500
3 k
1.5 k
GND
GND
Resistor values shown are nominal.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage, VI: 04, S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
a
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and
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2. The package thermal impedance is calculated in accordance with JESD 51-7.

Di n
SN5404 SN7404
UNIT
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VCC
VIH
Supply voltage
High-level input voltage
4.5
2
5 5.5 4.75
2
5 5.25 V
V
a
VIL
IOH
a Low-level input voltage
0.8
0.4
0.8
0.4
V
mA
r
TA
ad Operating free-air temperature 55 125 0 70 C

t
ec

otherwise noted)
SN5404 SN7404
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VOH VCC = MIN, VIL = 0.8 V, IOH = 0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
IIH VCC = MAX, VI = 2.4 V 40 40 A
IIL VCC = MAX, VI = 0.4 V 1.6 1.6 mA
IOS VCC = MAX 20 55 18 55 mA


SN5404
FROM TO SN7404
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 12 22
A Y RL = 400 , CL = 15 pF ns
tPHL 8 15
a
SN54LS04 SN74LS04
UNIT
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IOH High-level output current 0.4 0.4 mA
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a
a
otherwise noted)
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SN54LS04 SN74LS04
TEST CONDITIONS
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PARAMETER
UNIT
t

VOH VCC = MIN, VIL = MAX, IOH = 0.4 mA 2.5 3.4 2.7 3.4 V
ec
IOL = 4 mA 0.25 0.4 0.4

VOL VCC = MIN, VIH = 2 V V
IOL = 8 mA 0.25 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 A
IIL VCC = MAX, VI = 0.4 V 0.4 0.4 mA
IOS VCC = MAX 20 100 20 100 mA
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ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA

ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

SN54LS04
FROM TO SN74LS04
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 9 15
A Y RL = 2 k, CL = 15 pF ns
tPHL 10 15


SN54S04 SN74S04
UNIT
a
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otherwise noted)
SN54S04 SN74S04
Di n
VOH VCC = MIN, VIL = 0.8 V, IOH = 1 mA 2.5 3.4 2.7 3.4 V
lic l VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V
a
a
II
IIH
VCC = MAX,
VCC = MAX,
VI = 5.5 V
VI = 2.7 V 50
1
50
1 mA
A
r
IIL VCC = MAX, VI = 0.5 V 2 2 mA
ad IOS VCC = MAX 40 100 40 100 mA

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Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

SN54S04
FROM TO SN74S04
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(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 3 4.5
A Y RL = 280 , CL = 15 pF ns
tPHL 3 5
tPLH 4.5
A Y RL = 280 , CL = 50 pF ns
tPHL 5


SERIES 54/74 AND 54S/74S DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
a
RL CL
CL Under Test Point
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(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
lic l th
0V
a
tw
a
Low-Level 1.5 V 1.5 V Data
tsu
1.5 V 1.5 V
3V
r
Pulse Input
0V

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Output 3V
Control
3V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 1.5 V
In-Phase
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VOH (see Notes C 1.5 V

(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
1.5 V 1.5 V 1.5 V
(see Note D) and D)
VOL

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
F. The outputs are measured one at a time, with one input transition per measurement.


SERIES 54LS/74LS DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
a
RL CL
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CL Under Test Point
(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
1.3 V 1.3 V 1.3 V
lic l Pulse Input

0V
a
a
Low-Level
tw
Data
tsu
th
3V
r
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
ad 0V
t

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Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1
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In-Phase 1.5 V
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH 0.5 V
VOH
1.3 V 1.3 V 1.5 V
(see Note D) and D)
VOL
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.

SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
QUADRUPLESDLS033
2-INPUT POSITIVE-AND GATES
DECEMBER 1983 REVISED MARCH 1988
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PRODUCTION DATA information is current as of publication date. Copyright 1988, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SDLS033 DECEMBER 1983 REVISED MARCH 1988
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SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
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SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
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SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
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a
MC74VHC86
Quad 2-Input XOR Gate

The MC74VHC86 is an advanced high speed CMOS 2input
ExclusiveOR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
a
The internal circuit is composed of three stages, including a buffer http://onsemi.com
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V MARKING
systems to 3 V systems. DIAGRAMS
Ap git ic
Features
High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V

Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C 14
1
SOIC14
D SUFFIX
CASE 751A
14
VHC86G
AWLYWW
Di n
High Noise Immunity: VNIH = VNIL = 28% VCC 1
Power Down Protection Provided on Inputs
14
Balanced Propagation Delays
VHC
lic l
Designed for 2 V to 5.5 V Operating Range TSSOP14
DT SUFFIX 86
a
Low Noise: VOLP = 0.8 V (Max) ALYWG
a
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
1 CASE 948G
1
G
r
ad
ESD Performance: Human Body Model (HBM) > 2000 V; 14
t
Machine Model > 200 V SOEIAJ14

VHC86
Chip Complexity: 56 FETs or 14 Equivalent Gates M SUFFIX
ALYWG
CASE 965
ec
These Devices are PbFree and are RoHS Compliant 1

1
1
A1 3
2 Y1 A = Assembly Location
B1 WL, L = Wafer Lot
4
A2 Y, YY = Year
6
5 Y2 WW, W = Work Week
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B2 G or G = PbFree Package
9 (Note: Microdot may be in either location)
A3 8 Y = AB
10 Y3
B3
12 FUNCTION TABLE
A4 11
13 Y4 Inputs Output
B4
A B Y
Figure 1. Logic Diagram
L L L
L H H
H L H
VCC B4 A4 Y4 B3 A3 Y3 H H L
14 13 12 11 10 9 8
1 2 3 4 5 6 7
A1 B1 Y1 A2 B2 Y2 GND See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Pinout: 14Lead Packages (Top View)
Semiconductor Components Industries, LLC, 2011 1 Publication Order Number:

May, 2011 Rev. 5 MC74VHC86/D
MC74VHC86

MAXIMUM RATINGS

Symbol

VCC

DC Supply Voltage
Parameter Value
0.5 to +7.0
Unit
V
This device contains protection
circuitry to guard against damage

due to high static voltages or electric
Vin DC Input Voltage 0.5 to +7.0 V fields. However, precautions must

be taken to avoid applications of any
Vout DC Output Voltage 0.5 to VCC +0.5 V

voltage higher than maximum rated
IIK Input Diode Current 20 mA voltages to this highimpedance cir-

cuit. For proper operation, Vin and
IOK Output Diode Current $20 mA

Vout should be constrained to the
a
Iout DC Output Current, per Pin $25 mA range GND v (Vin or Vout) v VCC.

Unused inputs must always be
ICC DC Supply Current, VCC and GND Pins $50 mA tied to an appropriate logic voltage

PD

Power Dissipation in Still Air,

SOIC Packages
TSSOP Package
500
450
mW level (e.g., either GND or V CC ).
Unused outputs must be left open.
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Tstg

Storage Temperature 65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
C
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Di n
Derating SOIC Packages: 7 mW/C from 65 to 125C
TSSOP Package: 6.1 mW/C from 65 to 125C

lic l
RECOMMENDED OPERATING CONDITIONS
a
Symbol
VCC
a

DC Supply Voltage

Parameter Min
2.0
Max
5.5
Unit
V
r
Vin DC Input Voltage 0 5.5 V

ad
Vout

DC Output Voltage

0 VCC V
t
TA Operating Temperature, All Package Types 55 +125 C

tr, tf

Input Rise and Fall Time VCC = 3.3 V 0.3 V 0 100 ns/V
ec

VCC = 5.0 V 0.5 V 0 20
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http://onsemi.com
2
MC74VHC86

DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Test Conditions
VCC
V Min
TA = 25C
Typ Max
TA = 55C to +125C
Min Max Unit
VIH

Voltage

HighLevel Input

2.0
3.0 to
5.5
1.50
VCC x 0.7
1.50
VCC x 0.7
V
VIL

Voltage

LowLevel Input

2.0
3.0 to
0.50
VCC x 0.3
0.50
VCC x 0.3
V

5.5

VOH HighLevel Output Vin = VIH or VIL 2.0 1.9 2.0 1.9 V
Voltage IOH = 50 mA 3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4

Vin = VIH or VIL
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IOH = 4 mA 3.0 2.58 2.48

IOH = 8 mA 4.5 3.94 3.80

VOL

Voltage

LowLevel Output

Vin = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
V

Di n
Vin = VIH or VIL

IOL = 4 mA 3.0 0.36 0.44
4.5 0.36 0.44

IOL = 8 mA
lic l

Iin

Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 0.1 1.0 mA
ICC a

Quiescent Supply
Current

Vin = VCC or GND 5.5 2.0 20.0 mA

r

ad

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 55C to

TA = 25C +125C
ec

Symbol

tPLH,

Parameter

Propagation Delay, A or B to Y
Test Conditions
VCC = 3.3 0.3 V CL = 15 pF
Min Typ
7.0
Max
11.0
Min
1.0
Max
13.0
Unit
ns

tPHL CL = 50 pF 9.5 14.5 1.0 16.5

VCC = 5.0 0.5 V CL = 15 pF 4.8 6.8 1.0 8.0
CL = 50 pF 6.3 8.8 1.0 10.0

Cin

Input Capacitance
4 10 10 pF
El
Typical @ 25C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Note 1.) 18 pF

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
noload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0 V, Measured in SOIC Package)
TA = 25C
Symbol Characteristic Typ Max Unit

VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V
VOLV Quiet Output Minimum Dynamic VOL 0.3 0.8 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V
http://onsemi.com
3
MC74VHC86
Device Package Shipping
MC74VHC86DR2G SOIC14 2500 Tape & Reel
(PbFree)
MC74VHC86DTG TSSOP14 96 Units / Rail

(PbFree)
MC74VHC86DTR2G TSSOP14 2500 Tape & Reel

(PbFree)
a
MC74VHC86MELG SOEIAJ14 2000 Tape & Reel
(PbFree)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Ap git ic
TEST POINT
A or B VCC
50% OUTPUT
GND DEVICE
tPLH tPHL UNDER
Di n
TEST CL*
Y 50% VCC
lic l *Includes all probe and jig capacitance
a
a Figure 3. Switching Waveforms Figure 4. Test Circuit
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INPUT
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Figure 5. Input Equivalent Circuit
http://onsemi.com
4
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SDLS144C APRIL 1985 REVISED MAY 2010
D 3-State Outputs Drive Bus Lines or Buffer SN54LS, SN54S . . . J OR W PACKAGE

Memory Address Registers SN74LS240, SN74LS244 . . . DB, DW, N, OR NS PACKAGE
SN74LS241 . . . DW, N, OR NS PACKAGE
D PNP Inputs Reduce DC Loading SN74S . . . DW OR N PACKAGE
D Hysteresis at Inputs Improves Noise (TOP VIEW)
Margins
1G 1 20 VCC
1A1 2 19 2G/2G
description
2Y4 3 18 1Y1
a
These octal buffers and line drivers are designed 1A2 4 17 2A4
specifically to improve both the performance and 2Y3 5 16 1Y2
density of three-state memory address drivers, 1A3 6 15 2A3
Ap git ic
clock drivers, and bus-oriented receivers and 2Y2 7 14 1Y3
transmitters. The designer has a choice of 1A4 8 13 2A2
selected combinations of inverting and 2Y1 9 12 1Y4
noninverting outputs, symmetrical, active-low GND 10 11 2A1
output-control (G) inputs, and complementary
Di n
output-control (G and G) inputs. These devices 2G for LS241 and S241 or 2G for all other drivers.
feature high fan-out, improved fan-in, and 400-mV
noise margin. The SN74LS and SN74S devices
lic l can be used to drive terminated lines down to

133 .
SN54LS, SN54S . . . FK PACKAGE
(TOP VIEW)
a
a

2G/2G
VCC
2Y4
1A1
1G
r
ad 1A2 4
3 2 1 20 19
18 1Y1
t
2Y3 5 17 2A4
ec
1A3 6 16 1Y2
2Y2 7 15 2A3
1A4 8 14 1Y3
9 10 11 12 13
GND
2Y1
2A1
1Y4
2A2
2G for LS241 and S241 or 2G for all other drivers.

El
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

ORDERING INFORMATION{
TA PACKAGE} ORDERABLE PART NUMBER TOP-SIDE MARKING

SN74LS240N SN74LS240N
PDIP N Tube
SN74S240N SN74S240N
a
SN74S241N SN74S241N
SN74S244N SN74S244N
Tube SN74LS240DW
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LS240
Tape and reel SN74LS240DWR
Tube SN74LS241DW
LS241
Tube SN74LS244DW
LS244
Di n
0C to 70C Tape and reel SN74LS244DWR
SOIC DW
Tube SN74S240DW
S240
Tape and reel SN74S240DWR
lic l Tube SN74S241DW

S241
a
a Tube
Tape and reel
SN74S244DW
SN74S244DWR
S244
r
SN74LS240NSR 74LS240
ad SOP NS Tape and reel SN74LS241NSR 74LS241

t
SN74LS244NSR 74LS244
ec
SN74LS240DBR LS240
SSOP DB Tape and reel
SN74LS244DBR LS244
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
El

ORDERING INFORMATION{ (CONTINUED)
TA PACKAGE} ORDERABLE PART NUMBER TOP-SIDE MARKING

SN54LS240J SN54LS240J
SNJ54LS240J SNJ54LS240J
a
CDIP J Tube
SN54S240J SN54S240J
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SNJ54S240J SNJ54S240J
SN54S241J SN54S241J
SN54S244J SN54S244J
Di n
55C
55C to 125C
SNJ54LS240W SNJ54LS240W
lic l CFP W Tube

a
SNJ54S240W SNJ54S240W
a SNJ54S241W
SNJ54S244W
SNJ54S241W
SNJ54S244W
r
ad SNJ54LS241FK SNJ54LS241FK
t
LCCC FK Tube
ec
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
El

schematics of inputs and outputs

LS240, LS241, LS244 S240, S241, S244
EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT
VCC VCC
Req
a
9 k NOM
Input
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Input
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G and G inputs: Req = 2 k NOM
A inputs: Req = 2.8 k NOM
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a
a
r
TYPICAL OF ALL OUTPUTS
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VCC
R
ec
Output
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GND
LS240. LS241, LS244: R = 50 NOM

S240, S241, S244: R = 25 NOM

logic diagram
LS240, S240 LS241, S241
1
1G 1
1G
2 18
1A1 1Y1 2 18
1A1 1Y1
a
4 16
1A2 1Y2 16
4 1Y2
1A2
6 14
1A3 1Y3 6 14
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1A3 1Y3
8 12
1A4 1Y4 8 12
1A4 1Y4
19 19
2G 2G
Di n
11 9 11 9
2A1 2Y1 2A1 2Y1
lic l 2A2
13 7
2Y2 2A2
13 7
2Y2
a
a 2A3
15 5
2Y3 2A3
15 5
2Y3
r
ad 2A4
17 3
2Y4 2A4
17 3
2Y4
t
LS244, S244
ec
1
1G
2 18
1A1 1Y1
4 16
1A2 1Y2
El
6 14
1A3 1Y3
8 12
1A4 1Y4
19
2G
11 9
2A1 2Y1
13 7
2A2 2Y2
15 5
2A3 2Y3
17 3
2A4 2Y4
Pin numbers shown are for DB, DW, J, N, NS, and W packages.

Input voltage, VI: LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
a
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
Ap git ic
Di n
recommended operating conditions
SN54LS SN74LS
UNIT
lic l
VCC Supply voltage (see Note 1)
MIN
4.5
NOM
5
MAX
5.5
MIN
4.75
NOM
5
MAX
5.25 V
a
VIH
VIL
2
0.7
2
0.8
V
V
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NOTE 1: Voltage values are with respect to network ground terminal.

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otherwise noted)
SN54LS SN74LS
Hysteresis
VCC = MIN 0.2 0.4 0.2 0.4 V
(VT+ VT)
a
VCC = MIN,
VIH = 2 V, VIL = MAX, 2.4 3.4 2.4 3.4
IOH = 3 mA
VOH V
VCC = MIN,
VIH = 2 V, VIL = 0.5 V, 2 2
IOH = MAX
Ap git ic VCC = MIN, IOL = 12 mA 0.4 0.4

VOL VIH = 2 V
V, V
VIL = MAX IOL = 24 mA 0.5
VCC = MAX,
IOZH VIH = 2 V, VO = 2.7 V 20 20 A
VIL = MAX
Di n
VCC = MAX,
IOZL VIH = 2 V, VO = 0.4 V 20 20 A
VIL = MAX
II VCC = MAX, VI = 7 V 0.1 0.1 mA
lic l IIH VCC = MAX, VI = 2.7 V 20 20 A
a
IIL VCC = MAX, VIL = 0.4 V 0.2 0.2 mA
a
IOS VCC = MAX,
Outputs high All
40
17
225
27
40
17
225
27
mA
r
LS240 26 44 26 44
ad ICC
VCC = MAX,
MAX Outputs low
LS241, LS244 27 46 27 46 mA
t
Output open
LS240 29 50 29 50
Outputs disabled
ec
LS241, LS244 32 54 32 54
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

LS240 LS241, LS244
El

tPLH 9 14 12 18
RL = 667 ,
CL = 45 pF ns
tPHL 12 18 12 18
tPZL 20 30 20 30
RL = 667 ,
CL = 45 pF
F ns
tPZH 15 23 15 23
tPLZ 10 20 10 20
RL = 667 ,
CL = 5 pF ns
tPHZ 15 25 15 25


SN54S SN74S
UNIT
VCC Supply voltage (see Note 1) 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current
a
12 15 mA
External resistance between any input and VCC or ground 40 40 k
TA Operating free-air temperature (see Note 3) 55 125 0 70 C
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3. An SN54S241J operating at free-air temperature above 116C requires a heat sink that provides a thermal resistance from case
to free air, RCA, of not more that 40C/W.

Di n
otherwise noted)
SN54S SN74S
lic l VIK VCC = MIN, II = 18 mA 1.2 1.2 V
a
a
Hysteresis
(VT+ VT)
VCC = MIN 0.2 0.4 0.2 0.4 V
r
VCC = MIN VIH = 2 V, VIL = 0.8 V,
2.7
ad IOH = 1 mA
t
VCC = MIN, VIH = 2 V, VIL = 0.8 V,

VOH 2.4 3.4 2.4 3.4 V
IOH = 3 mA
ec

2 2
IOH = MAX
VOL 0.55 0.55 V
IOL = MAX
VCC = MAX, VIH = 2 V,
IOZH VO = 2.4 V 50 50 A
VIL = 0.8 V
VCC = MAX, VIH = 2 V,
IOZL VO = 0.5 V 50 50 A
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VIL = 0.8 V
IIH VCC = MAX, VI = 2.7 V 50 50 A
Any A 400 400 A
IIL MAX
VCC = MAX, VI = 0 5V
0.5
Any G 2 2 mA
IOS VCC = MAX 50 225 50 225 mA
S240 80 123 80 135
Outputs high
S241,S244 95 147 95 160
VCC = MAX, S240 100 145 100 150
ICC Outputs low mA
Output open S241, S244 120 170 120 180
S240 100 145 100 150
Outputs disabled
S241, S244 120 170 120 180
All typical values are at V
CC = 5 V, TA = 25C.
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.


S240 S241, S244
tPLH 4.5 7 6 9
RL = 90
, CL = 50 pF
F ns
tPHL 4.5 7 6 9
tPZL 10 15 10 15
RL = 90
, CL = 50 pF
F ns
tPZH 6.5 10 8 12
a
tPLZ 10 15 10 15
RL = 90
, CL = 5 pF ns
tPHZ 6 9 6 9
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VCC
Test RL
Test Point S1
Point VCC
From Output
a
RL CL
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CL Under Test Point
(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
1.3 V 1.3 V 1.3 V
lic l Pulse Input

0V
a
a
Low-Level
tw
Data
tsu
th
3V
r
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
ad 0V
t

ec
Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1
El
In-Phase 1.5 V
and D)
tPZH tPHZ
tPHL tPLH
VOH
VOH
1.3 V 1.3 V 1.5 V
(see Note D) and D)
VOL
F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 15 ns, tf 6 ns.
G. The outputs are measured one at a time with one input transition per measurement.


SERIES 54S/74S DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
RL
a
CL
CL Under Test Point
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(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
lic l th
0V
a
tw
a
Low-Level
1.5 V 1.5 V
Data
tsu
1.5 V 1.5 V
3V
r
Pulse Input
0V

t

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Output 3V
Control
3V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 1.5 V
In-Phase 1.5 V
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VOH (see Notes C

(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
1.5 V 1.5 V 1.5 V
(see Note D) and D)
VOL


APPLICATION INFORMATION
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SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
D 3-State Outputs Drive Bus Lines Directly SN54LS245 . . . J OR W PACKAGE
D PNP Inputs Reduce dc Loading on Bus

SN74LS245 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
Lines
D Hysteresis at Bus Inputs Improves Noise DIR 1 20 VCC
Margins A1 2 19 OE
D Typical Propagation Delay Times Port to A2 3 18 B1
Port, 8 ns A3 4 17 B2
a
A4 5 16 B3
IOL IOH A5 6 15 B4
TYPE (SINK (SOURCE A6 7 14 B5
CURRENT) CURRENT) A7 8 13 B6
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SN54LS245 12 mA 12 mA A8 9 12 B7
SN74LS245 24 mA 15 mA GND 10 11 B8
description SN54LS245 . . . FK PACKAGE

Di n
(TOP VIEW)
These octal bus transceivers are designed for
VCC
DIR
OE
asynchronous two-way communication between
A2
A1
data buses. The control-function implementation
lic l minimizes external timing requirements. 3 2 1 20 19
a
a A3 4 18 B1
The devices allow data transmission from the A4 5 17 B2
A bus to the B bus or from the B bus to the A bus, A5 6 16 B3
r
depending on the logic level at the A6 7 15 B4
ad direction-control (DIR) input. The output-enable A7 8 14 B5

t
(OE) input can disable the device so that the 9 10 11 12 13

buses are effectively isolated.
A8
B8
B7
B6
GND
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ORDERABLE TOP-SIDE
TA PACKAGE
PART NUMBER MARKING
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Tube SN74LS245DW
SOIC DW LS245
0C to 70C Tape and reel SN74LS245DWR
SSOP DB Tape and reel SN74LS245DBR LS245
Tube SN54LS245J SN54LS245J
CDIP J
Tube SNJ54LS245J SNJ54LS245J
55C to 125C
LCCC FK Tube SN54LS245FK
SN54LS245FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
a
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
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VCC VCC
9 k NOM 50 NOM
Di n
Input
Output
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a
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1
DIR
19
OE
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2
A1
18
B1
To Seven Other Channels

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, qJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
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NOTES: 1. All voltage values are with respect to GND.

Di n
SN54LS245 SN74LS245
UNIT
lic l
a
IOL
TA
a Low-level output current
Operating free-air temperature 55
12
125 0
24
70
mA
C
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otherwise noted)
SN54LS245 SN74LS245
VIK Input clamp voltage VCC = MIN, II = 18 mA 1.5 1.5 V
a
Hysteresis (VT+ VT) A or B VCC = MIN 0.2 0.4 0.2 0.4 V
VCC = MIN, IOH = 3 mA 2.4 3.4 2.4 3.4
VOH High level output voltage
High-level VIH = 2 V,
V V
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VIL = VIL(max) IOH = MAX 2 2
VCC = MIN, IOL = 12 mA 0.4 0.4

VOL Low level output voltage
Low-level VIH = 2 V,
V V
VIL = VIL(max) IOL = 24 mA 0.5
Off-state output current, VCC = MAX,
A
Di n
IOZH VO = 2.7 V 20 20
high-level voltage applied OE at 2 V
Off-state output current, VCC = MAX,
IOZL VO = 0.4 V 200 200 A
low-level voltage applied OE at 2 V
lic l
II
Input current at
maximum input
A or B
VCC = MAX
VI = 5.5 V 0.1 0.1
mA
a
IIH
a voltage DIR or OE
High-level input current VCC = MAX,
VI = 7 V
VIH = 2.7 V
0.1
20
0.1
20 A
r
IIL Low-level input current VCC = MAX, VIL = 0.4 V 0.2 0.2 mA
ad
IOS Short-circuit output current VCC = MAX 40 225 40 225 mA
t
Total, outputs high 48 70 48 70

ICC Supply current Total, outputs low VCC = MAX Outputs open 62 90 62 90 mA
ec
Outputs at high Z 64 95 64 95
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH Propagation delay time, low- to high-level output 8 12
pF
CL = 45 pF, RL = 667 W ns
tPHL Propagation delay time,
time high-
high to low-level
low level output 8 12
tPZL Output enable time to low level 27 40
CL = 45 pF
pF, RL = 667 W ns
tPZH Output enable time to high level 25 40
tPLZ Output disable time from low level 15 25
CL = 5 pF
pF, RL = 667 W ns
tPHZ Output disable time from high level 15 28


VCC
Test RL
Test Point S1
Point VCC
From Output
a
RL CL
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CL Under Test Point
(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
1.3 V 1.3 V 1.3 V
lic l Pulse Input

0V
a
a
Low-Level
tw
Data
tsu
th
3V
r
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
ad 0V
t

ec
Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 1.5 V
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In-Phase VOH 1.3 V

(see Notes C
and D)
tPZH tPHZ
tPHL tPLH
VOH
VOH
(see Notes C 1.3 V
Output 1.3 V 1.3 V
and D) 1.5 V
(see Note D) VOL

a
3.1.- Decodificador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2
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3.2.- Selector/multiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3
3.3.- Referencias del captulo 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5
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V1.0 3.1

Un circuito combinacional es aquel en el que el estado de sus salidas depende
nicamente del estado de sus entradas y sus combinaciones. Todos los elementos
bsicos vistos en el apartado anterior entran dentro de este grupo de dispositivos.
a
La forma de identificar un circuito combinacional es por medio de su nombre (si
es un circuito tpico) o por medio de su tabla de verdad. Tambin es posible hacerlo por
medio de su cronograma, pero no es lo ms habitual.
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Hay una coleccin de circuitos tpicos que se utilizan habitualmente y que se
identifican simplemente por medio de su nombre. A continuacin vemos algunos de
ellos. En muchos casos hacemos uso de modelos industriales reales cuya
Di n
documentacin se adjunta para contrastar los detalles.
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a
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3.1.- Decodificador
Un decodificador es un circuito combinacional que sirve para identificar un cdigo
r
ad
o para identificar un valor numrico. La figura 3.1 muestra el esquema lgico de un
t
decodificador comercial (74 LS138) que se denomina decodificador 3 a 8 porque

dispone de tres entradas y ocho salidas y su funcionamiento es de tal forma que para
ec
cada una de las 8 posibles combinaciones de las seales binarias de entrada (23 =8),
se activa una y solo una seal de salida. La figura 3.2 es la tabla de verdad
correspondiente al esquema de la figura 3.1.
El

del circuito 74LS138.
Como puede verse en la figura 3.1, el dispositivo tiene en total seis seales de
entrada, tres de ellas se denominan E (Enable, /E1, /E2 y E3), las otras tres seales se
denominan A (A0, A1 y A2). Las entradas E son las de habilitacin y sirven para
controlar el funcionamiento del dispositivo. Funcionan de forma que si no tienen el
V1.0 3.2
estado especificado en la tabla de verdad, el circuito no produce ninguna salida. Esto

corresponde a las tres primeras filas de la tabla. Cuando estas seales tienen el estado
/E1 = L, /E2 = L y E3 = H, el circuito funciona como se describe en la tabla, haciendo que
una de las 8 salidas se active segn sea la combinacin de los estados de las seales
A. Observar que la activacin de las seales de salida es a nivel bajo.
a
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Di n
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Figura 3.2. Tabla de verdad del circuito 74LS138.
a
a
Este dispositivo realiza una decodificacin de un cdigo octal en representacin
binaria a octal en representacin decimal.
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ad
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3.2.- Selector/multiplexor
Como su nombre indica, un selector es un circuito que permite seleccionar entre
varias opciones. En nuestro caso permite seleccionar entre varias seales, es decir
El
dispone de varias seales de entradas entre las cuales seleccionamos una para que
sea igual que la salida. La figura 3.3 muestra el esquema digital de un selector de dos
entradas y una salida y su smbolo.
C S
0 E0
1 E1
Figura 3.3. Selector/multiplexor de 2 a 1, smbolo y tabla

de verdad
La tabla de verdad de este dispositivo es la mostrada en la tabla de la figura 3.3.

La seal de control C nos permite hacer que a la salida S tengamos la seal E0
o la seal E1. Esto es lo que se ha representado en el cronograma de la figura 3.4.
V1.0 3.3
Figura 3.4.
Cronograma ejemplo
de funcionamiento de
un selector 2-1.
a
La figura 3.5 muestra el esquema lgico y el smbolo de un selector 4-1. En este
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caso disponemos de dos seales de control cuyas combinaciones binarias realizan la
seleccin de la seal de entrada a la salida. La tabla de verdad que describe su
funcionamiento es:
Di n
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C1 C0 Salida
H
H
a L
H
E0
E1
r
L L E2
ad
L H E3
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Figura 3.5. Selector/multiplexor de 4 a 1. Tabla de verdad,

esquema y smbolo.
La referencia DM74150 es un selector/multiplexor de 16 entradas, para lo cual son

necesarias 4 seales de control.
El
V1.0 3.4
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V1.0 3.5
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Di n r
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ad
a
El
ec
t
Di n r
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lic l a a
ad
a
El
ec
t
Di n r
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lic l a a
ad
a
El
ec
t
Di n r
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ad
a
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ec
t
Di n r
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ad
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Di n r
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DM74150, DM74151A Data Selectors/Multiplexers
March 1998
DM74150, DM74151A
a
Data Selectors/Multiplexers
General Description Features
These data selectors/multiplexers contain full on-chip decod- n 150 selects one-of-sixteen data lines
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ing to select the desired data source. The 150 selects n 151A selects one-of-eight data lines
one-of-sixteen data sources; the 151A selects one-of-eight n Performs parallel-to-serial conversion
data sources. The 150 and 151A have a strobe input which n Permits multiplexing from N lines to one line
must be at a low logic level to enable these devices. A high n Also for use as Boolean function generator
level at the strobe forces the W output high and the Y output
n Typical average propagation delay time, data input to W
(as applicable) low.
output
Di n
The 151A features complementary W and Y outputs, 150 11 ns
whereas the 150 has an inverted (W) output only. 151A 9 ns
The 151A incorporates address buffers which have sym- n Typical power dissipation
metrical propagation delay times through the complementary 150 200 mW
paths. This reduces the possibility of transients occurring at 151A 135 mW
lic l
the output(s) due to changes made at the select inputs, even n Alternate Military/Aerospace device (54150, 54151A) is
a
when the 151A outputs are enabled (i.e., strobe low).
a available. Contact a Fairchild Semiconductor Sales
Office/Distributor for specifications.
r
Connection Diagrams
ad
t
Dual-In-Line Package Dual-In-Line Package

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DS006546-1 DS006546-2
Order Number 54150DQMB, 54150FMQB, Order Number 54151ADMQB, 54151AFMQB,

DM54150J or DM74150N DM54151AJ, DM54151AW or DM74151AN
See Package Number J24A, N24A or W24C See Package Number J16A, N16E or W16A
1998 Fairchild Semiconductor Corporation DS006546 www.fairchildsemi.com

Absolute Maximum Ratings (Note 1) DM54 and 54 55C to +125C
DM74 0C to +70C
Supply Voltage 7V
Storage Temperature Range 65C to +150C
Input Voltage 5.5V
Operating Free Air Temperature Range
a
Recommended Operating Conditions
Symbol Parameter DM54150 DM74150 Units
Min Nom Max Min Nom Max
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VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current 0.8 0.8 mA
IOL Low Level Output Current 16 16 mA
Di n
TA Free Air Operating Temperature 55 125 0 70 C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings. The Recommended Operating
Conditions table will define the conditions for actual device operation.
lic l 150 Electrical Characteristics
a
aover recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ
(Note 2)
Max Units
r
VI Input Clamp Voltage VCC = Min, II = 12 mA 1.5 V
ad
VOH High Level Output VCC = Min, IOH = Max 2.4 V
t
Voltage VIL = Max, VIH = Min

VOL Low Level Output VCC = Min, IOL = Max 0.4 V
ec
Voltage VIH = Min, VIL = Max

II Input Current @ Max VCC = Max, VI = 5.5V 1 mA
Input Voltage
IIH High Level Input Current VCC = Max, VI = 2.4V 40 A
IIL Low Level Input Current VCC = Max, VI = 0.4V 1.6 mA
IOS Short Circuit VCC = Max DM54 20 55 mA
Output Current (Note 3) DM74 18 55
ICC Supply Current VCC = Max, (Note 4) 40 68 mA
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Note 2: All typicals are at VCC = 5V, TA = 25C.

Note 3: Not more than one output should be shorted at a time.
Note 4: ICC is measured with the strobe and data select inputs at 4.5V, all other inputs and outputs open.
www.fairchildsemi.com 2
150 Switching Characteristics
at VCC = 5V and TA = 25C
Symbol Parameter From (Input) RL = 400, CL = 15 pF Units
To (Output) Min Max
tPLH Propagation Delay Time Select 35 ns
a
Low to High Level Output to W
tPHL Propagation Delay Time Select 33 ns
High to Low Level Output to W
tPLH Propagation Delay Time Strobe 24 ns
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tPHL Propagation Delay Time Strobe 30 ns
tPLH Propagation Delay Time E0-E15 20 ns
Di n
tPHL Propagation Delay Time E0-E15 14 ns
Recommended Operating Conditions
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Symbol Parameter DM54151A DM74151A Units
a
VCC
VIH
a Supply Voltage
High Level Input Voltage
Min
4.5
2
Nom
5
Max
5.5
Min
4.75
2
Nom
5
Max
5.25 V
V
r
VIL Low Level Input Voltage 0.8 0.8 V
IOH
ad High Level Output Current 0.8 0.8 mA

t
IOL Low Level Output Current 16 16 mA

TA Free Air Operating Temperature 55 125 0 70 C
ec
151A Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 5)
VI Input Clamp Voltage VCC = Min, II = 12 mA 1.5 V
VOH High Level Output VCC = Min, IOH = Max 2.4 V
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Voltage VIL = Max, VIH = Min

VOL Low Level Output VCC = Min, IOL = Max 0.4 V
Voltage VIH = Min, VIL = Max
II Input Current @ Max VCC = Max, VI = 5.5V 1 mA
Input Voltage
IIH High Level Input Current VCC = Max, VI = 2.4V 40 A
IIL Low Level Input Current VCC = Max, VI = 0.4V 1.6 mA
IOS Short Circuit VCC = Max DM54 20 55 mA
Output Current (Note 6) DM74 18 55
ICC Supply Current VCC = Max, (Note 7) 27 48 mA
Note 5: All typicals are at VCC = 5V, TA = 25C.
Note 6: Not more than one output should be shorted at a time.
Note 7: ICC is measured with the strobe and data select inputs at 4.5V, all other inputs and outputs open.
3 www.fairchildsemi.com
151A Switching Characteristics
at VCC = 5V and TA = 25C
Symbol Parameter From (Input) RL = 400, CL = 15 pF Units
To (Output) Min Max
a
Low to High Level Output (4 Levels) to Y
High to Low Level Output (4 Levels) to Y
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Low to High Level Output (3 Levels) to W
High to Low Level Output (3 Levels) to W
Low to High Level Output to Y
Di n
tPHL Propagation Delay Time Strobe 30 ns
High to Low Level Output to Y
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tPHL Propagation Delay Time
High to Low Level Output
Strobe
to W
25 ns
a
tPLHa Propagation Delay Time
Low to High Level Output
D0-D7
to Y
24 ns
r
tPHL Propagation Delay Time D0-D7 24 ns
ad
tPLH
High to Low Level Output
Propagation Delay Time
to Y
D0-D7 14 ns
t

tPHL Propagation Delay Time D0-D7 14 ns
ec

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Logic Diagrams
150
a
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DS006546-3
Logic Diagrams
151A
a
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DS006546-4
See Address Buffers Below
Address Buffers for

54151A/74151A
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DS006546-5
Function Tables
54150/74150
Inputs Outputs
Select Strobe W
a
D C B A S
X X X X H H
L L L L L E0
L L L H L E1
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L L H L L E2
L L H H L E3
L H L L L E4
L H L H L E5
L H H L L E6
Di n
L H H H L E7
H L L L L E8
H L L H L E9
lic l H
H
L
L
H
H H
L L
L
E10
E11
a
a H
H
H
H
H
H H
L
L H
L
L
L
L
L
E12
E13
E14
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H H H H L E15
ad H = High Level, L = Low Level, X = Dont Care

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E0 , E1 E15 = the complement of the level of the respective E input

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54151A/75151A
Inputs Outputs
Select Strobe Y W
C B A S
X X X H L H
L L L L D0 D0
L L H L D1 D1
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L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
H = High Level, L = Low Level, X = Dont Care
D0, D1D7 = the level of the respective D input
Captulo 4.- Dispositivos Secuenciales
a
4.1.- Elemento de memoria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2
4.1.1.- Tipos de biestables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2
Ap git ic
4.2.- Contadores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4
4.3.- Temporizador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.5.- Registros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
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4.5.1.- Tipos de registros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.6.- Referencias del captulo 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18
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V1.0 4.1
Captulo 4.- Dispositivos Secuenciales

Un circuito secuencial es aquel en el que sus salidas son consecuencia de las
seales de entrada y/o de la historia anterior de stas. Para que esto pueda ser
posible, el circuito tiene que recordar lo que ha sucedido anteriormente. Por eso
a
empezamos repasando los elementos de memoria.
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4.1.- Elemento de memoria
En Electrnica Digital, un elemento de memoria es un circuito que es capaz de
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mantener informacin digital permanentemente a lo largo del tiempo. En Electrnica
Analgica, esto se logra utilizando condensadores ideales en los que depositamos una
carga elctrica y all se queda mientras no actuemos sobre ella para cambiarla. Por
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desgracia el condensador ideal no existe (como corresponde a su nombre) por lo que
a
a
este tipo de memoria analgica tiene una duracin muy limitada en el tiempo.
Sin embargo, utilizando tcnicas de conmutacin (tcnicas digitales un nuestro
r
caso) s es posible disponer de elementos capaces de mantener la informacin. Son
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los denominados biestables.
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4.1.1.- Tipos de biestables

En los libros de teora nos encontramos con muchos tipos de biestables. En la
industria electrnica el nmero diferentes de biestables se reduce mucho respecto a
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la teora. Por ltimo, nosotros utilizamos intensamente un solo tipo de biestables

aunque en este documento hablaremos de tres, el tipo RS, como el ms bsico y el
biestable tipo D y el tipo JK.
Biestable tipo RS: La figura 4.1a muestra la circuitera lgica de un biestable RS

construido con puertas NOR. Las salidas del circuito se mantienen en los niveles
correspondientes hasta que se modifica la combinacin de las seales de
entrada. En la figura se ha includo la tabla de verdad que define el
funcionamiento de este biestable. La figura 4.1b muestra el esquema de un
biestable RS NAND y su tabla de verdad.
V1.0 4.2
Figura 4.1a. Esquema de un biestable RS NOR y su tabla de verdad.
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Figura 4.1b. Esquema de un biestable RS NAND y su tabla de verdad.
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Biestable tipo D: Este es un biestable que no funciona como el anterior
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cambiando dos seales de entrada sino que su funcionamiento se basa en el
ad
flanco de una seal de control que se denomina reloj (clock). En la tabla de
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verdad que define su funcionamiento y que se ha incluido en la figura 4.2a,

podemos ver que mientras que la seal se reloj se mantiene a nivel alto (H), a
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nivel bajo (L) o si hay un cambio de alto a bajo (), la salida del biestable no
cambia respecto a su estado anterior (Qn = Qn-1). Solamente cuando existe un
flanco ascendente en la seal CK () la salida toma el mismo estado que la
entrada D. En esta situacin se dice que en Q se copia el estado de la entrada D.
El
Figura 4.2a. Tabla de verdad

de un biestable D.
Es decir, que con el flanco ascendente de la seal CK el estado de la

entrada D se almacena en este dispositivo hasta el prximo flanco ascendente el
CK. Por lo tanto, el biestable es una memoria digital de un bit.
La figura 4.2b muestra el esquema digital de un biestable D con entrada de
activacin (preset, /PRE) y borrado (clear, /CLR).
V1.0 4.3
La figura 4.3 muestra el esquema elctrico de un biestable D. Como puede

verse en esta figura, la complejidad del circuito es elevada, por lo que suele ser
habitual no utilizar el circuito elctrico (con transistores, resistencias, etc.) sino el
esquema digital o su smbolo, como en la figura 4.2b.
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Figura 4.2b. Esquema digital de
un biestable D.
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Figura 4.3. Esquema elctrico (electrnico) de un biestable tipo D.
V1.0 4.4
No es frecuente almacenar un solo bit de informacin digital, es poco

prctico, por eso se construyen asociaciones de biestables que junto con circuitos
combinacionales forman los circuitos secuenciales y memorias.
La referencia 74LS74 es un dispositivo que contiene dos biestables D como
los descritos en los prrafos anteriores.
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Biestable tipo JK: Un biestable tipo JK tiene un smbolo como el que se muestra
en la figura 4.4 junto a su tabla de verdad.
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La referencia 74LS76 es un dispositivo que contiene dos biestables tipo JK
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como los descritos en los prrafos anteriores.
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4.2.- Contadores
Los contadores junto con los registros son los elementos ms utilizados en
electrnica digital avanzada. Los contadores son estructuras que agrupan de formas
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diferentes biestables y circuitos combinacionales para obtener una determinada

funcionalidad. No nos introducimos en su diseo, sino que describimos su circuitera
y su funcionamiento.
Contador binario en cascada de 4 bits: Se denomina as a la estructura

representada en la figura 4.5 a). En ella podemos ver 4 biestables D conectados
en serie. Esta es la estructura ms simple para un contador binario y su
cronograma de funcionamiento lo tenemos en la figura 4.5 b).
V1.0 4.5
a
de un contador binario.
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En el cronograma (figura 4.5 b), podemos ver que las combinaciones de las
a
salidas Q3-Q0 van contando en binario desde 0000 hasta 1111, o lo que es lo
mismo, desde 0 hasta 15 en decimal.
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adEsta estructura de contador tambin se denomina ripple y asncrono ya que
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cada biestable acta despus de hacerlo el anterior, no a la vez.

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Ver la referencia 74HVC393.
Contador binario sncrono de 4 bits: Esta es una estructura diferente a la

anterior en cuanto que todos los biestables evolucionan sncronamente con la
seal del reloj. El modelo comercial 74LS161 es un ejemplo de esta estructura y
El
es el que se ha representado en la figura 4.6.

Los contadores no tiene porque contar siempre por un nmero que sea
potencia de 2, Aadiendo algo de circuitera podemos contar por cualquier
nmero entero entre 0 y 2n, siendo n el n de biestables en el contador. De hecho
el modelo citado es programable en la cuenta desde 1 hasta 15. La figura xx
muestra el cronograma de funcionamiento de este contador. Este modelo de
contador es adems programable, es decir que se le puede utilizar para contar
el nmero que queremos. Esto es lo que describe en el cronograma de la figura
4.7. Dado que el contador cuenta de 0 a 15 (decimal) si se quiere que la cuenta
sea solamente por tres, le cargamos un valor 12 (1100 en binario). La salida RCO
del contador se pone a nivel alto durante un periodo de la seal de reloj cuando
llega al final de la cuenta, indicando con ello esta situacin. Hay que tener
presente, como describe el cronograma, que el contador, una vez que llega a 15,
pasa al valor cero y contina contando ce nuevo hacia 15. Es decir que si
queremos que solo cuente tres en cada ocasin hay que volver a cargar el valor
1100 a su entrada cada vez que termina la cuenta.
V1.0 4.6
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digital del contador
binario 74LS161.
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Contador hacia adelante (up): Los casos vistos anteriormente son contadores
adelante, la evolucin de la cuenta va de 0 a 2n -1, siendo n el n de biestables
utilizados para la cuenta.
Contador hacia atrs (down): Los contadores atrs realizan la cuanta desde el
valor superior hacia cero. En determinados casos esto es interesante y con
frecuencia nos encontramos con contadores que permiten cuenta hacia adelante
y hacia atrs. La figura 4.8 muestra el esquema digital del modelo 74LS191 que
es un contador binario de 4 bits, up-down, programable y sncrono.
V1.0 4.7
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Figura 4.7. Cronograma funcional del dispositivo 74LS161.
La seal de control D/U (figura 4.8) es la que permite seleccionar la forma

de conteo de este dispositivo: D/U = H cuenta hacia adelante (up); D/U = L
cuenta hacia atrs (down).
La figura 4.9 muestra el cronograma que define el funcionamiento de este
contador.
Como puede comprobarse en los ltimos dispositivos que hemos
descrito, si no disponemos del cronograma, es muy difcil saber cmo funciona.
De ah la importancia de estos grficos.
V1.0 4.8
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Figura 4.8. Esquema digital del contador up-down 74LS191.
Dada la complejidad que tienen estos dispositivos, no es prctico

representarlos segn la figura 4.8. Lo ms utilizado es una representacin mucho
ms simple como se muestra en la figura 4.10, en donde el dispositivo se
representa por medio de un simple rectngulo al que se aade por el lado
izquierdo las seales de entrada y por el lado derecho las seales de salida y,
muy importante, un texto indicando el modelo del dispositivo.
Adems, en el smbolo se ha de indicar los nombres de todas las seales
segn las describe el fabricante y el nmero de la patilla a la que est conectada
cada seal.
V1.0 4.9
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Figura 4.9. Cronograma de funcionamiento del dispositivo 74LS191.

Figura 4.10.
Smbolo
simplificado
del dispositivo
74LS191
V1.0 4.10
4.3.- Temporizador
Cuando la seal de entrada a un contador es una seal de periodo constante sus
salidas nos est indicando intervalos de tiempo que son mltiplos del periodo de la
seal de entrada. Por eso, un temporizador no es ms que un contador utilizado para
contar periodos de la seal. Si por ejemplo, la seal del reloj es de 1 MHz (periodo de
1 :s), un contador de 32 bits (32 biestables) puede contar hasta 232 :s, es decir
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4.294.967.296 :s = 136,19 aos.
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4.4.- Divisor de frecuencia
De forma similar a lo descrito en el apartado anterior, si la seal de entrada a un
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contador es peridica de periodo T ,cada una de las salidas de los biestables nos da
una seal peridica de periodo 2T, 4T, 8T, 16T, etc. Es decir, un divisor digital de
frecuencia es un contador del cual utilizamos determinadas salidas cuando su entrada
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es peridica.
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4.5.- Registros
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Los registros son estructuras basadas en biestables como los contadores pero
diferentes de stos en su conexionado y en su funcionalidad.
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4.5.1.- Tipos de registros

Dependiendo de como se conectan los biestables que forman un registro se
obtienen distintas funciones. Estas funciones son las que definen los tipos de registros
que presentamos a continuacin.
Entrada paralelo - salida paralelo: Son registros a los que se accede con n bits
en paralelo y se obtienen los mismos n bits en paralelo. Este tipo de registro se
utiliza para almacenar informacin (tpicamente 8 bits). El modelo comercial de
referencia es el 74LS374. La figura 4.11 representa el esquema digital de este
registro. En esta figura podemos ver que hay dos modelos (74LS373 y 74LS374)
que se diferencian en que el primero es un registro transparente y es segundo
funciona por flanco de la seal reloj (CLK). La figura 4.12 muestra la tabla de
verdad de ambos registros. Ambos modelos tienen salida triestado y tienen una
alta capacidad de corriente de salida (24 mA). En SBM se utiliza mucho el modelo
74LS374. Ver la referencia 74LS374. Este tipo de registro es el que forma las
V1.0 4.11
clulas de una memoria RAM, como se ver en el captulo dedicado a estos

dispositivos.
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Figura 4.11. Esquema digital de los registros 74LS373 y 74LS374.
Figura 4.12. Tablas funcionales de los registros de

la figura 4.11.
V1.0 4.12
Registros de desplazamiento: Se denominan as los registros que permiten

cambiar la posicin relativa de los bits de un dato de ms de un bit. Se trata de
un conjunto de biestables conectados de serie y con la seal de reloj es comn
a todos ellos. La imagen ms clsica de ete tipo de conexin es la que se muestra
en la figura 4.13. En ella podemos ver que
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Figura 4.13. Esquema bsico de un registro de desplazamiento de 4

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bits y cronograma de funcionamiento.
En ella podemos ver que si suponemos que partimos del estado L en todos
los biestables, la informacin binaria introducida por Di para por todos los
biestables del registro produciendo las correspondientes salidas en Q0 - Q3. Los
distintos instante del funcionamiento segn el cronograma (a - h) quedan
delimitados por los flancos de subida de la seal de reloj porque se han utilizado
biestables tipo D por flanco de subida.
Observando los contenidos de los biestables, podemos ver que cada uno de
ellos contiene la informacin de la entrada pero en distintos instantes de tiempo
marcados por la seal CK. Este desplazamiento de la informacin binaria de un
biestable a otro es lo que da nombre a este tipo de registro.
V1.0 4.13
Entrada serie - salida paralelo: Cuando utilizamos un registro de

desplazamiento para almacenar informacin, la entrada de la informacin binaria
puede hacerse en serie como se muestra en la figura 4.13. Si disponemos de la
salida de cada uno de los biestables, se dice que la salida del registro es en
paralelo (figura 4.13). El modelo comercial 74VHC164 es un ejemplo de este tipo
de registro de desplazamiento. La figura 4.14 muestra el esquema digital de este
dispositivo. La figura 4.15 contiene la tabla de verdad que define el
a
funcionamiento de la figura 4.14.
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Figura 4.14
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Figura 4.15. Tabla de verdad

del esquema de la figura 4.14.
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Entrada serie - salida serie: Si en la figura 5.13 slo disponemos de la salida de

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un biestable (el ltimo de la derecha) el registro se dice que es de entrada en

serie y salida en serie.
Entrada paralelo - salida paralelo: Tambin es posible introducir la informacin

binaria en paralelo en cada uno de los biestables. Si adems las salidas de los
biestables estn accesibles, entonces el registro de desplazamiento es de entrada
en paralelo y salida en paralelo. Prestar atencin para no confundir con el modelo
74LS374 que es un registro de entrada en paralelo y salida en paralelo pero NO
es un registro de desplazamiento y, por lo tanto su funcionamiento es totalmente
diferente. La figura 4.16 muestra el esquema digital del modelo comercial
74HC299 que es un registro de desplazamiento de entrada y salida en paralelo.
En este caso y con el objeto de reducir el nmero de patillas del dispositivo, el
fabricante ha utilizado las mismas patillas para la informacin de entrada y de
salida. Por medio de las seales de control de salida /OE1 y /OE2 podemos hacer
que las patillas I/O7 a I/O0 sean entradas o salidas del registro. Esto es bastante
V1.0 4.14
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digital del registro de

desplazamiento
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74HC299.
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V1.0 4.15
razonable ya mientras escribimos la informacin binaria en el registro no

necesitamos disponer de las seales de salida ya que son iguales a las seales
de entrada. De esta forma el dispositivo necesita ocho patillas menos que si las
entradas y salidas son totalmente independientes.
Entrada paralelo - salida serie: Si en el dispositivos de la figura 5.13 utilizamos
a
una sola patilla de salida, decimos que tenemos la salida del registro en serie. El
modelo comercial 74LS165 (ver referencia) es un registro de desplazamiento de
ocho bits con entrada en paralelo y salida exclusivamente en serie (por el ltimo
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biestable).
Recirculacin: Este es un caso para los registros de desplazamiento de entrada

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serie y salida serie en el que el dato de salida en serie se conecta al dato de
entrada en serie. En esta situacin, una vez cargado el dato, cada flanco de reloj
cambia la posicin de los bits pero no desaparece la informacin del registro. As
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si el registro de es 8 bits, lada 8 flancos de reloj tenemos la misma informacin
a
en el mismo orden en el que se introdujo. Es decir que la informacin recircula
a
una y otra vez hasta que decidamos cambiarla.
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Tipos de desplazamientos: Hasta ahora se ha visto el desplazamiento que se

denomina a la izquierda en el que cada desplazamiento hace que cada bit de la
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informacin existente en el registro pase a una posicin de mayor peso numrico

(bit0 pasa a bit1, bit1 pasa a bit2, etc.)1. Sin embargo en muchas ocasiones
necesitamos realizar desplazamiento a la derecha. Esto se consigue cambiando
el orden de las conexiones de los biestable.
El
Tipos de rotaciones: Similar a lo dicho para los tipos de desplazamiento.
Otras opciones: Cabe pensar en dispositivos que permitan rotaciones y

desplazamientos a derecha e izquierda seleccionable por medio de seales de
control. Esto es lo que encontramos en la ULA de los :P.
Propiedades de los desplazamientos: Entre las propiedades de los

desplazamientos lgicos tenemos dos muy importantes:
Multiplicacin y divisin por 2. Un desplazamiento a izquierda de una
informacin numrica significa matemticamente una multiplicacin del
1
Prestar atencin a que en la representacin grfica aparece un desplazamiento a la
derecha debido al orden en el que se han representado de los biestables.
V1.0 4.16
valor numrico por la base. En el caso de un nmero binario es una

multiplicacin por 2. As, si al nmero binario 01000100 (68) le aplicamos
un desplazamiento a la izquierda pasa a ser 10001000 (136) de valor
doble al primero. Por otro lado, un desplazamiento a la derecha significa
una divisin por la base del valor numrico, 2 en el caso binario2. El
nmero binario 01010110 (86) para a ser 00101011 (43) al aplicarle un
desplazamiento a la derecha. De forma similar, dos desplazamientos
a
equivale a multiplicar o dividir por 4, etc.
Generacin de seales con forma especfica. Tanto los desplazamiento
con rotacin como sin ella, las salidas de los registros de desplazamiento
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nos permiten construir forma de onda digitales especficas combinando
la informacin del registro, la recirculacin o no y los flancos de reloj.
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2
Hay que tener presente que si el nmero es impar la divisin tendr un resto y esta
operacin de desplazamiento no lo tiene en cuenta.
V1.0 4.17
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V1.0 4.18
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V1.0 4.19

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!" # $%&" !# '%()$!" *!"& Copyright 1988, Texas Instruments Incorporated
*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"#
#"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&
"&#"/ !)) '!!&"&#

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SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
a
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level DUAL JK FLIP-FLOP
of the J and K inputs will perform according to the Truth Table as long as mini- WITH SET AND CLEAR
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions. LOW POWER SCHOTTKY
Ap git ic J SUFFIX
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OPERATING MODE
MODE SELECT TRUTH TABLE
INPUTS OUTPUTS 16
CERAMIC
CASE 620-09
1
SD CD J K Q Q
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Set L H X X H L
a
Toggle
a
Reset (Clear)
*Undetermined
H
L
H
L
L
H
X
X
h
X
X
h
L
H
q
H
H
q
N SUFFIX
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PLASTIC
Load 0 (Reset) H H l h L H
ad
16 CASE 648-08
Load 1 (Set) H H h l H L
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Hold H H l l q q 1
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
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if SD and CD go HIGH simultaneously.

H,h = HIGH Voltage Level D SUFFIX
L,l = LOW Voltage Level
SOIC
X = Immaterial 16
1 CASE 751B-03
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
El
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC DIAGRAM
LOGIC SYMBOL
Q 2 7
Q
SD 15 SD 11
16 K Q 12 K Q
1 CP 6 CP
CLEAR (CD) SET (SD)
K 4 J C Q 14 9 J C Q 10
J D D
3 8
CLOCK (CP) VCC = PIN 5
GND = PIN 13
FAST AND LS TTL DATA

5-1
SN54/74LS76A
GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 55 25 125 C
74 0 25 70
IOH Output Current High 54, 74 0.4 mA
a
IOL Output Current Low 54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Ap git ic
Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
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Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
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VIL Input LOW Voltage
54
74
0.7
0.8
V
Guaranteed Input
All Inputs
p LOW Voltage
g for
lic l
VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA
a
VOH
a Output HIGH Voltage

54
74
2.5
2.7
3.5
3.5
V
V
VCC = MIN,, IOH = MAX,, VIN = VIH
or VIL per Truth Table
r
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
ad
VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table
t
J, K 20
A
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Clear 60 VCC = MAX, VIN = 2.7 V

Clock 80
IIH Input HIGH Current
J, K 0.1
Clear 0.3 mA VCC = MAX, VIN = 7.0 V
Clock 0.4
J, K 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
Clear, Clock 0.8
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IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX

ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 30 45 MHz
VCC = 5.0
50V
tPLH 15 20 ns
Clock Clear
Clock, Clear, Set to Output CL = 15 pF
tPHL 15 20 ns
AC SETUP REQUIREMENTS (TA = 25C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tW Clock Pulse Width High 20 ns
tW Clear Set Pulse Width 25 ns
VCC = 5
5.0
0V
ts Setup Time 20 ns
th Hold Time 0 ns
FAST AND LS TTL DATA

5-2
74VHC393 Dual 4-Bit Binary Counter
December 2007
74VHC393
Dual 4-Bit Binary Counter
a
Features General Description
High Speed: fMAX = 170MHz (Typ.) at TA = 25C The VHC393 is an advanced high speed CMOS 4-bit
Ap git ic
Low power dissipation: ICC = 4A (Max.) at TA = 25C Binary Counter fabricated with silicon gate CMOS tech-
High noise immunity: VNIH = VNIL = 28% VCC (Min.) nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
Power down protection is provided on all inputs
CMOS low power dissipation. It contains two indepen-
Pin and function compatible with 74HC393 dent counter circuits in one package, so that counting or
Di n
frequency division of 8 binary bits can be achieved with
one IC. This device changes state on the negative going
transition of the CLOCK pulse. The counter can be reset
to 0 (Q0Q3 = L) by a HIGH at the CLEAR input
lic l regardless of other inputs.
a
a An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
r
systems and two supply systems such as battery back
ad up. This circuit prevents device destruction due to mis-

t
matched supply and input voltages.

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Ordering Information
Package
Order Number Number Package Description
74VHC393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
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74VHC393SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC393MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1998 Fairchild Semiconductor Corporation www.fairchildsemi.com

74VHC393 Rev. 1.5.0
Connection Diagram Logic Symbol/s
IEEE/IEC
a
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Pin Descriptions
Pin Names Description
Truth Table
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CLR1, CLR2 Clear Inputs Inputs Outputs
CP1, CP2 Clock Pulse Inputs CP CLR QA QB QC QD
X H L L L L
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QA, QB, QC, QD Outputs
a
L Count Up
a L No Change
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X: Dont Care
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t
System Diagram
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74VHC393 Rev. 1.5.0 2
Timing Chart
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74VHC393 Rev. 1.5.0 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating

VCC Supply Voltage 0.5V to +7.0V
a
VIN DC Input Voltage 0.5V to +7.0V
VOUT DC Output Voltage 0.5V to VCC + 0.5V
IIK Input Diode Current 20mA
Ap git ic
IOK Output Diode Current(4) 20mA
IOUT DC Output Current 25mA
ICC DC VCC / GND Current 75mA
TSTG Storage Temperature 65C to +150C
Di n
TL Lead Temperature (Soldering, 10 seconds) 260C
lic l
Recommended Operating Conditions(1)
a
a
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
r
ad Symbol Parameter Rating
t

VIN Input Voltage 0V to +5.5V
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VOUT Output Voltage 0V to VCC

TOPR Operating Temperature 40C to +85C
t r, t f Input Rise and Fall Time
VCC = 3.3V 0.3V 0 100ns/V
VCC = 5.0V 0.5V 0 20ns/V
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Note:
1. Unused inputs must be held HIGH or LOW. They may not float.

74VHC393 Rev. 1.5.0 4
DC Electrical Characteristics
TA = 40C to
TA = 25C +85C
Symbol Parameter VCC (V) Conditions Min. Typ. Max. Min. Max. Units
VIH HIGH Level Input 2.0 1.50 1.50 V
Voltage 3.0 5.5 0.7 x VCC 0.7 x VCC
VIL LOW Level Input 2.0 0.50 0.50 V
a
Voltage
3.0 5.5 0.3 x VCC 0.3 x VCC
VOH HIGH Level Output 2.0 VIN = V IH IOH = 50A 1.9 2.0 1.9 V
Voltage or VIL
3.0 2.9 3.0 2.9
Ap git ic
4.5 4.4 4.5 4.4
3.0 IOH = 4mA 2.58 2.48 V
4.5 IOH = 8mA 3.94 3.80
VOL LOW Level Output 2.0 VIN = V IH IOL = 50A 0.0 0.1 0.1 V
Di n
Voltage 3.0 or VIL 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 IOL = 4mA 0.36 0.44 V
lic l 4.5 IOL = 8mA 0.36 0.44
a
a IIN Input Leakage
Current
0 5.5 VIN = 5.5V or GND 0.1 1.0 A
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ICC Quiescent Supply 5.5 VIN = VCC or GND 4.0 40.0 A
Current
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74VHC393 Rev. 1.5.0 5
AC Electrical Characteristics
TA = 40C to
TA = 25C +85C
tPLH, tPHL Propagation Delay 3.3 0.3 CL = 15pF 8.6 13.2 1.0 15.5 ns
Time (CPQA) CL = 50pF 11.1 16.7 1.0 19.0
5.0 0.5 CL = 15pF 5.8 8.5 1.0 10.0
a
CL = 50pF 7.3 10.5 1.0 12.0
Time (CPQB) CL = 50pF 12.7 19.3 1.0 22.0
Ap git ic
5.0 0.5 CL = 15pF 6.8 9.8 1.0 11.5
CL = 50pF 8.3 11.8 1.0 13.5
Time (CPQC) CL = 50pF 14.2 21.5 1.0 24.5
Di n
5.0 0.5 CL = 15pF 7.7 11.2 1.0 13.0
CL = 50pF 9.2 13.2 1.0 15.0
lic l Time (CPQD) CL = 50pF 15.5 23.2 1.0 26.5
a
a 5.0 0.5 CL = 15pF
CL = 50pF
8.5
10.0
12.5
14.5
1.0
1.0
14.5
16.5
r
ad Time (CLRQn) CL = 50pF 10.4 15.8 1.0 18.0

t
5.0 0.5 CL = 15pF 5.4 8.1 1.0 9.5

ec
CL = 50pF 6.9 10.1 1.0 11.5

fMAX Maximum Clock 3.3 0.3 CL = 15pF 75 120 65 MHz
CL = 50pF 45 65 35
5.0 0.5 CL = 15pF 125 170 105
CL = 50pF 85 115 75
CIN Input Capacitance VCC = Open 4 10 10 pF
El
(2)
CPD Power Dissipation 23 pF
Capacitance
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load Average operating current can be obtained by the equation:
ICC(Opr.) = CPD VCC fIN + ICC / 2 (per Counter)
AC Operating Requirements
TA = 25C T A = 40C to +85C
Symbol Parameter VCC (V) Typ. Guaranteed Minimum Units
tW(L), tW(H) Minimum Pulse Width (CP) 3.3 0.3 5.0 5.0 ns
5.0 0.5 5.0 5.0
tW(H) Minimum Pulse Width (CLR) 3.3 0.3 5.0 5.0 ns
5.0 0.5 5.0 5.0
tREM Minimum Removal Time 3.3 0.3 5.0 5.0 ns
5.0 0.5 4.0 4.0

74VHC393 Rev. 1.5.0 6
SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162,
SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A,
SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS
SDLS060 OCTOBER 1976 REVISED MARCH 1988
a
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SN54LS160A THRU SN54LS163A, SN54S162,
SN54S163, SN74LS160A THRU SN74LS163A,
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SN54160, SN54162, SN74160, SN74162
SYNCHRONOUS 4-BIT COUNTERS
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SN54161, SN54163, SN74161, SN74163
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Ap git ic
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SN54LS160A, SN54LS162A, SN74LS160A, SN74LS162A
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Ap git ic
Di n
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SN54LS161A, SN54LS163A, SN74LS161A, SN74LS163A
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Ap git ic
Di n
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SN54S162, SN74S162
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SN54S163, SN74S163
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Di n
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SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162,
SN74160, SN74162, SN74LS160A, SN74LS162A, SN74S162
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SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163,
SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163
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Di n
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SN54160 THRU SN54163, SN74160 THRU SN74163
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Di n
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SN54160 THRU SN54163, SN74160 THRU SN74163
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Ap git ic
Di n
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SN54LS160 THRU SN54LS163A, SN74LS160 THRU SN74LS163A
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Ap git ic
Di n
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SN54LS160 THRU SN54LS163A, SN74LS160 THRU SN74LS163A
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Ap git ic
Di n
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SN54S162, SN54S163, SN74S162, SN74S163
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Ap git ic
Di n
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SN54S162, SN54S163, SN74S162, SN74S163
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Ap git ic
Di n
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Di n
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SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A,
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Di n
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SN54S162, SN54S163, SN74S162, SN74S163
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Ap git ic
Di n
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a
Ap git ic
Di n
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a
Ap git ic
Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
a
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Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191

a
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Di n
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SN54190, SN54LS190, SN74190, SN74LS190
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Ap git ic
Di n
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SN54191, SN54LS191, SN74191, SN74LS191
a
Ap git ic
Di n
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SN54190, SN54LS190, SN74190, SN74LS190
a
Ap git ic
Di n
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SN54191, SN54LS191, SN74191, SN74LS191
a
Ap git ic
Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191

a
Ap git ic
Di n
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SN54190, SN54191, SN74190, SN74191
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Ap git ic
Di n
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SN54LS190, SN54LS191, SN74LS190, SN74LS191
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Ap git ic
Di n
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SN54LS190, SN54LS191, SN74LS190, SN74LS191
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Ap git ic
Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191

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Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191

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Di n
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SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191

a
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Di n
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SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
D Choice of Eight Latches or Eight D-Type SN54LS373, SN54LS374, SN54S373,

Flip-Flops in a Single Package SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
D 3-State Bus-Driving Outputs SN74LS374 . . . DB, DW, N, OR NS PACKAGE
D Full Parallel Access for Loading SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
D Buffered Control Inputs
D Clock-Enable Input Has Hysteresis to OC 1 20 VCC
Improve Noise Rejection (S373 and S374) 1Q 2 19 8Q
a
D P-N-P Inputs Reduce DC Loading on Data 1D 3 18 8D
Lines (S373 and S374) 2D 4 17 7D
2Q 5 16 7Q
Ap git ic
description 3Q 6 15 6Q
3D 7 14 6D
These 8-bit registers feature 3-state outputs 4D 8 13 5D
designed specifically for driving highly capacitive 4Q 9 12 5Q
or relatively low-impedance loads. The GND 10 11 C
Di n
high-impedance 3-state and increased
C for LS373 and S373; CLK for LS374 and S374.
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system SN54LS373, SN54LS374, SN54S373,
lic l without need for interface or pullup components.

SN54S374 . . . FK PACKAGE
a
(TOP VIEW)
a These devices are particularly attractive for
VCC
OC
implementing buffer registers, I/O ports,
1Q
8Q
1D
bidirectional bus drivers, and working registers.
r
ad The eight latches of the LS373 and S373 are 2D 4
3 2 1 20 19
18 8D
t
transparent D-type latches, meaning that while 2Q 5 17 7D

the enable (C or CLK) input is high, the Q outputs 3Q 6 16 7Q
ec
follow the data (D) inputs. When C or CLK is taken 3D 7 15 6Q

low, the output is latched at the level of the data 4D 8 14 6D
that was set up. 9 10 11 12 13
The eight flip-flops of the LS374 and S374 are

4Q
5Q
5D
GND
C
edge-triggered D-type flip-flops. On the positive

transition of the clock, the Q outputs are set to the C for LS373 and S373; CLK for LS374 and S374.
logic states that were set up at the D inputs.
El
Schmitt-trigger buffered inputs at the enable/clock lines of the S373 and S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
ORDERABLE TOP-SIDE
TA PACKAGE
PART NUMBER MARKING
Tube SN74LS373N SN74LS373N
Tube SN74LS374N SN74LS374N
PDIP N
a
Tube SN74LS373DW
LS373
Tube SN74LS374DW
LS374
Ap git ic
0C to 70C SOIC DW
Tube SN74S373DW
S373
Tube SN74S374DW
S374
Di n
Tape and reel SN74LS373NSR 74LS373
lic l SSOP DB
Tape and reel
Tape and reel
SN74S374NSR
SN74LS374DBR
74S374
LS374A
a
a Tube
Tube
SN54LS373J
SNJ54LS373J
SN54LS373J
SNJ54LS373J
r
Tube SN54LS374J SN54LS374J
ad Tube SNJ54LS374J SNJ54LS374J

t
CDIP J
Tube SN54S373J SN54S373J
ec
Tube SNJ54S373J SNJ54S373J

Tube SN54S374J SN54S374J
55C to 125C Tube SNJ54S374J SNJ54S374J
Tube SNJ54LS373W SNJ54LS373W
Tube SNJ54S374W SNJ54S374W
El

LCCC FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
Function Tables
LS373, S373
(each latch)
INPUTS OUTPUT
OC C D Q
L H H H
a
L H L L
L L X Q0
H X X Z
Ap git ic
LS374, S374
(each latch)
INPUTS OUTPUT
OC CLK D Q
Di n
L H H
L L L
L L X Q0
lic l H X X Z
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SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
logic diagrams (positive logic)

LS373, S373 LS374, S374
Transparent Latches Positive-Edge-Triggered Flip-Flops
1 1
OC OC
11 11
C CLK
a
C1 2 C1 2
3 1Q 3 1Q
1D 1D 1D 1D
Ap git ic
2D
4
C1
1D
5
2Q
2D
4
1D
C1 5
2Q
Di n
C1 6 C1 6
7 3Q 7 3Q
3D 1D 3D 1D
lic l C1 9 C1 9
a
4D
a8
1D
4Q
4D
8
1D
4Q
r
C1
ad 13
C1 12
5Q 13
12
5Q
t
5D 1D 5D 1D
ec
C1 15 C1 15
14 6Q 14 6Q
6D 1D 6D 1D
C1 16 C1 16
17 7Q 17 7Q
7D 1D 7D 1D
El
C1 19 C1 19
18 8Q 18 8Q
8D 1D 8D 1D
for S373 Only for S374 Only
Pin numbers shown are for DB, DW, J, N, NS, and W packages.

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
schematic of inputs and outputs

LS373
EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- AND TYPICAL OF ALL OUTPUTS
OUTPUT-CONTROL INPUTS
VCC VCC VCC
Req = 20 k NOM 17 k NOM 100 NOM
a
Input
Ap git ic
Input
Output
Di n
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LS374
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EQUIVALENT OF DATA INPUTS EQUIVALENT OF CLOCK- AND TYPICAL OF ALL OUTPUTS

OUTPUT-CONTROL INPUTS
VCC VCC VCC
30 k NOM 17 k NOM 100 NOM

El
Input
Input
Output

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
(LS devices)
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
a
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
Ap git ic
Di n
SN54LS SN74LS
UNIT
lic l
VCC Supply voltage 4.5 5 5 4.75 5 5.25 V
a
VOH
IOH
a High-level output voltage
5.5
1
5.5
2.6
V
mA
r
ad CLK high 15 15
t
tw Pulse duration ns
CLK low 15 15
LS373 5 5
ec
tsu Data setup time ns

LS374 20 20
LS373 20 20
th Data hold time ns
LS374 5 0
The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).
El

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374

otherwise noted)
SN54LS SN74LS
VIK Input clamp voltage VCC = MIN, II = 18 mA 1.5 1.5 V
a
VCC = MIN,, VIH = 2 V,,
VOH High level output voltage
High-level 24
2.4 34
3.4 24
2.4 31
3.1 V
VIL = VIL max, IOH = MAX
VCC = MIN,, VIH = 2 V,, IOL = 12 mA 0.25 0.4 0.25 0.4
VOL Low level output voltage
Low-level V
Ap git ic
VIL = VIL max IOL = 24 mA 0.35 0.5
Off-state output current,, VCC = MAX,, VIH = 2 V,,
IOZH 20 20 m A
high-level voltage applied VO = 2.7 V
Off-state output current,, VCC = MAX,, VIH = 2 V,,
IOZL 20
20 20
20 m A
low-level voltage applied VO = 0.4 V
Di n
Input current at maximum
II VCC = MAX
MAX, VI = 7 V 01
0.1 01
0.1 mA
input voltage
IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 m A
lic l
IIL Low-level input current VCC = MAX, VI = 0.4 V 0.4 0.4 mA
a
IOS
ICC
a Short-circuit output current
Supply current
VCC = MAX
VCC = MAX,, LS373
30
24
130
40
30
24
130
40
mA
mA
r
Output control at 4.5 V LS374 27 40 27 40
ad
t

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
ec

FROM TO LS373 LS374
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
RL = 667 , CL = 45 pF,
fmax 35 50 MHz
See Note 3
tPLH RL = 667 , CL = 45 pF,, 12 18
El
Data Any Q ns
tPHL See Note 3 12 18
tPLH RL = 667 , CL = 45 pF,, 20 30 15 28
C or CLK Any Q ns
tPHL See Note 3 18 30 19 28
tPZH RL = 667 , CL = 45 pF,, 15 28 20 26
OC Any Q ns
tPZL See Note 3 25 36 21 28
tPHZ 15 25 15 28
OC Any Q RL = 667 , CL = 5 pF ns
tPLZ 12 20 12 20
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
fmax = maximum clock frequency
tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
tPZH = output enable time to high level
tPZL = output enable time to low level
tPHZ = output disable time from high level
tPLZ = output disable time from low level

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
schematic of inputs and outputs

S373 and S374 S373 and S374
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
VCC VCC
2.8 k NOM 50 NOM
a
Ap git icInput
Output
Di n
lic l
a
a
r
ad
t
ec
El

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
(S devices)
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
a
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
Ap git ic

Di n
SN54S SN74S
UNIT
lic l
VCC
VOH
Supply voltage
High-level output voltage
4.5 5 5.5
5.5
4.75 5 5.25
5.5
V
V
a
IOH
a High-level output current
High 6
2
6
6.5 mA
r
tw Pulse duration,
duration clock/enable ns
Low 7.3 7.3
ad S373 0 0
t
tsu Data setup time ns

S374 5 5
ec
S373 10 10
th Data hold time ns
S374 2 2
El

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374

otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH 2 V
VIL 0.8 V
VIK VCC = MIN, II = 18 mA 1.2 V
SN54S 2.4 3.4
a
VOH VCC = MIN,
MIN VIH = 2 V
V, VIL = 0
0.8
8VV, IOH = MAX V
SN74S 2.4 3.1
VOL VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V
IOZH VCC = MAX, VIH = 2 V, VO = 2.4 V 50 m A
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IOZL VCC = MAX, VIH = 2 V, VO = 0.5 V 50 m A
II VCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VI = 2.7 V 50 m A
IIL VCC = MAX, VI = 0.5 V 250 m A
Di n
IOS VCC = MAX 40 100 mA
Outputs high 160
S373 Outputs low 160
lic l Outputs disabled 190
a
ICC a VCC = MAX
S374
Outputs high
Outputs low
Outputs disabled
110
140
160
mA
r
ad CLK and OC at 4 V, D inputs at 0 V
180
t
All typical values are at VCC= 5 V, TA = 25C.

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
ec

FROM TO S373 S374
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
RL = 280 , CL = 15 pF,
fmax 75 100 MHz
See Note 3
El
tPLH RL = 280 , CL = 15 pF,, 7 12

Data Any Q ns
tPHL See Note 3 7 12
tPLH RL = 280 , CL = 15 pF,, 7 14 8 15
C or CLK Any Q ns
tPHL See Note 3 12 18 11 17
tPZH RL = 280 , CL = 15 pF,, 8 15 8 15
OC Any Q ns
tPZL See Note 3 11 18 11 18
tPHZ 6 9 5 9
OC Any Q RL = 280 , CL = 5 pF ns
tPLZ 8 12 7 12
NOTE 3. Maximum clock frequency is tested with all outputs loaded.
fmax = maximum clock frequency
tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
tPZH = output enable time to high level
tPZL = output enable time to low level
tPHZ = output disable time from high level
tPLZ = output disable time from low level

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374

VCC
Test RL
Test Point S1
Point VCC
From Output
a
RL CL
Under Test Point
Ap git ic
CL
(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
lic l 0V
a
th
a
Low-Level
1.3 V
tw
1.3 V
Data
tsu
1.3 V 1.3 V
3V
r
Pulse Input
0V

t

ec
Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
In-Phase
Waveform 1 1.5 V
VOH 1.3 V
El
(see Notes C
and D)
tPZH tPHZ
tPHL tPLH
VOH
VOH
(see Notes C 1.3 V
Output 1.3 V 1.3 V
and D) 1.5 V
(see Note D) VOL
H. All parameters and waveforms are not applicable to all devices .

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374

SERIES 54S/74S DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
RL
a
CL
CL Under Test Point
Ap git ic
(see Note A) CL
(see Note A) S2

Di n
3V
High-Level Timing
lic l th
0V
a
tw
a
Low-Level
1.5 V 1.5 V
Data
tsu
1.5 V 1.5 V
3V
r
Pulse Input
0V

t

ec
Output 3V
Control
3V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 1.5 V
In-Phase VOH (see Notes C 1.5 V
El

tPZH tPHZ
tPHL tPLH
VOH
(see Notes C 1.5 V
Output 1.5 V 1.5 V 1.5 V
(see Note D) and D)
VOL
G. All parameters and waveforms are not applicable to all devices .

SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
TYPICAL APPLICATION DATA
Bidirectional Bus Driver

Output
Control 1
1D 1Q
2D 2Q
a
3D 3Q
Bidirectional 4D LS374 4Q
or Bidirectional
Data Bus 1 5D 5Q Data Bus 2
S374
Ap git ic
6D 6Q
7D C 7Q
8D 8Q
Clock 1 Clock 2
1Q 1D
Di n
2Q C 2D
3Q 3D
4Q LS374 4D
or
lic l 5Q
6Q
S374
5D
6D
a
a 7Q
8Q
7D
8D
r
Output
Control 2
ad
t
Clock 1 H
Bus
ec
Exchange
Clock
Clock 2 H
Clock Circuit for Bus Exchange
Expandable 4-Word by 8-Bit General Register File

El
LS374 or S374
1/2 SN74LS139
or SN74S139
G Y0 LS374 or S374
Y1
A Y2
Enable Select B Y3 LS374 or S374
LS374 or S374
1/2 SN74LS139 Y0 Y1 Y2 Y3
or SN74S139 A B G
Clock
Clock
Select

74VHC164 8-Bit Serial-In, Parallel-Out Shift Register
February 2008
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
a
Features General Description
High Speed: fMAX = 175MHz at VCC = 5V The VHC164 is an advanced high-speed CMOS device
Ap git ic
Low power dissipation: ICC = 4A (max.) at TA = 25C fabricated with silicon gate CMOS technology. It
High noise immunity: VNIH = VNIL = 28% VCC (min.) achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
Power down protection provided on all inputs
power dissipation. The VHC164 is a high-speed 8-Bit
Low noise: VOLP = 0.8V (max.) Serial-In/Parallel-Out Shift Register. Serial data is
Pin and function compatible with 74HC164
Di n
entered through a 2-input AND gate synchronous with
the LOW-to-HIGH transition of the clock. The device fea-
tures an asynchronous Master Reset which clears the
register, setting all outputs LOW independent of the
lic l clock. An input protection circuit insures that 0V to 7V
a
can be applied to the input pins without regard to the
a supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
r
backup. This circuit prevents device destruction due to
ad mismatched supply and input voltages.

t
ec
Ordering Information
Package
Order Number Number Package Description
74VHC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
El
74VHC164SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74VHC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.

74VHC164 Rev. 1.4.0
Connection Diagram Logic Symbol
a
Ap git ic
Pin Description
Pin Description
Function Table
Operating
Mode MR
Inputs
A B Q0
Outputs
Q1Q7
Di n
Names
Reset (Clear) L X X L LL
A, B Data Inputs
Shift H L L L Q0Q6
CP Clock Pulse Input (Active Rising Edge)
lic l
MR Master Reset Input (Active LOW)
H L H L Q0Q6
a
H H L L Q0Q6
a
Q0Q7 Outputs
H H H H Q0Q6
r
H = HIGH Voltage Levels
ad
Functional Description L = LOW Voltage Levels
t
The VHC164 is an edge-triggered 8-bit shift register with X = Immaterial

serial data entry and an output from each of the eight Q = Lower case letters indicate the state of the
ec
stages. Data is entered serially through one of two inputs referenced input or output one setup time prior to
(A or B); either of these inputs can be used as an active the LOW-to-HIGH clock transition.
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the
logical AND of the two data inputs (A B) that existed
El
before the rising clock edge. A LOW level on the Master

Reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all Q outputs LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.

74VHC164 Rev. 1.4.0 2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating

a
VIN DC Input Voltage 0.5V to +7.0V
VOUT DC Output Voltage 0.5V to VCC + 0.5V
IIK Input Diode Current 20mA
Ap git ic
IOK Output Diode Current 20mA
IOUT DC Output Current 25mA
ICC DC VCC / GND Current 75mA
TSTG Storage Temperature 65C to +150C
Di n
TL Lead Temperature (Soldering, 10 seconds) 260C
lic l
Recommended Operating Conditions(1)
a
a
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
r
ad Symbol Parameter Rating
t
VCC Supply Voltage 2.0V to 5.5V

VIN Input Voltage 0V to +5.5V
ec
VOUT Output Voltage 0V to VCC

TOPR Operating Temperature 40C to +85C
tr , tf Input Rise and Fall Time,
VCC = 3.3V 0.3V 0ns/V 100ns/V
VCC = 5.0V 0.5V 0ns/V 20ns/V
Note:
El
1. Unused inputs must be held HIGH or LOW. They may not float.

74VHC164 Rev. 1.4.0 3
DC Electrical Characteristics
TA = 40C to
TA = 25C +85C
VIH HIGH Level Input 2.0 1.50 1.50 V
Voltage 3.05.5 0.7 x VCC 0.7 x VCC
VIL LOW Level Input 2.0 0.50 0.50 V
a
Voltage
3.05.5 0.3 x VCC 0.3 x VCC
VOH HIGH Level 2.0 VIN = VIH IOH = 50A 1.9 2.0 1.9 V
Output Voltage or VIL
3.0 2.9 3.0 2.9
Ap git ic
4.5 4.4 4.5 4.4
3.0 IOH = 4mA 2.58 2.48
4.5 IOH = 8mA 3.94 3.80
VOL LOW Level 2.0 VIN = VIH IOL = 50A 0.0 0.1 0.1 V
Di n
Output Voltage 3.0 or VIL 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 IOL = 4mA 0.36 0.44
lic l 4.5 IOL = 8mA 0.36 0.44
a
a IIN Input Leakage
Current
05.5 VIN = 5.5V or GND 0.1 1.0 A
r
ICC Quiescent 5.5 VIN = VCC or GND 4.0 40.0 A
Supply Current
ad
t
Noise Characteristics
ec
TA = 25C
Symbol Parameter VCC (V) Conditions Typ. Limits Units
VOLP (2) Quiet Output Maximum 5.0 CL = 50pF 0.5 0.8 V
Dynamic VOL
VOLV(2) Quiet Output Minimum 5.0 CL = 50pF 0.5 0.8 V
El
Dynamic VOL
VIHD(2) Minimum HIGH Level 5.0 CL = 50pF 3.5 V
Dynamic Input Voltage
VILD(2) Maximum LOW Level 5.0 CL = 50pF 1.5 V
Dynamic Input Voltage
Note:
2. Parameter guaranteed by design.

74VHC164 Rev. 1.4.0 4
AC Electrical Characteristics
TA = 40C
TA = 25C to +85C
fMAX Maximum Clock 3.3 0.3 CL = 15pF, RL = 1k 80 125 65 MHz
Frequency CL = 50pF, RL = 1k 50 75 45
a
5.0 0.5 CL = 15pF, RL = 1k 125 175 105
CL = 50pF, RL = 1k 85 115 75
tPLH, tPHL Propagation Delay 3.3 0.3 CL = 15pF, RL = 1k 8.4 12.8 1.0 15.0 ns
Time (CPQn)
Ap git ic
CL = 50pF, RL = 1k 10.9 16.3 1.0 18.5
5.0 0.5 CL = 15pF, RL = 1k 5.8 9.0 1.0 10.5
CL = 50pF, RL = 1k 7.3 11.0 1.0 12.5
tPHL Propagation Delay 3.3 0.3 CL = 15pF, RL = 1k 8.3 12.8 1.0 15.0 ns
Di n
Time (MRQn) CL = 50pF, RL = 1k 10.8 16.3 1.0 18.5
5.0 0.5 CL = 15pF, RL = 1k 5.2 8.6 1.0 10.0
CL = 50pF, RL = 1k 6.7 10.6 1.0 12.0
lic l CIN Input Capacitance VCC = Open 4 10 10 pF
a
a CPD Power Dissipation
Capacitance
(3) 76 pF
r
Note:
ad
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
t
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD VCC fIN + ICC.
ec
AC Operating Requirements
TA = 40C
TA = 25C to +85C
VCC (V)(4) Guaranteed
El
Symbol Parameter Typ. Minimum Units

tW(L), tW(H) Minimum Pulse Width (CP) 3.3 5.0 5.0 ns
5.0 5.0 5.0
tW(L) Minimum Pulse Width (MR) 3.3 5.0 5.0 ns
5.0 5.0 5.0
tS Minimum Setup Time 3.3 5.0 6.0 ns
5.0 4.5 4.5
tH Minimum Hold Time 3.3 0.0 0.0 ns
5.0 1.0 1.0
tREC Minimum Removal Time (MR) 3.3 2.5 2.5 ns
5.0 2.5 2.5
Note:
4. VCC is 3.3 0.3V or 5.0 0.5V

74VHC164 Rev. 1.4.0 5
74HC299; 74HCT299
8-bit universal shift register; 3-state
Rev. 03 28 July 2008 Product data sheet
1. General description
a
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in
compliance with JEDEC standard no. 7A.
Ap git ic
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and
hold operations. An operation is determined by the mode select inputs S0 and S1, as
shown in Table 3.
Di n
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in
serial shifting of longer words.
lic l
a
a A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of
the clock pulse. Inputs can change when the clock is in either state, provided that the
r
recommended set-up and hold times are observed.
ad
t
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,
ec
the shift, hold, load and reset operations still occur when preparing for a parallel load
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.
2. Features
n Multiplexed inputs/outputs provide improved bit density
El
n Four operating modes:

u Shift left
u Shift right
u Hold (store)
u Load data
n Operates with output enable or at high-impedance OFF-state (Z)
n 3-state outputs drive bus lines directly
n Cascadable for n-bit word lengths
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Specified from 40 C to +85 C and from 40 C to +125 C
NXP Semiconductors 74HC299; 74HCT299
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
a
74HC299
74HC299D 40 C to +125 C SO20 plastic small outline package; 20 leads; body SOT163-1
width 7.5 mm
Ap git ic
74HC299DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1
body width 5.3 mm
74HC299N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC299PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
Di n
74HCT299
74HCT299D 40 C to +125 C SO20 plastic small outline package; 20 leads; body SOT163-1
width 7.5 mm
lic l
74HCT299DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1
a
a
74HCT299N 40 C to +125 C DIP20
body width 5.3 mm
plastic dual in-line package; 20 leads (300 mil) SOT146-1
r
74HCT299PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1
ad body width 4.4 mm

t
4. Functional diagram
ec
1 19
DSR S0 S1 DSL
11 18
12 CP
El
8-BIT SHIFT REGISTER

MR
9
Q0 Q7
8 17
OE1
2
OE2 INPUT/3-STATE OUTPUT CIRCUITRY
3
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
7 13 6 14 5 15 4 16 001aai460
Fig 1. Functional diagram
74HC_HCT299_3 NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 28 July 2008 2 of 24

9
R SRG8
2
3 & 3EN5
1
0 0
19 M
1 3
12
C4/1 /2
a
11
1 I/O0 7 1, 4D
S0 7 8
3, 4D Z6
19 S1 I/O1 13 6, 5
Ap git ic
11 DSR I/O2 6 13
3, 4D
18 DSL I/O3 14 5
6
I/O4 5
14
12 CP I/O5 15 5
9 MR I/O6 4 15
Di n
4
I/O7 16
2 16
OE Q0 8 3, 4D
3 17
7, 5 Z7
Q7 17 18
2, 4D
lic l 001aai458 001aai459
a
Fig 2.
a Logic symbol Fig 3. IEC logic symbol
r
ad
t
ec
El

DSR
S0
S1 D
Q I/O0
CP
a
FF0
RD
CP
Ap git ic
Q0
D
OE1 Q I/O1
CP
FF1
OE2 RD
Di n
D
Q I/O2
CP
lic l FF2
RD
a
a
r
D
Q I/O3
ad CP
FF3
t
RD
ec
D
Q I/O4
CP
FF4
RD
El
D
Q I/O5
CP
FF5
RD
D
Q I/O6
CP
FF6
RD
DSL
D
Q I/O7
CP
FF7
Q7 RD
MR 001aai461
Fig 4. Logic diagram

5. Pinning information
5.1 Pinning
a
74HC299
74HCT299
S0 1 20 VCC
Ap git ic
74HC299 OE1 2 19 S1
74HCT299
OE2 3 18 DSL
S0 1 20 VCC
I/O6 4 17 Q7
OE1 2 19 S1
Di n
3 18 DSL I/O4 5 16 I/O7
OE2
I/O6 4 17 Q7 I/O2 6 15 I/O5
I/O4 5 16 I/O7
I/O0 7 14 I/O3
lic l I/O2 6
7
15 I/O5
14 I/O3 Q0 8 13 I/O1
a
I/O0
a Q0
MR
8
9
13 I/O1
12 CP
MR 9 12 CP
r
GND 10 11 DSR GND 10 11 DSR
ad 001aai511 001aai457
t
Fig 5. Pin configuration (SO20 and (T)SSOP20) Fig 6. Pin configuration (DIP20)
ec
5.2 Pin description

Table 2. Pin description
Symbol Pin Description
S0 1 mode select input
El
OE1 2 3-state output enable input (active LOW)

OE2 3 3-state output enable input (active LOW)
I/O6 4 parallel data input or 3-state parallel output (bus driver)
Q0 8 serial output (standard output)
MR 9 asynchronous master reset input (active LOW)
GND 10 ground (0 V)
DSR 11 serial data shift-right input
CP 12 clock input (LOW to HIGH, edge-triggered)
Q7 17 serial output (standard output)

Table 2. Pin description continued

Symbol Pin Description
DSL 18 serial data shift-left input
S1 19 mode select input
VCC 20 positive supply voltage
a
6. Functional description
Ap git ic
Table 3. Function table[1]
Input Response
MR S1 S0 CP
L X X X asynchronous reset; Q0 to Q7 = LOW
Di n
H H H parallel load; I/On Qn
H L H shift right; DSR Q0, Q0 Q1, etc.
H H L shift left; DSL Q7, Q7 Q6, etc.
H
lic l L L X hold
a
[1]
a
H = HIGH voltage level;
L = LOW voltage level;
r
= LOW to HIGH CP transition;
adX = dont care.

t
7. Limiting values
ec
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
VI < 0.5 V or VI > VCC + 0.5 V 20
El
IIK input clamping current [1] - mA

IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA
IO output current 0.5 V < VO < VCC + 0.5 V
standard outputs - 25 mA
bus driver outputs - 35 mA
ICC supply current
standard outputs - 50 mA
bus driver outputs - 70 mA
IGND ground current
standard outputs 50 - mA
bus driver outputs 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
DIP20 package [2] - 750 mW
SO20 package [3] - 500 mW
(T)SSOP20 package [4] - 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly at 12 mW/K above 70 C.

[3] Ptot derates linearly at 8 mW/K above 70 C.
[4] Ptot derates linearly at 5.5 mW/K above 60 C.
8. Recommended operating conditions
a
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74HC299 74HCT299 Unit
Ap git ic
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Di n
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate
lic l VCC = 2.0 V - - 625 - - - ns/V
a
a VCC = 4.5 V
VCC = 6.0 V
-
-
1.67
-
139
83
-
-
1.67
-
1.39
-
ns/V
ns/V
r
ad
9. Static characteristics
t
Table 6. Static characteristics

ec
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to 40 C to Unit
+85 C +125 C
Min Typ Max Min Max Min Max
74HC299
VIH HIGH-level VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
El
input voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
input voltage VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

Table 6. Static characteristics continued

+85 C +125 C
VOH HIGH-level VI = VIH or VIL
a
output voltage all outputs
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
Ap git ic IO = 20 A; VCC = 6.0 V

standard outputs
IO = 4.0 mA;
VCC = 4.5 V
5.9
3.98
6.0
4.32
-
-
5.9
3.84
-
-
5.9
3.7
-
-
V
V
Di n
IO = 5.2 mA; 5.48 5.81 - 5.34 - 5.2 - V
VCC = 6.0 V
bus driver outputs
lic l IO = 6.0 mA; 3.98 4.32 - 3.84 - 3.7 - V
a
a VCC = 4.5 V
IO = 7.8 mA; 5.48 5.81 - 5.34 - 5.2 - V
r
VCC = 6.0 V
VOL
ad LOW-level VI = VIH or VIL
t

IO = 20 A; VCC = 2.0 V
ec
- 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
standard outputs
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
El
bus driver outputs

IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; - - 0.1 - 1.0 - 1.0 A
current VCC = 6.0 V
IOZ OFF-state output VI = VIH or VIL; VO = VCC or - - 0.5 - 5.0 - 10.0 A
current GND; VCC = 6.0 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 A
VCC = 6.0 V
CI input capacitance - 3.5 - - - - - pF
CI/O input/output - 10 - - - - - pF
capacitance
CPD power dissipation per package [1] - 120 - - - - - pF
capacitance
74HCT299
VIH HIGH-level VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
input voltage

Table 6. Static characteristics continued

+85 C +125 C
VIL LOW-level VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
a
input voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
Ap git ic
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
standard outputs
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
bus driver outputs
Di n
IO = 6.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage
lic l all outputs

IO = 20 A
a
a - 0 0.1 - 0.1 - 0.1 V
standard outputs
r
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
ad bus driver outputs

t
IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V

II input leakage VI = VCC or GND; - - 0.1 - 1.0 - 1.0 A
ec
current VCC = 5.5 V

IOZ OFF-state output VI = VIH or VIL; VO = VCC or - - 0.5 - 5.0 - 10.0 A
current GND per input pin; other
inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 A
VCC = 5.5 V
El
ICC additional supply per input pin;

current VI = VCC 2.1 V;
other inputs at VCC or
GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
I/On, DSR, DSL, MR - 25 90 - 112.5 - 122.5 A
and S1
CP, S0 - 60 216 - 270 - 294 A
OEn - 30 108 - 135 - 147 A
CI input capacitance - 3.5 - - - - - pF
CI/O input/output - 10 - - - - - pF
capacitance
CPD power dissipation per package [1] - 125 - - - - - pF
capacitance
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;

(CL VCC2 fo) = sum of outputs.

CL = output load capacitance in pF;
VCC = supply voltage in V;
VI = GND to VCC for 74HC299;
VI = GND to (VCC 1.5 V) for 74HCT299.
a
10. Dynamic characteristics
Table 7. Dynamic characteristics
Ap git ic
GND (ground = 0 V); for test circuit, see Figure 11.
+85 C +125 C
Di n
74HC299
tpd propagation CP to Q0, Q7; see Figure 7 [1]
delay VCC = 2.0 V - 66 200 - 250 - 300 ns
lic l VCC = 4.5 V - 24 40 - 50 - 60 ns
a
a VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
-
20
19
-
34
-
-
-
43
-
-
-
51
ns
ns
r
CP to I/On; see Figure 7
ad VCC = 2.0 V - 66 200 - 250 - 300 ns

t
VCC = 4.5 V - 24 40 - 50 - 60 ns
ec
VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns
VCC = 6.0 V - 19 34 - 43 - 51 ns
MR to Q0, Q7 or I/On; [2]
see Figure 8
VCC = 2.0 V - 66 200 - 250 - 300 ns
VCC = 4.5 V - 24 40 - 50 - 60 ns
El
VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns
VCC = 6.0 V - 19 34 - 43 - 51 ns
tt transition time bus driver (I/On); see Figure 7 [3]
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
standard (Q0, Q7); see Figure 7
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns

Table 7. Dynamic characteristics continued

+85 C +125 C
tW pulse width CP HIGH or LOW; see Figure 7
a
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
Ap git ic MR LOW; see Figure 8

VCC = 2.0 V
VCC = 4.5 V
80
16
19
7
-
-
100
20
-
-
120
24
-
-
ns
ns
Di n
VCC = 6.0 V 14 6 - 17 - 20 - ns
tPZH OFF-state to OEn to I/On; see Figure 10 [4]
HIGH VCC = 2.0 V - 50 155 - 195 - 235 ns

propagation
lic l delay VCC = 4.5 V - 18 31 - 39 - 47 ns
a
tPZL
a OFF-state to
VCC = 6.0 V
OEn to I/On; see Figure 10
- 14 26 - 33 - 40 ns
r
LOW VCC = 2.0 V - 41 130 - 165 - 195 ns
propagation
ad delay VCC = 4.5 V - 15 26 - 33 - 39 ns

t
VCC = 6.0 V - 12 22 - 28 - 33 ns
ec
tPHZ HIGH to OEn to I/On; see Figure 10 [5]
OFF-state VCC = 2.0 V - 66 185 - 230 - 280 ns

propagation
delay VCC = 4.5 V - 24 37 - 46 - 56 ns
VCC = 6.0 V - 19 31 - 39 - 48 ns
tPLZ LOW to OEn to I/On; see Figure 10
OFF-state VCC = 2.0 V - 55 155 - 195 - 235 ns
El
propagation
delay VCC = 4.5 V - 20 31 - 39 - 47 ns
VCC = 6.0 V - 16 26 - 33 - 40 ns
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 5 14 - 5 - 5 - ns
VCC = 4.5 V 5 5 - 5 - 5 - ns
VCC = 6.0 V 5 4 - 5 - 5 - ns


+85 C +125 C
tsu set-up time DSR, DSL to CP; see Figure 7
a
VCC = 2.0 V 100 33 - 125 - 150 - ns
VCC = 4.5 V 20 12 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
Ap git ic S0, S1 to CP; see Figure 9

VCC = 2.0 V
VCC = 4.5 V
100
20
33
12
-
-
125
25
-
-
150
30
-
-
ns
ns
Di n
VCC = 6.0 V 17 10 - 21 - 26 - ns
I/On to CP; see Figure 7
VCC = 2.0 V 125 39 - 155 - 190 - ns
lic l VCC = 4.5 V 25 14 - 31 - 38 - ns
a
th
a hold time
VCC = 6.0 V
I/On, DSR, DSL to CP;
21 11 - 26 - 32 - ns
r
see Figure 7
ad VCC = 2.0 V 0 14 - 0 - 0 - ns
t
VCC = 4.5 V 0 5 - 0 - 0 - ns
VCC = 6.0 V 0 4 - 0 - 0 - ns
ec
S0, S1 to CP; see Figure 9

VCC = 2.0 V 0 28 - 0 - 0 - ns
VCC = 4.5 V 0 10 - 0 - 0 - ns
VCC = 6.0 V 0 8 - 0 - 0 - ns
fmax maximum CP input; see Figure 7
El
frequency VCC = 2.0 V 5.0 15 - 4.0 - 3.4 - MHz

VCC = 4.5 V 25 45 - 20 - 17 - MHz
VCC = 5.0 V; CL = 15 pF - 50 - - - - - MHz
VCC = 6.0 V 29 54 - 24 - 20 - MHz
74HCT299
tpd propagation CP to Q0, Q7; see Figure 7 [1]
delay VCC = 4.5 V - 22 37 - 46 - 56 ns

VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns
CP to I/On; see Figure 7
VCC = 4.5 V - 22 37 - 46 - 56 ns
VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns
MR to Q0, Q7 or I/On; [2]
see Figure 8
VCC = 4.5 V - 27 46 - 58 - 69 ns
VCC = 5.0 V; CL = 15 pF - 23 - - - - - ns


+85 C +125 C
tt transition time bus driver (I/On); see Figure 7 [3]
a
VCC = 4.5 V - 5 12 - 15 - 18 ns
standard (Q0, Q7); see Figure 7
VCC = 4.5 V - 7 15 - 19 - 22 ns
Ap git ic
tW pulse width clock HIGH or LOW; see Figure 7
VCC = 4.5 V
master reset LOW; see Figure 8
20 10 - 25 - 30 - ns
Di n
VCC = 4.5 V 20 11 - 25 - 30 - ns
ten enable time OEn to I/On; see Figure 10 [4]
VCC = 4.5 V - 19 30 - 38 - 45 ns
lic l
tPHZ HIGH to OEn to I/On; see Figure 10 [5]
a
a OFF-state VCC = 4.5 V - 24 37 - 46 - 56 ns
propagation
delay
r
tPLZ LOW to OEn to I/On; see Figure 10
ad OFF-state VCC = 4.5 V - 20 32 - 40 - 48 ns

t
propagation
delay
ec
trec recovery time MR to CP; see Figure 8

VCC = 4.5 V 10 2 - 9 - 11 - ns
tsu set-up time I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V 25 14 - 31 - 38 - ns
El
VCC = 4.5 V 32 18 - 40 - 48 - ns
th hold time I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V 0 11 - 0 - 0 - ns
VCC = 4.5 V 0 17 - 0 - 0 - ns
fmax maximum CP input; see Figure 7
frequency VCC = 4.5 V 25 42 - 20 - 17 - MHz
VCC = 5.0 V; CL = 15 pF - 46 - - - - - MHz
[1] tpd is the same as tPHL and tPLH.

[2] tpd is the same as tPHL.
[3] tt is the same as tTHL and tTLH.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.

[6] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
a
VCC = supply voltage in V;
N = number of inputs switching.
11. Waveforms
Ap git ic I/On, DSR, DSL

VI
Di n VM
inputs
GND
th th
tsu tsu
lic l 1/fmax
a
a CP input
VI
VM
r
GND
ad tW
t
tPHL tPLH
VOH
ec
I/On, Q0, Q7
VM
outputs
VOL
tTHL tTLH
001aai462
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
El
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to
clock pulse set-up and hold times, the output transition times and the maximum clock frequency

VI
MR input VM
GND
tW
a
trec
VI
CP input VM
Ap git ic
GND
tPHL
VOH
I/On, Q0, Q7 VM
outputs
Di n
VOL
001aai463

lic l
Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the
a
a master reset to clock pulse removal time
r
ad VI
t
I/On, DSR, DSL, Sn

VM
inputs
ec
GND
tsu th tsu th
VI
CP input VM
GND
001aai464
El

Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse

tr tf
VI
90 %
OEn input VM
GND 10 %
a
tPLZ tPZL
VOH
I/On output
LOW to OFF VM
Ap git ic
OFF to LOW
10 %
VOL
tPHZ tPZH
VOH
I/On output 90 %
Di n
HIGH to OFF VM
OFF to HIGH
VOL
outputs outputs outputs
enabled disabled enabled
lic l
a
001aai465
a Measurement points are given in Table 8.
r
ad
Fig 10. 3-state enable and disable times for OEn inputs
t
Table 8. Measurement points

ec
Type Input Output

VI VM VM
74HC299 VCC 0.5VCC 0.5VCC
74HCT299 3V 1.3 V 1.3 V
El
VCC VCC
VI VO RL = 1 k S1
PULSE open
DUT
GENERATOR
CL
RT
50 pF
001aai466
Test data is given in Table 9.

Definitions for test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 11. Test circuit for measuring switching times

Table 9. Test data

Type Input Load S1 position
VI tr, tf CL RL tPHL, tPLH
74HC299 VCC 6 ns 15 pF, 50 pF 1 k open
74HCT299 3V 6 ns 15 pF, 50 pF 1 k open
a
Ap git ic
Di n
lic l
a
a
r
ad
t
ec
El

12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
a
Ap git ic
D E A
X
c
Di n
y HE v M A
lic l Z
a
a 20 11
r
ad Q
t
A2 A
A1 (A 3)
ec
pin 1 index

Lp
L
1 10 detail X
e w M
bp
El
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)

max.
0.3 2.45 0.49 0.32 13.0 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.1 2.25 0.36 0.23 12.6 7.4 10.00 0.4 1.0 0.4 8o
o
0.012 0.096 0.019 0.013 0.51 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.49 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT163-1 075E04 MS-013
03-02-19
Fig 12. Package outline SOT163-1 (SO20)


SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
a
Ap git ic
D E A
X
Di n
c
y HE v M A
lic l Z
a
a 20 11
r
ad
t
Q
A2 A
(A 3)
ec
A1
pin 1 index

Lp
L
1 10 detail X
w M
bp
El
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1)
max.
mm 2
0.21 1.80 0.38 0.20 7.4 5.4 7.9 1.03 0.9 0.9 8o
0.25 0.65 1.25 0.2 0.13 0.1 o
0.05 1.65 0.25 0.09 7.0 5.2 7.6 0.63 0.7 0.5 0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT339-1 MO-150
03-02-19
Fig 13. Package outline SOT339-1 (SSOP20)


DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
a
Ap git ic D ME
seating plane
A2 A
Di n
L A1
lic l c
a
a Z e
b1
w M
(e 1)
r
b
20 11 MH
ad
t
pin 1 index
ec
1 10
El
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A A1 A2
b b1 c D
(1)
E
(1)
e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 0.36 26.92 6.40 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 2
1.30 0.38 0.23 26.54 6.22 3.05 7.80 8.3
0.068 0.021 0.014 1.060 0.25 0.14 0.32 0.39
inches 0.17 0.02 0.13 0.1 0.3 0.01 0.078
0.051 0.015 0.009 1.045 0.24 0.12 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

ISSUE DATE
99-12-27
SOT146-1 MS-001 SC-603
03-02-13
Fig 14. Package outline SOT146-1 (DIP20)


TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
a
Ap git ic D
c
E A
X
Di n
y HE v M A
lic l 20 11
a
a
r
Q
ad A2 (A 3) A
t
A1
pin 1 index

ec
Lp
L
1 10
detail X
w M
e bp
El
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1)
max.
mm 1.1
0.15 0.95 0.30 0.2 6.6 4.5 6.6 0.75 0.4 0.5 8o
0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 6.4 4.3 6.2 0.50 0.3 0.2 0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT360-1 MO-153
03-02-19
Fig 15. Package outline SOT360-1 (TSSOP20)


13. Revision history

Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT299_3 20080728 Product data sheet - 74HC_HCT299_CNV_2
a
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.

Ap git ic
Section 3: Ordering information added
Section 12: Package outline drawings added
Section 9 Static characteristics: Family data added
Section 11 Waveforms: Test circuit added
Di n
74HC_HCT299_CNV_2 19970828 Product specification - -
lic l
a
a
r
ad
t
ec
El

14. Legal information
14.1 Data sheet status

Document status[1][2] Product status[3] Definition
a
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
Ap git ic
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term short data sheet is explained in section Definitions.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Di n
14.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customers own risk.
lic l
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications Applications that are described herein for any of these
a
a
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
r
with the same product type number(s) and title. A short data sheet is intended Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
ad
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data damage to the device. Limiting values are stress ratings only and operation of
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sheet, which is available on request via the local NXP Semiconductors sales the device at these or any other conditions above those given in the
office. In case of any inconsistency or conflict with the short data sheet, the Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
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full data sheet shall prevail.

Terms and conditions of sale NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
14.3 Disclaimers at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
General Information in this document is believed to be accurate and explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
reliable. However, NXP Semiconductors does not give any representations or any inconsistency or conflict between information in this document and such
warranties, expressed or implied, as to the accuracy or completeness of such terms and conditions, the latter will prevail.
information and shall have no liability for the consequences of use of such
No offer to sell or license Nothing in this document may be interpreted
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information.
or construed as an offer to sell products that is open for acceptance or the
Right to make changes NXP Semiconductors reserves the right to make grant, conveyance or implication of any license under any copyrights, patents
changes to information published in this document, including without or other industrial or intellectual property rights.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof. 14.4 Trademarks
Suitability for use NXP Semiconductors products are not designed,
Notice: All referenced brands, product names, service names and trademarks
authorized or warranted to be suitable for use in medical, military, aircraft,
are the property of their respective owners.
space or life support equipment, nor in applications where failure or
15. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
a
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
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6 Functional description . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
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11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
14
lic lLegal information. . . . . . . . . . . . . . . . . . . . . . . 23
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14.1
14.2
14.3
aData sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15
adContact information. . . . . . . . . . . . . . . . . . . . . 23
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16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
NXP B.V. 2008. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 July 2008
Document identifier: 74HC_HCT299_3
SN54165, SN54LS165A, SN74165, SN74LS165A
The SN54165 and SN74165 devices
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
are obsolete and are no longer supplied.
SDLS062B OCTOBER 1976 REVISED JANUARY 2000
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SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS The SN54165 and SN74165 devices
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SN54165, SN54LS165A, SN74165, SN74LS165A
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SN54165, SN54LS165A, SN74165, SN74LS165A
typical shift, load, and inhibit sequences
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SN54165, SN54LS165A, SN74165, SN74LS165A
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otherwise noted)
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switching characteristics, SN54165 and SN74165, VCC = 5 V, TA = 25 C

SN54165, SN54LS165A, SN74165, SN74LS165A
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otherwise noted)
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switching characteristics, SN54LS165A and SN74LS165A, VCC = 5 V, TA = 25 C

SN54165, SN54LS165A, SN74165, SN74LS165A
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Captulo 5.- Dispositivos computacionales
5.1.- Sumador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2
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5.2.- Unidad lgica y aritmtica . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4
5.3.- Coprocesador y FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6
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5.4.- Referencias del captulo 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7
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V1.0 5.1
5.- Dispositivos computacionales

Los dispositivos computacionales son aquellos que realizan funciones aritmticas
y lgicas de varios bits en paralelo (4, 8, 16,...) como:
Funciones aritmticas
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< Suma
< Resta
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< Divisin
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Funciones lgicas
< AND
< NAND
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< NOR
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< Complemento o Inversin

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< Desplazamientos (a derecha y a izquierda)

< Rotaciones
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5.1.- Sumador
Un sumador es un dispositivo especfico para realizar sumas. La figura 5.1
muestra el esquela digital de un sumador de 4 bits. Como puede verse, se trata de un
dispositivo complejo que contiene 32 elementos bsicos (en este caso). Cuando se
incrementa el nmero de bits, esta complejidad crece bastante, lo que hace que sea
inviable su representacin. Es por ello por lo que se utiliza un representacin como
bloque funcional (figura 5.2) siempre acompaada de la tabla de verdad que define su
funcionamiento (figura 5.3). Estas figuras corresponden al modelo comercial 74F283
(ver la referencia).
V1.0 5.2
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Figura 5.1. Esquema digital de un sumador completo de 4 bits.

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Figura 5.3 Tabla de verdad del sumador de la figura 5.1.
V1.0 5.3
Figura 5.2 Sumador como

bloque funcional.
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5.2.- Unidad lgica y aritmtica
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Unidad, Lgica y Aritmtica (ULA) como la que se muestra en la figura 5.4 que realiza
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funciones aritmticas como suma, resta (figura 5.5) y funciones lgicas. Estas dos
figuras corresponden al modelo comercial L4C383 (ver esta referencia) que trabaja con
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datos de 16 bits.
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Observar la complejidad de la circuitera para realizar estas tareas.

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Sin embargo, las ULAs que se utilizan en los :P son an mas complejas puesto
que disponen de funciones de desplazamiento y recirculacin de bits y otras funciones
complementarias. Es por ello que en SBM de utiliza un bloque multifuncional
denominado ULA representado por medio de un smbolo como el de la figura 5.6, en
la que por medio de una seales de control se selecciona la funcin a realizar.
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V1.0 5.4
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Figura 5.4. Esquema digital de una ULA.

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Figura 5.5. Funciones de la

ULA de la figura 5.4.
Figura 5.6. Representacin simplificada de una

ULA.
V1.0 5.5
5.3.- Coprocesador y FPU

Los coprocesadores eran dispositivos de clculo que funcionaban bajo el control
de una UCP. Se trataba de un dispositivo externo al procesador especializado en
clculo numrico, ms concretamente en punto flotante, lo que se conoce como FPU
(Floating Point Unit). Las frases anteriores estn en pasado porque hoy no se utilizan
los coprocesadores en este formato. Los procesadores actuales que tienen opciones
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de clculo numrico lo hacen por medio de ULAs o FPUs integradas en el propio
procesador.
Sin embargo no deja de ser interesante saber cmo son las FPUs anque sean
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antiguas ya que su principio es el mismo actualmente.
En todos los casos de clculo, un procesador con una ULA puede realizar todas
las funciones de una FPU. Sin embargo el xito de
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estas unidades lo podemos ver en la figura 5.7
que hace una comparativa en cuanto a velocidad
de proceso (o su inverso, tiempo de ejecucin)
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entre un procesador (8086) y el mismo procesador
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con FPU (8086 + 8087).
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En esta figura se puede ver que una simple
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suma es casi 100 veces ms rpida cuanto hay
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FPU, lo que significa un incremento porcentual de
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la velocidad de proceso del 10.000%.

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Si observamos el tiempo de clculo de una

raz cuadrada, la relacin de tiempos es de 544
veces ms rpido con FPU.
Las FPUs tienen una arquitectura similar a
una UCP, como puede verse en la referencia
Figura 5.7. Comparativa de tiempos
8087.
El
de ejecucin entre procesador y

procesador + FPU.
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V1.0 5.7
Philips Semiconductors Product specification
4-bit binary full adder with fast carry 74F283
FEATURES PIN CONFIGURATION

High speed 4-bit addition
Cascadable in 4-bit increments 1 1 16 VCC
Fast Internal carry look-ahead B1 2 15 B2
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A1 3 14 A2
0 4 13 2
DESCRIPTION
The 74F283 adds two 4-bit binary words (An plus Bn) plus the A0 5 12 A3
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incoming carry. The binary sum appears on the sum outputs B0 6 11 B3
(03) and the outgoing carry (COUT) according to the equation:
CIN 7 10 3
CIN+20(A0+B0)+21(A1+B1)+22(A2+B2)+23(A3+B3)
=0+21+42+83+16COUT GND 8 9 COUT
where (+)=plus
Due to the symmetry of the binary add function, the 74F283 can be SF00852
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used with either all active-High operands (positive logic) or with all
active-Low operands (negative logic). See Function Table. In case of
all active-Low operands (negative logic) the results 14 and COUT TYPICAL TYPICAL
should be interpreted also as active-Low. With active-High inputs, TYPE PROPAGATION SUPPLY CURRENT
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CIN cannot be left open; it must be held Low when no carry in is DELAY (TOTAL)
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intended. Interchanging inputs of equal weight does not affect the
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operation, thus A0, B0, CIN can arbitrarily be assigned to pins 5, 6,
7, etc.
74F283
6.5ns 40mA
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Due to pin limitations, the intermediate carries of the 74F283 are not
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brought out for use as inputs or outputs. However, other means can
be used to effectively insert a carry into, or bring a carry out from, an DESCRIPTION
COMMERCIAL RANGE
VCC = 5V 10%, PKG DWG #
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intermediate stage. Tamb = 0C to +70C

16-pin plastic DIP N74F283N SOT38-4
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16-pin plastic SO N74F283D SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

74F(U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
A0 - A3 A operand inputs 1.0/2.0 20A/1.2mA
B0 - B3 B operand inputs 1.0/2.0 20A/1.2mA
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CIN Carry input 1.0/1.0 20A/0.6mA

COUT Carry output 50/33 1.0mA/20mA
03 Sum outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)
5
0
5 6 3 2 14 15 12 11 3
P
14
A0 B0 A1 B1 A2 B2 A3 B3 12 3
0 4
1
CIN COUT
7 9
6 0 13
0 1 2 3 2 3 10
Q
15
11 3
4 1 13 10
7 CI CO 9
VCC=Pin 16
GND=Pin 8 SF00853 SF00854
1989 Mar 03 2 853-0364 95944

LOGIC DIAGRAM
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9
COUT
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B3
12 10
A3 3
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15
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13
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B1
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1
3 1
A1
6
B0
4
5 0
A0
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7
VCC=Pin 16 CIN
GND=Pin 8 SF00855
FUNCTION TABLE
PINS CIN A0 A1 A2 A3 B0 B1 B2 B3 0 1 2 3 COUT Example:
1001
Logic levels L L H L H H L L H H H L L H 1010
10011
Active High 0 0 1 0 1 1 0 0 1 1 1 0 0 1
(10+9=19)
Active Low 1 1 0 1 0 0 1 1 0 0 0 1 1 0 (carry+5+6=12)
H = High voltage level
L = Low voltage level
1989 Mar 03 3
Figure A shows how to make a 3-bit adder. Tying the operand inputs they do not influence 2. Similarly, when A2 and B2 are the same,
of the fourth adder (A3, B3) Low makes 3 dependent only on, and the carry into the third stage does not influence the carry out of the
equal to, the carry from the third adder. Using somewhat the same third stage. Figure C shows a method of implementing a 5-input
principle, Figure B shows a way of dividing the 74F283 into a 2-bit encoder where the inputs are equally weighted. The outputs 0, 1
and a 1-bit adder. The third stage adder (A2, B2, 2) is used as and 2 present a binary number of inputs I0I4 that are true.
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means of getting a carry (C10) signal into the fourth stage adder (via Figure D shows one method of implementing a 5-input majority gate.
A2 and B2) and bringing out the carry from the second stage on 2. When three or more of the inputs I0I4 are true, the output M4 is
Note that as long as A2 and B2 are the same, whether High or Low, true.
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APPLICATIONS
C10
A0 B0 A1 B1 A10 B10
L
A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3
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CIN COUT CIN CIN COUT C11
0 1 2 3 0 1 2 3
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0 1 C2 10
a A. 3-bit Adder B. 2-bit and 1-bit Adder
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I2
ad I0 I1 L I3 I4 I0 I1
I2
I3 I4
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A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3
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CIN COUT CIN COUT
0 1 2 3 0 1 2 3
20 21 22
C. 5-input Encoder M4
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D. 5-input Majority Gate

SF00856
1989 Mar 03 4
ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
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VCC Supply voltage 0.5 to +7.0 V
VIN Input voltage 0.5 to +7.0 V
IIN Input current 30 to +5 mA
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VOUT Voltage applied to output in High output state 0.5 to VCC V
IOUT Current applied to output in Low output state 40 mA
Tamb Operating free-air temperature range 0 to +70 C
Tstg Storage temperature 65 to +150 C
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RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL PARAMETER UNIT
Min Nom Max
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VCC Supply voltage 4.5 5.0 5.5 V
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VIH
VIL
2.0
0.8
V
V
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IIK Input clamp current 18 mA
IOH
ad High-level output current 1 mA

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IOL Low-level output current 20 mA

Tamb Operating free-air temperature range 0 70 C
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DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONSNO TAG TYP UNIT
MIN NO TAG MAX
VCC = MIN, VIL = MAX 10%VCC 2.5

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VOH
O High level output voltage
High-level V
VIH = MIN, IOH = MAX 5%VCC 2.7 3.4
VCC = MIN, VIL = MAX 10%VCC 0.30 0.50
VOL
O Low level output voltage
Low-level V
VIH = MIN, IOL = MAX 5%VCC 0.30 0.50
VIK Input clamp voltage VCC = MIN, II = IIK 0.73 1.2 V
II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 A
IIH High-level input current VCC = MAX, VI = 2.7V 20 A
CIN only 0.6 mA
IIL Low level input current
Low-level MAX VI = 0
VCC = MAX, 0.5V
5V
An, Bn 1.2 mA
IOS Short-circuit output currentNO TAG VCC = MAX 60 150 mA
ICC Supply current (total)4 VCC = MAX 40 55 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. ICC should be measured with all outputs open and the following conditions:
Condition1: all inputs grounded
Condition 2: all B inputs Low, other inputs at 4.5V
Condition 3: all inputs at 4.5V
1989 Mar 03 5
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb= +25C Tamb = 0C to +70C
TEST VCC = +5
+5.V
V +5 V 10%
VCC = +5.V
SYMBOL PARAMETER UNIT
a
CONDITIONS CL = 50pF, CL = 50pF,
RL = 500 RL = 500
MIN TYP MAX MIN MAX
tPLH Propagation delay 3.5 7.0 9.5 3.0 10.5 ns
Waveform 1, 2
CIN to i
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tPHL 4.0 7.0 9.5 3.5 10.5 ns
Waveform 1, 2
tPHL Ai or Bi to i 3.5 7.0 9.5 3.5 10.5 ns
Waveform 2
tPHL CIN to COUT 3.0 5.4 7.0 2.5 8.0 ns
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Waveform 1, 2
tPHL Ai or Bi to COUT 2.5 5.3 7.0 2.5 8.0 ns
AC WAVEFORMS
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For all waveforms, VM=1.5V.
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a
Ai, Bi, CIN VM VM
Ai, Bi, CIN VM VM
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tPLH tPHL tPHL tPLH
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i, COUT VM VM
i, COUT VM VM
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SF00857 SF00858
Waveform 1. Propagation Delay Waveform 2. Propagation Delay

Operands and Carry Inputs to Outputs Operands and Carry Inputs to Outputs
TEST CIRCUIT AND WAVEFORM
VCC tw AMP (V)

90% 90%
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NEGATIVE
VM VM
PULSE
10% 10%
VIN VOUT 0V
PULSE D.U.T.
GENERATOR tTHL (tf ) tTLH (tr )
RT CL RL tTLH (tr ) tTHL (tf )

AMP (V)
90% 90%
POSITIVE
PULSE VM VM
Test Circuit for Totem-Pole Outputs 10% 10%

tw 0V
DEFINITIONS: Input Pulse Definition

RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value. INPUT PULSE REQUIREMENTS
CL = Load capacitance includes jig and probe capacitance; family
see AC ELECTRICAL CHARACTERISTICS for value. amplitude VM rep. rate tw tTLH tTHL
RT = Termination resistance should be equal to ZOUT of
74F 3.0V 1.5V 1MHz 500ns 2.5ns 2.5ns
pulse generators.
SF00006
1989 Mar 03 6
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)L4C383
DEVICES INCORPORATED 16-bit Cascadable ALU (Extended Set)
FEATURES DESCRIPTION
High-Speed (15ns), Low Power The L4C383 is a flexible, high speed, bit result (F). Five select lines control
16-bit Cascadable ALU cascadable 16-bit Arithmetic and Logic the ALU and provide 19 arithmetic and
a
Extended Function Set Unit. The L4C383 is capable of 13 logical functions. Registers are
(32 Advanced ALU Functions) performing up to 32 different provided on both the ALU inputs and
All Registers Have a Bypass Path arithmetic or logic functions. the output, but these may be bypassed
for Complete Flexibility under user control. An internal feed-
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The L4C383 can be cascaded to perform back path allows the registered ALU
Replaces IDT7383 32-bit or greater operations. See
68-pin PLCC, J-Lead Cascading the L4C383 on the next output to be routed to one or both of
page. the ALU inputs, accommodating chain
operations and accumulation.
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ARCHITECTURE ALU OPERATIONS
The L4C383 operates on two 16-bit The S4S0 lines specify the operation to
operands (A and B) and produces a 16- be
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their select codes are shown in Table 1.
a
a
L4C383 BLOCK DIAGRAM
ALU STATUS
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ad A15-A0 B15-B0
The ALU provides Overflow and Zero
status bits. A Carry output is also
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16 16
provided for cascading multiple

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ENA A REGISTER B REGISTER ENB devices, however it is only defined for

the 19 arithmetic functions. The ALU
sets the Zero output when all 16 output
bits are zero. The N, C16 and OVF flags
FTAB for the arithmetic operations are
FFFFH FFFFH defined in Table 2.
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5
S4-0 OPERAND REGISTERS
The L4C383 has two 16-bit wide input
registers for operands A and B. These
4 registers are rising edge triggered by a
common clock. The A register is
N, C16 ALU C0
OVF, Z
16
enabled for input by setting the ENA
control LOW, and the B register is
RESULT REGISTER ENF enabled for input by setting the ENB
control LOW. When either the ENA
control or ENB control is HIGH, the
data in the corresponding input register
FTF will not change.
16
This architecture allows the L4C383 to
OE accept arguments from a single 16-bit
data bus. For those applications that do
not require registered inputs, both the
16
CLK TO ALL REGISTERS F15-F0 A and B operand registers can be

bypassed with the FTAB control line.
Arithmetic Logic Units
1 08/16/2000LDS.383-E
L4C383
16-bit Cascadable ALU (Extended Set)
TABLE 1. ALU FUNCTIONS TABLE 2. ALU STATUS FLAGS

S4-S0 FUNCTION Bit Carry Generate = gi = AiBi for i = 0 ... 15
00000 A + B + C0 Bit Carry Propagate = pi = Ai + Bi for i = 0 ... 15
00001 A OR B
P0 = p0
00010 A + B + C0
Pi = pi (Pi1) for i = 1 ... 15
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00011 A + B + C0
00100 A + C0 and
00101 A OR F
G0 = g0
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00110 A 1 + C0
Gi = gi + pi (Gi1) for i = 1 ... 15
00111 A + C0 Ci = Gi1 + Pi1 (C0) for i = 1 ... 15
01000 A + F + C0
01001 A OR F then
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01010 A + F + C0 C16 = G15 + P15C0
01011 A + F + C0 OVF = C15 XOR C16
01100 F + B + C0 Zero = All Output Bits Equal Zero
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01101 A OR B N = Sign Bit of ALU Operation
a
01110
01111
a F + B + C0
F + B + C0 OUTPUT REGISTER
The output of the ALU drives the input of flags
common to both devices. The Zero output
should be logically ANDed to
r
10000 A XOR B
produce the Zero flag for the 32-bit result.
ad
10001 A AND B a 16-bit register. This rising-edge-
triggered register is clocked by the same significantand
The OVF C16 outputs of the most
t
10010 A AND B
clock as the input registers. When the slice are valid for the 32-bit
result.
ec
10011 A XNOR B
ENF control is LOW, data from the ALU
10100 A XOR F will be clocked into the output register. Propagation delay calculations for this
10101 A AND F By disabling the output register, interme- configuration require two steps: First
diate results can be held while loading determine the propagation delay from the
10110 A AND F
new input operands. Three-state drivers input of interest to the C16 output of the
10111 ALL 1's + C0
controlled by the OE input allow the lower slice. Add this number to the delay
11000 B + C0 L4C383 to be configured in a single from the C0 input of the upper slice to the
El
11001 A AND B bidirectional bus system. output of interest (of the C0 setup time, if
the F register is used). The sum gives the
11010 B + C0 The output register can be bypassed by overall input-to-output delay (or setup
11011 B 1 + C0 asserting the FTF control signal (FTF = time) for the 32-bit configuration. This
11100 F + C0 HIGH). When the FTF control is asserted, method gives a conservative result, since
output data is routed around the output the C16 output is very lightly loaded.
11101 A OR B
register, however, it continues to function Formulas for calculation of all critical
11110 F 1 + C0 normally via the ENF control. The delays for a 32-bit system are shown in
11111 F + C0 contents of the output register will again Figures 4A through 4D.
be available on the output pins if FTF is
When the FTAB control is asserted released. Cascading to greater than 32 bits can be
(FTAB = HIGH), data is routed accomplished by simply connecting the
around the A and B input registers; CASCADING THE L4C383 C16 output of each slice to the C0 input of
however, they continue to function the next more significant slice.
normally via the ENA and ENB Cascading the L4C383 to 32 bits is Propagation delays are calculated as
controls. The contents of the input accomplished simply by connecting the for the 32-bit case, except that the C0
registers will again be available to the C16 output of the least significant slice to to C16 delays for all intermediate slices
ALU if the FTAB control is released. the C0 input of the most sig-nificant slice. must be added to the overall delay for
The S4-S0, ENA, ENB, and ENF lines are each path.

2 08/16/2000LDS.383-E
L4C383
FIGURE 4A. FTAB = 0, FTF = 0

From To Calculated Specification Limit
Clock F = Same as 16-bit case
Clock Other = (Clock C16) + (C0 Out)
C0 Other = (C0 C16) + (C0 Out)
S4-S0 Other = (S4-S0 C16) + (C0 Out)
A, B Setup time = Same as 16-bit case
a
C0 Setup time = (C0 C16) + (C0 Setup time)
S4-S0 Setup time = (S4-S0 C16) + (C0 Setup time)
ENA, ENB, ENF Setup time = Same as 16-bit case
Minimum cycle time = (Clock C16) + (C0 Setup time)
Ap git ic A 31 -A 16
D
Q
B 31 -B 16
D
Q
A 15 -A 0
D
Q
B 15 -B 0
D
Q
CLOCK
Di n
C0, S 4 S 0
A B A B
C0 C 16 C0
F F
lic l
a
a MOST 16
D
Q
CLOCK
16
D
Q
CLOCK
LEAST
r
SIGNIFICANT SIGNIFICANT
ad SLICE F 31 -F 16 F 15 -F 0 SLICE
t
ec
FIGURE 4B. FTAB = 0, FTF = 1

Clock F = (Clock C16) + (C0 F)
Clock Other = (Clock C16) + (C0 Out)
C0 F = (C0 C16) + (C0 F)
S4-S0 F = (S4-S0 C16) + (C0 F)
El
S4-S0 Other = (S4-S0 C16) + (C0 Out)

A, B Setup time = Same as 16-bit case
A 31 -A 16 B 31 -B 16 A 15 -A 0 B 15 -B 0
D D D D
CLOCK
Q Q Q Q
C0, S 4 S 0
A B A B
C0 C 16 C0
F F
MOST 16 16 LEAST
SLICE F 31 -F 16 F 15 -F 0 SLICE

3 08/16/2000LDS.383-E
L4C383
FIGURE 4C. FTAB = 1, FTF = 0

Clock F = Same as 16-bit case
A, B Other = (A, B C16) + (C0 Out)
S4-S0 Other = (S4-S0 C16) + (C0 Out)
A, B Setup time = (A, B C16) + (C0 Setup time)
a
Ap git ic
(F register accumulate loop)
A 31 -A 16 B 31 -B 16 A 15 -A 0 B 15 -B 0
Di n C0, S 4 S 0
A B A B
C0 C 16 C0
F F
lic l D CLOCK D CLOCK
a
Q Q
a MOST
SIGNIFICANT
16 16 LEAST
SIGNIFICANT
r
ad
t
ec
FIGURE 4D. FTAB = 1, FTF = 1

A, B F = (A, B C16) + (C0 F)
A, B Other = (A, B C16) + (C0 Out)
C0 F = (C0 C16) + (C0 F)
S4-S0 F = (S4-S0 C16) + (C0 F)
El
S4-S0 Other = (S4-S0 C16) + (C0 Out)

A, B Setup time = (A, B C16) + (C0 Setup time)
(F register accumulate loop)
A 31 -A 16 B 31 -B 16 A 15 -A 0 B 15 -B 0
C0, S 4 S 0
A B A B
C0 C 16 C0
F F
MOST 16 16 LEAST

4 08/16/2000LDS.383-E
L4C383
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... 65C to +150C

Operating ambient temperature ........................................................................................... 55C to +125C
VCC supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V
a
Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
Ap git ic
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Di n
Mode Temperature Range (Ambient) Supply Voltage
Active Operation, Commercial 0C to +70C 4.75 V VCC 5.25 V
lic l Active Operation, Military 55C to +125C 4.50 V VCC 5.50 V
a
a
r
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
ad
t
Symbol Parameter Test Condition Min Typ Max Unit

ec
VOH Output High Voltage VCC = Min., IOH = 2.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V
VIH Input High Voltage 2.0 VCC V
VIL Input Low Voltage (Note 3) 0.0 0.8 V

El
IIX Input Current Ground VIN VCC (Note 12) 20 A
IOZ Output Leakage Current Ground VOUT VCC (Note 12) 20 A
ICC1 VCC Current, Dynamic (Notes 5, 6) 15 30 mA
ICC2 VCC Current, Quiescent (Note 7) 1.5 mA

5 08/16/2000LDS.383-E
L4C383
SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0C to +70C)
GUARANTEED MAXIMUM C1234567890123456789012345678901212345678901234567890

OMBINATIONAL DELAYS Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
To Output 1234567890123456789012345678901212345678901234567890
L4C383-55* L4C383-40*
1234567890123456789012345678901212345678901234567890 L4C383-26
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
From Input 1234567890123456789012345678901212345678901234567890
F15-F0 N OVF, Z C16 F15-F0 N OVF, Z C16 F15-F0
1234567890123456789012345678901212345678901234567890 N OVF, Z C16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
a
FTAB = 0, FTF = 0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
32 38 53 36 26 30 44 32 22 22 26 22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0 1234567890123456789012345678901212345678901234567890
34 22 28 20
1234567890123456789012345678901212345678901234567890
18 18
1234567890123456789012345678901212345678901234567890
Ap git ic
S4-S0 1234567890123456789012345678901212345678901234567890
42 42 42 32 34 35
1234567890123456789012345678901212345678901234567890
22 22 22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0, FTF = 1 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock 1234567890123456789012345678901212345678901234567890
56 38 53 36 46 30 44 32
1234567890123456789012345678901212345678901234567890
28 22 26 22
C0 1234567890123456789012345678901212345678901234567890
37 34 22 30 28 20
1234567890123456789012345678901212345678901234567890 22 18 18
Di n
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 55 42 42 42 40 32 34 35
1234567890123456789012345678901212345678901234567890 26 22 22 22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 1, FTF = 0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
lic l
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
36 46 37 30 40 32
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
22 22 22
a
Clock
C0
a 1234567890123456789012345678901212345678901234567890
32 26
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
34 22 28 20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
22

18

18
r
S4-S0 1234567890123456789012345678901212345678901234567890
42 42 42 32 34 35
1234567890123456789012345678901212345678901234567890
22 22 22
ad
FTAB = 1, FTF = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
t
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
55 36 46 37 40 30 40 32
1234567890123456789012345678901212345678901234567890
26 22 22 22
ec
Clock 1234567890123456789012345678901212345678901234567890
56 38 53 36 46 30 44 32
1234567890123456789012345678901212345678901234567890 28 22 26 22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0 37 34 22 30 28 20
1234567890123456789012345678901212345678901234567890 22 18 18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 55 42 42 42 40 32 34 35
1234567890123456789012345678901212345678901234567890 26 22 22 22
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
L4C383-55* L4C383-40* L4C383-26
El
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1
1234567890123456789012345678901212345678901234567890 FTAB = 0 FTAB = 1
1234567890123456789012345678901212345678901234567890
Input 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
8 2 35 2 8 2 28 2 8 2 16 2
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0 1234567890123456789012345678901212345678901234567890
21 0 21 0 16 0 16 0
1234567890123456789012345678901212345678901234567890
8 0 8 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 1234567890123456789012345678901212345678901234567890
44 0 44 0 32 0 32 0
1234567890123456789012345678901212345678901234567890
18 0 18 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
ENA, ENB, ENF 1234567890123456789012345678901212345678901234567890
10 2 10 2 10 2 10 2 8 2 8 2
12345678901234567890123456
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
12345678901234567890123456 CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456 12345678901234567890123456
12345678901234567890123456
L4C383-55* L4C383-40* L4C383-26
12345678901234567890123456 L4C383-55* L4C383-40* L4C383-26
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456 12345678901234567890123456
12345678901234567890123456
tENA 12345678901234567890123456
12345678901234567890123456
20 18 16 Minimum Cycle Time12345678901234567890123456
12345678901234567890123456
43 34 20
12345678901234567890123456
12345678901234567890123456 12345678901234567890123456
12345678901234567890123456
tDIS 12345678901234567890123456
12345678901234567890123456
20 18 16 Highgoing Pulse 12345678901234567890123456
12345678901234567890123456
15 10 10
12345678901234567890123456
12345678901234567890123456
123456789012345678901234 Lowgoing Pulse 12345678901234567890123456
12345678901234567890123456
15 10 10
123456789012345678901234
123456789012345678901234 12345678901234567890123456
123456789012345678901234
*DISCONTINUED SPEED GRADE
6 08/16/2000LDS.383-E
L4C383
SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0C to +70C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes12345678901234567890123456

9, 10 (ns)
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
To Output L4C383-20 L4C383-15*
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
From Input F15-F0 N OVF, Z C16 12345678901234567890123456
F15-F0 N OVF, Z C16
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
a
FTAB = 0, FTF = 0 12345678901234567890123456
12345678901234567890123456
Clock 11 20 20 20
12345678901234567890123456
12345678901234567890123456
11 15 15 15
12345678901234567890123456
12345678901234567890123456
C0 14 14 12345678901234567890123456
13 13
12345678901234567890123456
12345678901234567890123456
Ap git ic
S4-S0 18 20 18 12345678901234567890123456
14 15 14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
FTAB = 0, FTF = 1 12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Clock 20 20 20 20 12345678901234567890123456
15 15 15 15
12345678901234567890123456
C0 18 14 14 12345678901234567890123456
14 13 13
12345678901234567890123456
Di n
12345678901234567890123456
12345678901234567890123456
S4-S0 20 18 20 18 15 14 15 14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
FTAB = 1, FTF = 0 12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
lic l
A15-A0, B15-B0 16 20 17 12345678901234567890123456
14 15 14
12345678901234567890123456
12345678901234567890123456
a
Clock
C0
a 11

14

14
12345678901234567890123456
11
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
13 13
12345678901234567890123456
12345678901234567890123456
r
S4-S0 18 20 18 12345678901234567890123456
14 15 14
12345678901234567890123456
ad
FTAB = 1, FTF = 1
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
t
12345678901234567890123456
12345678901234567890123456
A15-A0, B15-B0 20 16 20 17 12345678901234567890123456
15 14 15 14
12345678901234567890123456
ec
Clock 20 20 20 20 12345678901234567890123456
12345678901234567890123456
15 15 15 15
12345678901234567890123456
12345678901234567890123456
C0 18 14 14 14 13 13
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
S4-S0 20 18 20 18 15 14 15 14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
L4C383-20 L4C383-15*
El
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
FTAB = 0 FTAB = 1 12345678901234567890123456
FTAB = 0 FTAB = 1
12345678901234567890123456
12345678901234567890123456
Input Setup Hold Setup Hold 12345678901234567890123456
12345678901234567890123456
Setup Hold Setup Hold
12345678901234567890123456
12345678901234567890123456
A15-A0, B15-B0 5 0 14 0 12345678901234567890123456
12345678901234567890123456
5 0 12 0
12345678901234567890123456
12345678901234567890123456
C0 12 0 12 0 12345678901234567890123456
12345678901234567890123456
10 0 10 0
12345678901234567890123456
12345678901234567890123456
S4-S0 15 0 15 0 12345678901234567890123456
12345678901234567890123456
12 0 12 0
12345678901234567890123456
12345678901234567890123456
ENA, ENB, ENF 5 0 5 0 12345678901234567890123456
12345678901234567890123456
5 0 5 0
12345678901234567890123456
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)

1234567890123 CLOCK CYCLE TIME AND PULSE 1234567890123
WIDTH Notes 9, 10 (ns)
1234567890123 1234567890123
L4C383-20 1234567890123
L4C383-15*
1234567890123 L4C383-20 1234567890123
L4C383-15*
1234567890123
1234567890123
1234567890123 1234567890123
1234567890123
tENA 8 1234567890123
1234567890123
6 Minimum Cycle Time 18 1234567890123
1234567890123
14
1234567890123
1234567890123 1234567890123
1234567890123
tDIS 8 1234567890123
1234567890123
6 Highgoing Pulse 5 1234567890123
1234567890123
4
1234567890123
1234567890123
123456789012345678901234 Lowgoing Pulse 5 1234567890123
1234567890123
4
123456789012345678901234
123456789012345678901234 1234567890123
123456789012345678901234
7 08/16/2000LDS.383-E
L4C383
SWITCHING CHARACTERISTICS MILITARY OPERATING RANGE (55C to +125C)

123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
To Output 123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C383-65* L4C383-45* L4C383-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
From Input 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
F15-F0 N OVF, Z C16 F15-F0 N OVF, Z C16 F15-F0 N OVF, Z C16
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
a
FTAB = 0, FTF = 0 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock 37 44 63 45 28 34 50 34 26 28 34 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
42 25 32 23 22 22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Ap git ic
S4-S0 123456789012345678901234567890121234567890123456789012345678901212345678901234
48 48 48 38 38 38 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0, FTF = 1 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock 123456789012345678901234567890121234567890123456789012345678901212345678901234
68 44 63 45 56 34 50 34 34 28 34 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
42 42 25 32 32 23 26 22 22
Di n
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S4-S0 66 48 48 48 46 38 38 38 30 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 1, FTF = 0 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
lic l
A15-A0, B15-B0 123456789012345678901234567890121234567890123456789012345678901212345678901234
44 56 44 32 46 36 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
a
Clock
C0
a 123456789012345678901234567890121234567890123456789012345678901212345678901234
37 28 26
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
42 25 32 23 22 22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
r
S4-S0 123456789012345678901234567890121234567890123456789012345678901212345678901234
48 48 48 38 38 38 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
ad 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
t
FTAB = 1, FTF = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
A15-A0, B15-B0 123456789012345678901234567890121234567890123456789012345678901212345678901234
65 44 56 44 45 32 46 36 30 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
ec
Clock 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
68 44 63 45 56 34 50 34 34 28 34 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0 42 42 25 32 32 23 26 22 22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S4-S0 66 48 48 48 46 38 38 38 30 28 28 28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C383-65* L4C383-45* L4C383-30*
El
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Input Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
A15-A0, B15-B0 123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
10 3 43 3 8 3 33 3 8 3 20 3
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0 123456789012345678901234567890121234567890123456789012345678901212345678901234
25 0 25 0 20 0 20 0 12 0 12 0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S4-S0 123456789012345678901234567890121234567890123456789012345678901212345678901234
50 0 50 0 36 0 36 0 20 0 20 0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
ENA, ENB, ENF 123456789012345678901234567890121234567890123456789012345678901212345678901234
12 2 12 2 10 2 10 2 10 2 10 2
123456789012345678901234567890121234567890123456789012345678901212345678901234
TRI-STATE1234567890123456789012345678901212345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
1234567890123456789012345678901212345 CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456789012123456
1234567890123456789012345678901212345
1234567890123456789012345678901212345 12345678901234567890123456789012123456
12345678901234567890123456789012123456
1234567890123456789012345678901212345
L4C383-65* L4C383-45* L4C383-30*
1234567890123456789012345678901212345 12345678901234567890123456789012123456
L4C383-65* L4C383-45* L4C383-30*
12345678901234567890123456789012123456
1234567890123456789012345678901212345
1234567890123456789012345678901212345 12345678901234567890123456789012123456
tENA 1234567890123456789012345678901212345
22 20 18 Minimum Cycle Time12345678901234567890123456789012123456
12345678901234567890123456789012123456
52 38 26
1234567890123456789012345678901212345
1234567890123456789012345678901212345 12345678901234567890123456789012123456
12345678901234567890123456789012123456
tDIS 1234567890123456789012345678901212345
1234567890123456789012345678901212345
22 20 18 Highgoing Pulse 12345678901234567890123456789012123456
12345678901234567890123456789012123456
20 15 12
1234567890123456789012345678901212345 12345678901234567890123456789012123456
12345678901234567890123456789012123456
123456789012345678901234 Lowgoing Pulse 12345678901234567890123456789012123456
12345678901234567890123456789012123456
20 15 12
123456789012345678901234
123456789012345678901234 12345678901234567890123456789012123456
123456789012345678901234
8 08/16/2000LDS.383-E
L4C383
SWITCHING CHARACTERISTICS MILITARY OPERATING RANGE (55C to +125C)

1234567890123456789012345678901212345678901234567890
To Output 1234567890123456789012345678901212345678901234567890
L4C383-25* L4C383-20*
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
From Input 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
F15-F0 N OVF, Z C16 F15-F0 N OVF, Z C16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
a
FTAB = 0, FTF = 0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock 14 24 24 24 14 20 20 20
1234567890123456789012345678901212345678901234567890
C0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
18 18 16 16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Ap git ic
S4-S0 1234567890123456789012345678901212345678901234567890
22 24 22 18 20 18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0, FTF = 1 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock 1234567890123456789012345678901212345678901234567890
25 24 24 24 20 20 20 20
1234567890123456789012345678901212345678901234567890
C0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
21 18 18 17 16 16
Di n
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 25 22 24 22 20 18 20 18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 1, FTF = 0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
lic l
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
20 25 22 17 20 17
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
a
Clock
C0
a 1234567890123456789012345678901212345678901234567890
14 14
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
18 18 16 16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
r
S4-S0 1234567890123456789012345678901212345678901234567890
22 24 22 18 20 18
1234567890123456789012345678901212345678901234567890
ad 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
t
FTAB = 1, FTF = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
25 20 25 22 20 17 20 17
1234567890123456789012345678901212345678901234567890
ec
Clock 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25 24 24 24 20 20 20 20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0 21 18 18 17 16 16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 25 22 24 22 20 18 20 18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
L4C383-25* L4C383-20*
El
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Input Setup Hold Setup Hold Setup Hold Setup Hold
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0 1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
7 2 14 2 6 2 12 2
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0 1234567890123456789012345678901212345678901234567890
14 0 14 0 12 0 12 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S4-S0 1234567890123456789012345678901212345678901234567890
19 0 19 0 16 0 16 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
ENA, ENB, ENF 1234567890123456789012345678901212345678901234567890
7 0 7 0 6 0 6 0
1234567890123456789012345678901212345678901234567890
TRI-STATE1234567890123456789012345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns) CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456
1234567890123456789012345
1234567890123456789012345 12345678901234567890123456
12345678901234567890123456
1234567890123456789012345
L4C383-25* L4C383-20*
1234567890123456789012345 12345678901234567890123456
L4C383-25* L4C383-20*
12345678901234567890123456
1234567890123456789012345
1234567890123456789012345 12345678901234567890123456
tENA 1234567890123456789012345
14 10 Minimum Cycle Time12345678901234567890123456
12345678901234567890123456
20 18
1234567890123456789012345
1234567890123456789012345 12345678901234567890123456
12345678901234567890123456
tDIS 1234567890123456789012345
1234567890123456789012345
14 10 Highgoing Pulse 12345678901234567890123456
12345678901234567890123456
8 6
1234567890123456789012345 12345678901234567890123456
12345678901234567890123456
123456789012345678901234 Lowgoing Pulse 12345678901234567890123456
12345678901234567890123456
8 6
123456789012345678901234
123456789012345678901234 12345678901234567890123456
123456789012345678901234
9 08/16/2000LDS.383-E
L4C383
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with 11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ation of these products at values beyond output reference levels of 1.5 V (except with datasheet loads. For the tDIS test,
those indicated in the Operating Condi- tDIS test), and input levels of nominally the transition is measured to the
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a 200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
a
tended periods may affect reliability. specified IOH and IOL at an output 10mA loads. The balancing volt-
2. The products described by this spec- voltage of VOH min and VOL max age, V TH, is set at 3.5 V for Z-to-0
ification include internal circuitry de- respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
Ap git ic
signed to protect the chip from damag- bridge with upper and lower current to-1 and 1-to-Z tests.
ing substrate injection currents and ac- sources of IOH and IOL respectively, 12. These parameters are only tested at
cumulations of static charge. Neverthe- and a balancing voltage of 1.5 V may be the high temperature extreme, which is
less, conventional precautions should used. Parasitic capacitance is 30 pF the worst case for leakage current.
be observed during storage, handling, minimum, and may be distributed.
Di n
and use of these circuits in order to This device has high-speed outputs ca- FIGURE A. OUTPUT LOADING CIRCUIT
avoid exposure to excessive electrical pable of large instantaneous current
stress values. pulses and fast turn-on/turn-off times.
lic l
3. This device provides hard clamping of As a result, care must be exercised in the S1
a
testing of this device. The following
DUT
a
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at 0.6 V and
measures are recommended:
a. A 0.1 F ceramic capacitor should be
CL VTH
IOL
r
IOH
VCC + 0.6 V. The device can withstand installed between VCC and Ground
ad
indefinite operation with inputs in the leads as close to the Device Under Test
t
range of 0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors FIGURE B. THRESHOLD LEVELS
tion will not be adversely affected, how- should be installed between device VCC
ec
tENA tDIS
ever, input current levels will be well in and the tester common, and device OE 1.5 V 1.5 V
excess of 100 mA. ground and tester common. Z 0 3.5V Vth
4. Actual test conditions may vary from b. Ground and VCC supply planes
1.5 V VOL* 0.2 V
0 Z
those designated but operation is guar- must be brought directly to the DUT 0.2 V
1 Z
anteed as specified. socket or contactor fingers.

1.5 V VOH*
Z 1 0V Vth
5. Supply current for a given applica- c. Input voltages should be adjusted to

VOL* Measured VOL with IOH = 10mA and IOL = 10mA
El
VOH* Measured VOH with IOH = 10mA and IOL = 10mA
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F levels relative to the DUT ground pin.
where 4
10. Each parameter is shown as a min-
N = total number of device outputs imum or maximum value. Input re-
C = capacitive load per output quirements are specified from the point
V = supply voltage of view of the external system driving
F = clock frequency the chip. Setup time, for example, is
specified as a minimum since the exter-
6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case re-
rate. quirements of all parts. Responses from
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
VCC or Ground, no load. delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
but not 100% tested. any device always provides data within
that time.

10 08/16/2000LDS.383-E
L4C383
ORDERING INFORMATION 1234567890123456789012345678901212345678901234567

1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
68-pin 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
68-pin
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1 2 3 4 5 6 7 8
1234567890123456789012345678901212345678901234567
9 10 11
1234567890123456789012345678901212345678901234567
B15
B14
B13
B12
B11
B10
A8
A7
A6
A5
A4
A3
A2
A1
A0
B9
B8
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
A
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 A8 A7 A5 A3 A1 B15 B13 B11 B9
A9 B7
1234567890123456789012345678901212345678901234567
10 60
a
A10 11 59 B6 1234567890123456789012345678901212345678901234567
B
1234567890123456789012345678901212345678901234567
A10 A9 A6 A4 A2 A0 B14 B12 B10 B8 B7
A11 12 58 B5 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
C
A12 13 57 B4 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
A12 A11 B5 B6
A13 14 56 B3 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
D
1234567890123456789012345678901212345678901234567
Ap git ic
A14 15 55 B2 A14 A13 B3 B4
A15 16 54 B1 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
E
CLK 17 53 B0 1234567890123456789012345678901212345678901234567
CLK A15
Top View
1234567890123456789012345678901212345678901234567 B1 B2
Top 1234567890123456789012345678901212345678901234567
Through Package
VCC 18
View
52 ENA 1234567890123456789012345678901212345678901234567
F
1234567890123456789012345678901212345678901234567
GND VCC (i.e., Component Side Pinout) ENA B0
GND 19 51 ENB
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
G
C16 FTAB
1234567890123456789012345678901212345678901234567
20 50
1234567890123456789012345678901212345678901234567
Di n GND C16 FTAB ENB
GND S4
1234567890123456789012345678901212345678901234567
21 49
N 22 48 S3 1234567890123456789012345678901212345678901234567
H
1234567890123456789012345678901212345678901234567
ZERO N S3 S4
ZERO 23 47 S2 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
J
OVF 24 46 S1 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
ENF OVF S1 S2
1234567890123456789012345678901212345678901234567
lic l ENF
FTF
25
26 44
45 S0
C0 1234567890123456789012345678901212345678901234567
K
1234567890123456789012345678901212345678901234567
FTF OE F14 F12 F10 F8 F6 F4
1234567890123456789012345678901212345678901234567
F2 C0 S0
a
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
a 1234567890123456789012345678901212345678901234567
L
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
OE
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
F15 F13 F11 F9 F7 F5 F3 F1 F0

1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
r
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
ad 1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
t
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
ec
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Discontinued Package
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Plastic J-Lead Chip Carrier Ceramic Pin Grid Array
Speed (J2) (G1)
0C to +70C C OMMERCIAL SCREENING
El
26 ns L4C383JC26
20 ns L4C383JC20
55C to +125C C OMMERCIAL SCREENING
55C to +125C MIL-STD-883 C OMPLIANT

11 08/16/2000LDS.383-E
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Captulo 6.- Dispositivos de Memoria
a
6.1.- Clasificacin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2
Ap git ic
6.2.- Memoria esttica de acceso aleatorio (RAM). . . . . . . . . . . . . . . . . . . . 6.2
6.3.- Memorias dinmicas de acceso aleatorio (DRAM). . . . . . . . . . . . . . . 6.5
6.4.- Memoria de acceso aleatorio de slo lectura (RMM). . . . . . . . . . . . . . 6.6
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V1.0 6.1
6.1.- Clasificacin
Industrialmente existen muchos tipos de memorias que pueden clasificarse segn
varios criterios. Veamos algunos de ellos.
Tipo de acceso:
a
Directo. La informacin se localiza por medio de un nmero que se
denomina direccin.
Ap git ic
Asociativo. La localizacin se hace por medio del contenido o parte de l.
Formato de la informacin:
Di n
Paralelo. Todos los bits de la informacin se obtiene simultneamente en el
mismo instante temporal.
lic l Serie. Los bits de la informacin se obtienen a lo largo de un periodo de
a
a tiempo bit a bit.
r
ad
Almacenamiento:
t
Voltil. En este caso la informacin desaparece cuando cesa la alimentacin

ec
del dispositivo.
No voltil. La informacin bo desaparece auque no haya alimentacin.
Funcionamiento:
El
Esttico. La informacin se mantiene siempre que haya alimentacin en el

dispositivo.
Dinmico. Es necesario refrescar la informacin para mantenerla an con
alimentacin en el dispositivo.
Existen otra muchas posibilidades que no se citan aqu ya que este documento solo es
una introduccin.
6.2.- Memoria esttica de acceso aleatorio (RAM).

El desarrollo de este apartado est realizado en el captulo 4 del libro Sistemas
Basados en Microprocesadores junto con el captulo 2 del libro Diseo Prctico de
V1.0 6.2
SBMs (ver la bibliografa).

Sin embargo, con el objetivo de situarnos en dispositivos comerciales, en la figura
6.1 se muestra el esquema digital de una memoria de 2Mb.
a
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Figura 6.1. Esquema digital de una memoria RAM esttica de 2Mbits

organizada en 256Kbx8.
Este esquema corresponde al modelo CY7C1010DV33 del fabricante Cypress.

Como puede verse est organizada en 256 bytes a los que se accede por medio de 18
El
seales de direccin (A17 - A0).

La figura 6.2 muestra los cronogramas funcionales de este dispositivo para el ciclo
de lectura. El primero de ellos es para el caso en el que las seales /OE y /CE est
permanentemente a nivel bajo. As podemos ver cuanto es el tiempo de acceso desde
las direcciones. En el segundo, las seales /OE y /CE determinan los parmetros
temporales. En la referencia CY7C1010DV33 se encuentran las tablas con los valores
de las cotas de estos cronogramas.
V1.0 6.3
a
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Di n
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a
a
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ad
t
Figura 6.2. Cronogramas del ciclo de lectura.

ec
La figura 6.3 muestra los cronogramas de escritura de este dispositivo. Observad

que as como en el ciclo de lectura, el flanco de bajada de la seal /OE o /CE es
desde donde se cuenta el tiempo de lectura, en los ciclos de escritura el dato ha de
estar presente un tiempo antes (tSD) y un tiempo despus (tHD) del flanco de subida
de la seal /WE, respecto al cual se acotan los tiempos.
El
V1.0 6.4
a
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Di n
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a
a
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El
Figura 6.3. Cronogramas del ciclo de escritura.
6.3.- Memorias dinmicas de acceso aleatorio (DRAM).

Las memorias RAM dinmicas (DRAM) forman un grupo muy importante dentro
de la memorias electrnicas y deben de ser estudiadas detalladamente debido a su
complejidad funcional. En el captulo 4 del el libro Sistemas Basados en
Microprocesadores se hace una introduccin a los modos bsicos de funcionamiento
de estos dispositivo y su control. Este tipo de memoria es el que se utiliza en
ordenadores que requieren una alta capacidad de almacenamiento RAM como lps
ordenadores personales y superiores. Sin embargo no es frecuente encontrarlas en
sistemas industriales de control basados en :C.
V1.0 6.5
6.4.- Memoria de acceso aleatorio de slo lectura (RMM).

RMM (Read Mostly Memory, memorias de lectura principalmente) es el nombre
genrico que reciben las memoria conocidas como ROM (Read Only Memory) y PROM
(Progammable Read Only Memory). Este ltimo grupo entran una gran variedad de
memorias muy dependientes de evolucin de la tecnologa.
a
Las RMM tienen dos ciclos funcionales; el de lectura y el de programacin. El de
lectura es totalmente equivalente al de una memoria RAM (ver el apartado anterior).
El ciclo de programacin no es similar al de escritura de la memoria RAM en cuanto
que los requerimientos temporales y de control son totalmente diferentes.
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En las referencias de esta captulo tenemos el modelo AT28C040 del fabricante
Atmel, que es una memoria tipo EEPROM (Electrically Erasable and Programmable
Read Only Memory). Como puede verse en esta referencia el tiempo de acceso en
Di n
lectura es de 200 ns mientras que el tiempo de grabacin alcanza el valor de 10 ms.
Es por esto por lo que no se puede utilizar como memoria RAM de lectura y escritura.
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V1.0 6.6
CY7C1010DV33
2-Mbit (256 K 8) Static RAM
2-Mbit (256 K 8) Static RAM
Features Functional Description
a
Pin and function compatible with CY7C1010CV33 The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256 K words by 8 bits. Easy memory expansion is
High speed provided by an active LOW Chip Enable (CE), an active LOW
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tAA = 10 ns Output Enable (OE), and three-state drivers. Writing to the
Low active power device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
ICC = 90 mA at 10 ns
through I/O7) is then written into the location specified on the
Low CMOS standby power address pins (A0 through A17).
ISB2 = 10 mA Reading from the device is accomplished by taking Chip Enable
Di n
2.0 V data retention (CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
Automatic power down when deselected location specified by the address pins will appear on the I/O pins.
lic l TTL-compatible inputs and outputs The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
a
Easy memory expansion with CE and OE features
a HIGH), the outputs are disabled (OE HIGH), or during a Write
Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
r
TSOP II packages with center power and ground (revolutionary)
ad pinout.
t
Logic Block Diagram

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INPUT BUFFER IO0

A0
A1 IO1
A2
ROW DECODER
A3 IO2
SENSE AMPS
A4
A5 256K x 8 IO3
A6
A7 ARRAY IO4
A8
A9 IO5
A10
IO6
CE IO7
POWER
COLUMN DECODER
WE DOWN
OE
A14
A12
A13
A15
A16
A17
A11
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-00062 Rev. *E Revised December 2, 2013
CY7C1010DV33
Contents
Selection Guide ................................................................ 3 Ordering Information ...................................................... 11
Pin Configuration ............................................................. 3 Ordering Code Definitions ......................................... 11
Maximum Ratings ............................................................. 4 Package Diagrams .......................................................... 12
Operating Range ............................................................... 4 Acronyms ........................................................................ 14
a
Electrical Characteristics ................................................. 4 Document Conventions ................................................. 14
Capacitance ...................................................................... 5 Units of Measure ....................................................... 14
Thermal Resistance .......................................................... 5 Document History Page ................................................. 15
AC Test Loads and Waveforms ....................................... 5 Sales, Solutions, and Legal Information ...................... 16
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Data Retention Characteristics ....................................... 6 Worldwide Sales and Design Support ....................... 16
Data Retention Waveform ................................................ 6 Products .................................................................... 16
AC Switching Characteristics ......................................... 7 PSoC Solutions ...................................................... 16
Switching Waveforms ...................................................... 8 Cypress Developer Community ................................. 16
Truth Table ...................................................................... 10 Technical Support ..................................................... 16
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Document Number: 001-00062 Rev. *E Page 2 of 16

CY7C1010DV33
Selection Guide
Description -10 Unit
Maximum Access Time 10 ns
a
Maximum Operating Current 90 mA
Maximum CMOS Standby Current 10 mA
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Pin Configuration
Figure 1. 36-pin SOJ pinout [1] Figure 2. 44-pin TSOP II pinout [1]
Di n 1 44 NC
NC
NC 2 43 NC
A4 1 36 NC A4 3 NC
42
A3 2 35 A5 A3 4 A5
41
A2 3 34 A6 A2 5 A6
40
lic l A1
A0
4
5
33
32
A7
A8
A1 6 39 A7
a
A0 7 38 A8
a CE
IO0
IO1
6
7
8
31
30
29
OE
IO7
IO6
CE
IO0
IO1
8
9
10
37
36
35
OE
IO7
IO6
r
VCC 9 28 GND VCC VSS
11 34
ad GND
IO2
10
11
27
26
VCC
IO5
VSS
IO2
12 33 VCC
IO5
t
13 32
IO3 12 25 IO4 IO3 IO4
14 31
WE 13 24 A9 15 30 A9
WE
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A17 14 23 A10 A17 A10

16 29
A16 15 22 A11 A16 A11
17 28
A15 16 21 A12 A15 A12
18 27
A14 17 20 NC A14 NC
19 26
A13 18 19 NC A13 NC
20 25
NC 21 24 NC
NC 22 23 NC
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Note
1. NC pins are not connected on the die.

CY7C1010DV33
Maximum Ratings DC Input Voltage [2] ............................ 0.3 V to VCC + 0.3 V

Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested. Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage Temperature ............................... 65 qC to +150 qC
Latch Up Current ................................................... > 200 mA
a
Ambient Temperature with
Power Applied ......................................... 55 qC to +125 qC
Operating Range
Supply Voltage on
VCC Relative to GND [2] ...............................0.5 V to +4.6 V Range Ambient Temperature VCC
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DC Voltage Applied to Outputs Industrial 40qC to +85qC 3.3V r 0.3V
in High Z State [2] ................................ 0.3 V to VCC + 0.3 V
Electrical Characteristics
Di n
Over the Operating Range
-10
Parameter Description Test Conditions
lic l Min Max Unit
a
VOH
VOL
a Output HIGH Voltage
Output LOW Voltage
VCC = Min; IOH = 4.0 mA
VCC = Min; IOL = 8.0 mA
2.4

0.4
V
V
r
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL
ad Input LOW Voltage [2]
0.3 0.8 V
t
IIX Input Leakage Current GND < VI < VCC 1 +1 PA

IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled 1 +1
ec
PA
ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz 90 mA
83 MHz 80
66 MHz 70
40 MHz 60
ISB1 Automatic CE Power-down Max VCC, CE > VIH; VIN > VIH or 20 mA
Current TTL Inputs VIN < VIL, f = fMAX
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ISB2 Automatic CE Power-down Max VCC, CE > VCC 0.3 V, 10 mA

Current CMOS Inputs VIN > VCC 0.3 V, or VIN < 0.3 V, f = 0
Note
2. VIL (min.) = 2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns.

CY7C1010DV33
Capacitance
Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
CIN Input capacitance TA = 25 qC, f = 1 MHz, VCC = 3.3 V 8 8 pF
a
COUT I/O capacitance 8 8 pF
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Thermal Resistance
Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
4JA Thermal resistance Still air, soldered on a 3 4.5 inch, four 59.17 50.66 qC/W
(junction to ambient) layer printed circuit board
Di n
4JC Thermal resistance 32.63 17.77 qC/W
(junction to case)
lic l
AC Test Loads and Waveforms
a
a Z = 50 :
Figure 3. AC Test Loads and Waveforms [4]
r
ALL INPUT PULSES
OUTPUT 3.0 V
ad 50 : 30 pF* 10%
90% 90%
10%
t
* CAPACITIVE LOAD CONSISTS GND

OF ALL COMPONENTS OF THE 1.5 V
TEST ENVIRONMENT
ec
(a) Rise Time: 1 V/ns (b) Fall Time: 1 V/ns

High-Z characteristics: R 317:
3.3 V
OUTPUT
5 pF R2
351:
(c)
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Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown
in Figure 3 (c).

CY7C1010DV33
Data Retention Characteristics

Parameter [5] Description Conditions Min Max Unit
a
VDR VCC for Data Retention 2 V
ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC 0.3 V, 10 mA
VIN > VCC 0.3 V or VIN < 0.3 V
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tCDR [6] Chip Deselect to Data Retention Time 0 ns
[7]
tR Operation Recovery Time tRC ns
Di n
Data Retention Waveform
Figure 4. Data Retention Waveform
lic l
a
DATA RETENTION MODE
a VCC 3.0V
tCDR
VDR > 2V 3.0V
tR
r
CE
ad
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Notes
5. No inputs may exceed VCC + 0.3 V.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 Ps or stable at VCC(min.) > 50 Ps.

CY7C1010DV33
AC Switching Characteristics
-10
a
Parameter [8] Description
Min Max Unit
Read Cycle
tpower[9] VCC(typical) to the first access 100
Ap git ic
Ps
tRC Read Cycle Time 10 ns
tAA Address to Data Valid 10 ns
tOHA Data Hold from Address Change 3 ns
Di n
tACE CE LOW to Data Valid 10 ns
tDOE OE LOW to Data Valid 5 ns
tLZOE OE LOW to Low Z [10] 0 ns
lic l
tHZOE OE HIGH to High Z [10, 11]
5 ns
a
tLZCE a CE LOW to Low Z[10] 3 ns
tHZCE CE HIGH to High Z[10, 11] 5 ns
r
tPU CE LOW to Power-up 0 ns
tPD
ad CE HIGH to Power-down 10 ns
t
Write Cycle[12, 13]

tWC Write Cycle Time 10 ns
ec
tSCE CE LOW to Write End 7 ns

tAW Address Set-up to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-up to Write Start 0 ns
tPWE WE Pulse Width 7 ns
tSD Data Set-up to Write End 5 ns
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tHD Data Hold from Write End 0 ns

tLZWE WE HIGH to Low Z[10] 3 ns
tHZWE WE LOW to High Z[10, 11] 5 ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
9. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 5. Transition is measured when the outputs enter a high
impedance state.
12. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
13. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

CY7C1010DV33
Switching Waveforms
Figure 5. Read Cycle No. 1 [14, 15]
a
tRC
RC
ADDRESS
tAA
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tOHA
DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]

Di n
ADDRESS
lic l tRC
a
CE
a
r
tACE
ad OE
t
tHZOE
tDOE
ec
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
VCC tPU ICC
SUPPLY 50% 50%
CURRENT ISB
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Notes
14. The device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
16. Address valid before or similar to CE transition LOW.

CY7C1010DV33
Switching Waveforms (continued)

Figure 7. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [17, 18]
tWC
a
ADDRESS
tSCE
CE
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tAW tHA
tSA tPWE
WE
Di n
OE
tSD tHD
DATA I/O DATAIN VALID
lic l NOTE 19
a
a tHZOE
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18]

r
ad tWC
t
ADDRESS
ec
tSCE
CE
tAW tHA
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tSA tPWE
WE
tSD tHD
DATA I/O NOTE 19 DATA VALID
tHZWE tLZWE
Notes
17. Data IO is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.

CY7C1010DV33
Truth Table
CE OE WE I/O0I/O7 I/O8I/O15 Mode Power
H X X High Z High Z Power Down Standby (ISB)
a
L L H Data Out Data Out Read All Bits Active (ICC)
L X L Data In Data In Write All Bits Active (ICC)
L H H High Z High Z Selected, Outputs Disabled Active (ICC)
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Features
Read Access Time 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 256 Bytes
Internal Control Timer
Fast Write Cycle Time
Page Write Cycle Time 10 ms Maximum
a
1 to 256 Byte Page Write Operation
Low Power Dissipation
50 mA Active Current 4-Megabit
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Hardware and Software Data Protection
DATA Polling for End of Write Detection (512K x 8)
High Reliability CMOS Technology
Endurance: 10,000 Cycles
Paged Parallel
Data Retention: 10 Years
EEPROMs
Di n
Single 5V r 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
AT28C040
lic l
a
a
1. Description
The AT28C040 is a high-performance electrically erasable and programmable read-
r
only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by
ad
8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device
t
offers access times to 200 ns with power dissipation of just 440 mW.
ec
The AT28C040 is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 256-byte page register to allow
writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to
256 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a
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new access for a read or write can begin.

Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra 256
bytes of EEPROM for device identification or tracking.
0542FPEEPR2/09
2. Pin Configurations 2.2 32-lead Flatpack Top View
Pin Name Function

A18 1 32 VCC
A0 - A18 Addresses A16 2 31 WE
A15 3 30 A17
CE Chip Enable
A12 4 29 A14
OE Output Enable A7 5 28 A13
a
A6 6 27 A8
WE Write Enable
A5 7 26 A9
I/O0 - I/O7 Data Inputs/Outputs A4 8 25 A11
A3 9 24 OE
NC No Connect
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A2 10 23 A10
A1 11 22 CE
A0 12 21 I/O7
I/O0 13 20 I/O6
I/O1 14 19 I/O5
Di n I/O2 15 18 I/O4
GND 16 17 I/O3
lic l
a
2.1 a
44-lead LCC Top View
VCC
r
A15
A16
A18
A17
A14
WE
NC
NC
NC
NC
ad
6
5
4
3
2
1
44
43
42
41
t 40
A12 7 39 A13
A7 8 38 A8
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A6 9 37 A9
A5 10 36 A11
NC 11 35 NC
NC 12 34 NC
NC 13 33 NC
A4 14 32 NC
A3 15 31 OE
A2 16 30 A10
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A1 17 29 CE
18
19
20
21
22
23
24
25
26
27
28
A0
I/O0
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
2 AT28C040
0542FPEEPR2/09
AT28C040
3. Block Diagram
a
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Di n
4. Absolute Maximum Ratings*
lic l
Temperature Under Bias................................ -55qC to +125qC *NOTICE: Stresses beyond those listed under Absolute
a
a
Storage Temperature ..................................... -65qC to +150qC
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
r
All Input Voltages other conditions beyond those indicated in the
ad
(including NC pins) operational sections of this specification is not
t
with Respect to Ground ...................................-0.6V to +6.25V implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
ec
All Output Voltages reliability.

with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9

with Respect to Ground ...................................-0.6V to +13.5V
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3
0542FPEEPR2/09
5. Device Operation
5.1 Read
The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
a
5.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
Ap git ic
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
Di n
5.3 Page Write
The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 255 additional
lic l bytes. Each successive byte must be written within 150Ps (tBLC) of the previous byte. If the tBLC
a
a limit is exceeded, the AT28C040 will cease accepting data and commence the internal program-
ming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page
r
write operation, A8 - A18 must be the same.
ad The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be
t
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
ec
5.4 Data Polling

The AT28C040 features Data Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write
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cycle.
5.5 Toggle Bit

In addition to Data Polling, the AT28C040 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
5.6 Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4 AT28C040
0542FPEEPR2/09
AT28C040
5.6.1 Hardware Protection

Hardware features protect against inadvertent writes to the AT28C040 in the following ways:
(a) VCC sense if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before
allowing a write: (c) write inhibit holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
a
5.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28C040. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP
Ap git ic
disabled.
SDP is enabled when the host system issues a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be
Di n
protected against inadvertent write operations. It should be noted that once protected, the host
can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command
sequence used to enable SDP must precede the data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
lic l tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down
a
a conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device, and the
memory addresses used in the sequence may be written with data in either a byte or page write
r
operation.
ad After setting SDP, any attempt to write to the device without the 3-byte command sequence will
t
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
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5.7 Device Identification

An extra 256 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V r 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
El
5.8 Optional Chip Erase Mode

The entire device can be erased using a 6-byte software erase code. Please see Software Chip
Erase application note for details.
5
0542FPEEPR2/09
6. DC and AC Operating Range
AT28C040-20 Operation
Read Program
Industrial -40C - 85C -40C - 85C
Operating Temperature (Case)
Extended -55C - 125C -40C - 85C
a
VCC Power Supply 5Vr 10% 5Vr 10%
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7. Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
(2)
Write VIL VIH VIL DIN
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Write Inhibit X X VIH
Write Inhibit X VIL X
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Output Disable X VIH X High Z
a
Notes: a 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
r
ad
8. DC Characteristics
t
Symbol Parameter Condition Min Max Units

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ILI Input Load Current VIN = 0V to VCC + 1V 10 A

ILO Output Leakage Current VI/O = 0V to VCC 10 A
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
El
VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 A 2.4 V
VOH2 Output High Voltage CMOS IOH = -100A; VCC = 4.5V 4.2 V
6 AT28C040
0542FPEEPR2/09
AT28C040
9. AC Read Characteristics
AT28C040-20
Symbol Parameter Min Max Units
tACC Address to Output Delay 200 ns
tCE(1) CE to Output Delay 200 ns
tOE(2) OE to Output Delay 0 55 ns
a
tDF(3)(4) CE or OE to Output Float 0 55 ns
tOH Output Hold from OE, CE or Address, whichever occurred first 0 ns
10. AC Read Waveforms(1)(2)(3)(4)
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a
Notes:
a 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC.
r
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
ad without impact on tACC.

t
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.
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11. Input Test Waveforms and Measurement Level

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tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance

f = 1 MHz, T = 25C(1)
Symbol Typ Max Units Conditions
CIN 4 10 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.
7
0542FPEEPR2/09
14. AC Write Characteristics
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
a
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 100 ns
tDS Data Set-up Time 50 ns
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tDH, tOEH Data, OE Hold Time
15. AC Write Waveforms

0 ns
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15.1 WE Controlled
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15.2 CE Controlled
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8 AT28C040
0542FPEEPR2/09
AT28C040
16. Page Mode Characteristics

tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
a
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 100 ns
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tBLC
tWPH
Byte Load Cycle Time
Write Pulse Width High
17. Page Mode Write Waveforms(1)(2)

50
150 Ps
ns
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Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).
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2. OE must be high only when WE and CE are both low.
9
0542FPEEPR2/09
18. Software Data 19. Software Data
Protection Enable Algorithm(1) Protection Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555
LOAD DATA 55
a
LOAD DATA 55
TO TO
ADDRESS 2AAA ADDRESS 2AAA
LOAD DATA A0 LOAD DATA 80
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TO TO
ADDRESS 5555 ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX LOAD DATA AA

TO TO
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ANY ADDRESS(4) ADDRESS 5555
LOAD LAST BYTE LOAD DATA 55

TO TO
lic l LAST ADDRESS

ENTER DATA
ADDRESS 2AAA
a
Notes:
a PROTECT STATE
1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).
LOAD DATA 20
TO
r
ADDRESS 5555
EXIT DATA
ad 2. Write Protect state will be activated at end of write

even if no other data is loaded. LOAD DATA XX
PROTECT STATE(3)
t
TO
3. Write Protect state will be deactivated at end of write
ANY ADDRESS(4)
period even if no other data is loaded.
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4. 1 to 256 bytes of data are loaded.

LOAD LAST BYTE
TO
LAST ADDRESS
20. Software Protected Program Cycle Waveform(1)(2)(3)

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Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
10 AT28C040
0542FPEEPR2/09
AT28C040
21. Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
a
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
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22. Data Polling Waveforms
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23. Toggle Bit Characteristics(1)

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Symbol Parameter Min Typ Max Units

tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tOEHP OE High Pulse 150 ns
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tWR Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
24. Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0542FPEEPR2/09
7.- Dispositivos Perifricos
a
7.1.- Introduccin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2
7.2.- Clasificacin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3
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7.3.- Interfaz paralelo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3
7.4.- Interfaz serie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3
7.5.- Controlador de tiempo y frecuencia . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4
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7.6.- Controlador de interrupciones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4
7.7.- Controlador de ADM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5
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a
7.9.- Puerto analgico . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5
a
7.10.- Otros dispositivos perifricos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5
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7.11.- Referencias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7
ad
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V1.0 7.1
7.1.- Introduccin
Los dispositivos perifricos son elementos complejos programables
complementarios a una UCP. De una forma genrica podemos decir que todos los
elementos que no es UCP ni UCM es un dispositivo perifrico (a la UCP).
Los dispositivos perifricos sirven para realizar funciones por medio de circuitera
a
ms eficientemente que si se realizaran por medio de programacin de la UCP. Es
decir que los dispositivos perifricos permiten que la UCP se descargue de tareas
fcilmente realizable por estos dispositivos, as ella puede dedicarse a controlar todo
el sistema. Los dispositivos perifricos son trabajadores especializados en una
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determinada tarea. Son programables para establecerles el mtodo de trabajo dentro
de su especialidad y se comunican con la UCP por medio de los buses del sistema
(direcciones, datos y control).
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En todos los dispositivos perifricos podemos encontrar tres tipos de registros que
son los que utiliza el programador del sistema (a travs de la UCP) para manejar y
supervisar su funcionamiento. Lo mas frecuente es organizarlo en los tres tipos
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siguientes:
a
a1. Registros de programacin, que sirven para establecer la forma de
funcionamiento del dispositivo.
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ad 2. Registros de control, que sirven para obtener informacin del estado del
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dispositivo y lo que est haciendo, as como para enviarle rdenes para su

ejecucin.
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3. Registros de datos, por medio de los cuales el dispositivo transfiere

informacin a o desde la UCP.
Dependiendo del tipo de dispositivo perifrico, veremos que el nmero de

registros de cada tipo vara segn sea necesario.
El
Lo ms frecuente es que estos registros sean de 8 bits y en muchos casos los de

programacin y los de control se programan bit a bit. Esto significa que aunque un
registro dispone de 8 bits, cada uno de los bits sirve para activar o desactivar una
funcin dentro del dispositivo. Tambin nos encontraremos con grupos de 2 o mas bits
para seleccionar determinadas funciones. Todo esto nos lo dice el fabricante del
dispositivo en su manual.
La utilizacin de estos dispositivos se hace mayoritariamente por programacin
(en muy pocos casos pueden ser controlados manualmente). El programa que ejecuta
la UCP (y que es escrito por nosotros) va realizando operaciones de escritura y de
lectura para configurar y hacer funcionar los dispositivos como se desee dentro de las
posibilidades que tiene cada uno de ellos. Para lograr esto hay que conocer cmo
funciona cada dispositivo y cmo se ha de manejar.
V1.0 7.2
7.2.- Clasificacin
En el mercado nos encontramos con una enorme variedad de dispositivos
perifricos. Nosotros los vamos a clasificar en las cuatro siguientes categoras:
1. Interfaz paralelo. Es un clsico para poder gobernar dispositivos digitales
bit a bit o por byte. Tiene propiedades importantes como alta velocidad de
a
transferencia (B/s) pero tiene el inconveniente de su poco alcance (unos
metros en el mejor caso).
2. Interfaz serie. Su uso est muy extendido (USB, FireWire, CAN, I2C, ...) ya
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que simplifica enormemente el conexionado y, adems, tiene un gran
alcance.
3. Expansin de funciones. En esta categora nos encontramos con muchos
elementos de los que solo citaremos algunas: Controlador de tiempo y
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frecuencia, controlador de interrupciones y controlador de ADM (Acceso
Directo a Memoria)
lic l 4. Puerto analgico. Esta categora es extremadamente til cuando se trabaja
a
a con seales analgicas con tratamiento digital (Mixed signal) y suele estar
incorporada en la mayora de los microcontroladores actuales.
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7.3.- Interfaz paralelo

El interfaz paralelo o puerto paralelo, est descrito en detalle en el captulo 8 del
libro Sistemas Basados en Microprocesadores en los apartados 8.1 a 8.4 y 8.5. Por
eso, en este documento solamente hacemos la inclusin de la referencia tcnica del
fabricante en la referencia 8255, que tambin describe su funcionamiento.
El
Por otro lado, el :C MSP430 dispone de una interfaz paralelo ligeramente

diferente. Para ver este caso hay que consultar los documentos externos
MSP430G2553 Hojas de datos y MSP430x2xx Family Users Guide disponibles en
el Aula Virtual. En el primero encontramos las caractersticas elctricas y temporales
de funcionamiento mientras que en el segundo hay una descripcin muy completa de
esta interfaz que en este caso la denominan Digital I/O y es el captulo 8 de este
documento.
7.4.- Interfaz serie

De forma similar al caso anterior, el controlador de la interfaz serie o puerto serie,
se encuentra descrito detalladamente en el captulo 8 del libro Sistemas Basados en
Microprocesadores en los apartados 8.1 a 8.4 y 8.5. Por eso, en este documento
V1.0 7.3
solamente hacemos la inclusin de la referencia tcnica del fabricante en la referencia

82050, que tambin describe su funcionamiento.
En el caso del MSP430, el puerto serie se denomina USI (Universal Serial
Interface) y la tenemos en los documentos externos MSP430G2553 Hojas de datos
y MSP430x2xx Family Users Guide disponibles en el Aula Virtual. En el primero
encontramos las caractersticas elctricas y temporales de funcionamiento mientras
que en el segundo hay una descripcin muy completa de esta interfaz en los captulos
a
14 a 19 de este documento.
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7.5.- Controlador de tiempo y frecuencia
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De nuevo, como en el apartado anterior, el controlador de tiempo y frecuencia o
temporizador, se encuentra descrito detalladamente en el captulo 8 del libro Sistemas
Basados en Microprocesadores en los apartados 8.1 a 8.4 y 8.6. Por eso, en este
lic l
documento solamente hacemos la inclusin de la referencia tcnica del fabricante en
a
la referencia 8254, que tambin describe su funcionamiento.
a
En el caso del MSP430, el temporizador se denomina Timer y lo tenemos en los
r
documentos externos MSP430G2553 Hojas de datos y MSP430x2xx Family Users
ad
Guide disponibles en el Aula Virtual. En el primero encontramos las caractersticas
t
elctricas y temporales de funcionamiento mientras que en el segundo hay una

descripcin muy completa de esta interfaz en los captulos 12 y 13 de este documento.
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7.6.- Controlador de interrupciones

Como en los casos anteriores, el controlador de interrupciones se encuentra
descrito detalladamente en el captulo 7 del libro Sistemas Basados en
El
Microprocesadores en los apartados 7.1 y 7.2. Por eso, en este documento solamente
hacemos la inclusin de la referencia tcnica del fabricante en la referencia 8259, que
tambin describe su funcionamiento.
En el caso del MSP430, el funcionamiento del control de interrupciones lo
tenemos en los documentos externos MSP430G2553 Hojas de datos y MSP430x2xx
Family Users Guide disponibles en el Aula Virtual. En el primero encontramos las
caractersticas elctricas y temporales de funcionamiento mientras que en el segundo
hay una descripcin muy completa de este controlador en el captulo 2 de este
documento.
V1.0 7.4
7.7.- Controlador de ADM

Como en los casos anteriores, el controlador de ADM se encuentra descrito
detalladamente en el captulo 7 del libro Sistemas Basados en Microprocesadores en
los apartados 7.1 y 7.3. Por eso, en este documento solamente hacemos la inclusin
de la referencia tcnica del fabricante en la referencia 8237, que tambin describe su
funcionamiento.
a
En el caso del MSP430, algunos modelos incluyen un controlador de ADM que
lo podemos ver en el captulo 6 del documento externo MSP430x2xx Family Users
Guide disponible en el Aula Virtual.
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7.9.- Puerto analgico
En este caso nos encontramos con dos posibilidades, que el puerto analgico sea
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de entrada (datos hacia la UCP) o de salida.
a
a
Entrada analgica. Es el caso ms frecuente de encontrar en los
microcontroladores. En nuestro caso y dado que utilizamos el MSP4390 de
r
Texas Instruments, disponemos de una entrada analgica de 10 bits
ad compartida entre varios canales de entrada.

t
En el caso del MSP430, la entrada analgica se denomina ADC10 (10-bit

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Analog to Digital Converter) y la tenemos en los documentos externos

MSP430G2553 Hojas de datos y MSP430x2xx Family Users Guide
disponibles en el Aula Virtual. En el primero encontramos las caractersticas
elctricas y temporales de funcionamiento mientras que en el segundo hay una
descripcin muy completa de este puerto en el captulo 22 de este documento.
El
Salida analgica. Cada da es ms frecuente encontrar SBM con salida

analgica, sin embargo no es demasiado frecuente encontrar :C que la tenga.
En el caso del MSP430, hay modelos que disponen de ete puerto analgico
de salida y se denomina DCA12" y lo tenemos en el captulo 25 del
documento MSP430x2xx Family Users Guide disponibles en el Aula Virtual.
7.10.- Otros dispositivos perifricos

Los dispositivos perifricos o controladores citados en los apartados anteriores
son los que utilizamos en SED, pero como se dijo en el apartado 7.1 existen muchos
ms que son prcticamente imposible de describir. Se han elegido stos por ser los
mas simples de entender y se usan muy frecuentemente.
V1.0 7.5
En el caso de la familia de :C MSP430 tenemos los siguientes dispositivos

adems de los citados (solo a modo de cita):
Basic Clock Module+
Flash Memory Controller
Supply Voltage Supervisor (SVS)
a
Watchdog Timer+ (WDT+)
Hardware Multiplier
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Universal Serial Communication Interface, SPI
Universal Serial Communication Interface, I2C
TLV (Tag-Length-Value)
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SD16_A (16-bit sigma-delta analog-to-digital conversion module)
ADC12
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SD24_A (24-bit sigma-delta analog-to-digital converter)
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Embedded Emulation Module (EEM)
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V1.0 7.6
7.11.- Referencias
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V1.0 7.7
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8254
PROGRAMMABLE INTERVAL TIMER
Y Compatible with All Intel and Most Y Six Programmable Counter Modes
Other Microprocessors Y Three Independent 16-Bit Counters
Y Handles Inputs from DC to 10 MHz Y Binary or BCD Counting
8 MHz 8254
10 MHz 8254-2 Y Single a 5V Supply
a
Y Status Read-Back Command Y Available in EXPRESS
Standard Temperature Range
The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcom-
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puter system design. It provides three independent 16-bit counters, each capable of handling clock inputs up
to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.
The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.
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231164 2
Figure 2. Pin Configuration
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231164 1
Figure 1. 8254 Block Diagram
September 1993 Order Number: 231164-005

8254
Table 1. Pin Description

Pin
Symbol Type Name and Function
No.
D7 D0 18 I/O DATA: Bi-directional three state data bus lines, connected to system
data bus.
CLK 0 9 I CLOCK 0: Clock input of Counter 0.
OUT 0 10 O OUTPUT 0: Output of Counter 0.
a
GATE 0 11 I GATE 0: Gate input of Counter 0.
GND 12 GROUND: Power supply connection.
VCC 24 POWER: a 5V power supply connection.
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WR 23 I WRITE CONTROL: This input is low during CPU write operations.
RD 22 I READ CONTROL: This input is low during CPU read operations.
CS 21 I CHIP SELECT: A low on this input enables the 8254 to respond to
RD and WR signals. RD and WR are ignored otherwise.
A1, A0 2019 I ADDRESS: Used to select one of the three Counters or the Control
Word Register for read or write operations. Normally connected to
Di n the system address bus.
A1
0
A0
0 Counter 0
Selects
0 1 Counter 1
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1 0 Counter 2
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a
CLK 2
OUT 2
18
17 O
I
1 1 Control Word Register
CLOCK 2: Clock input of Counter 2.
OUT 2: Output of Counter 2.
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CLK 1 15 I CLOCK 1: Clock input of Counter 1.
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OUT 1 13 O OUT 1: Output of Counter 1.
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FUNCTIONAL DESCRIPTION Some of the other counter/timer functions common

to microcomputers which can be implemented with
the 8254 are:
General # Real time clock
The 8254 is a programmable interval timer/counter # Event-counter
designed for use with Intel microcomputer systems. # Digital one-shot
It is a general purpose, multi-timing element that can # Programmable rate generator
El
be treated as an array of I/O ports in the system

software. # Square wave generator
# Binary rate multiplier
The 8254 solves one of the most common problems # Complex waveform generator
in any microcomputer system, the generation of ac-
curate time delays under software control. Instead of # Complex motor controller
setting up timing loops in software, the programmer
configures the 8254 to match his requirements and
programs one of the counters for the desired delay. Block Diagram
After the desired delay, the 8254 will interrupt the
CPU. Software overhead is minimal and variable DATA BUS BUFFER
length delays can easily be accommodated.
This 3-state, bi-directional, 8-bit buffer is used to in-
terface the 8254 to the system bus (see Figure 3).
2
8254
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Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions
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READ/WRITE LOGIC COUNTER 0, COUNTER 1, COUNTER 2
The Read/Write Logic accepts inputs from the sys- These three functional blocks are identical in opera-
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tem bus and generates control signals for the other tion, so only a single Counter will be described. The
functional blocks of the 8254. A1 and A0 select one internal block diagram of a single counter is shown
of the three counters or the Control Word Register in Figure 5.
to be read from/written into. A low on the RD in-
put tells the 8254 that the CPU is reading one of the The Counters are fully independent. Each Counter
counters. A low on the WR input tells the 8254 may operate in a different Mode.
that the CPU is writing either a Control Word or an
initial count. Both RD and WR are qualified by CS; The Control Word Register is shown in the figure; it
RD and WR are ignored unless the 8254 has been is not part of the Counter itself, but its contents de-
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selected by holding CS low. termine how the Counter operates.
The status register, shown in Figure 5, when

CONTROL WORD REGISTER latched, contains the current contents of the Control
The Control Word Register (see Figure 4) is selected Word Register and status of the output and null
by the Read/Write Logic when A1,A0 e 11. If the count flag. (See detailed explanation of the Read-
Back command.)
CPU then does a write operation to the 8254, the
data is stored in the Control Word Register and is
The actual counter is labelled CE (for Counting Ele-
interpreted as a Control Word used to define the
operation of the Counters. ment). It is a 16-bit presettable synchronous down
counter.
The Control Word Register can only be written to;
OLM and OLL are two 8-bit latches. OL stands for
status information is available with the Read-Back
Command. Output Latch; the subscripts M and L stand for
Most significant byte and Least significant byte
3
8254
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Figure 4. Block Diagram Showing Control Word Register and Counter Functions
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231164 5
Figure 5. Internal Block Diagram of a Counter
4
8254
respectively. Both are normally referred to as one other peripherals of the family. It is treated by the
unit and called just OL. These latches normally fol- systems software as an array of peripheral I/O
low the CE, but if a suitable Counter Latch Com- ports; three are counters and the fourth is a control
mand is sent to the 8254, the latches latch the register for MODE programming.
present count until read by the CPU and then return
to following the CE. One latch at a time is enabled Basically, the select inputs A0,A1 connect to the A0,
by the counters Control Logic to drive the internal A1 address bus signals of the CPU. The CS can be
bus. This is how the 16-bit Counter communicates derived directly from the address bus using a linear
a
over the 8-bit internal bus. Note that the CE itself select method. Or it can be connected to the output
cannot be read; whenever you read the count, it is of a decoder, such as an Intel 8205 for larger sys-
the OL that is being read. tems.
Similarly, there are two 8-bit registers called CRM
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and CRL (for Count Register). Both are normally OPERATIONAL DESCRIPTION
referred to as one unit and called just CR. When a
new count is written to the Counter, the count is
stored in the CR and later transferred to the CE. The General
Control Logic allows one register at a time to be
loaded from the internal bus. Both bytes are trans- After power-up, the state of the 8254 is undefined.
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ferred to the CE simultaneously. CRM and CRL are
cleared when the Counter is programmed. In this
way, if the Counter has been programmed for one
byte counts (either most significant byte only or least
The Mode, count value, and output of all Counters
are undefined.
How each Counter operates is determined when it is

significant byte only) the other byte will be zero. programmed. Each Counter must be programmed
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Note that the CE cannot be written into; whenever a before it can be used. Unused counters need not be
programmed.
a
count is written, it is written into the CR.
a
The Control Logic is also shown in the diagram.
CLK n, GATE n, and OUT n are all connected to the Programming the 8254
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outside world through the Control Logic.
Counters are programmed by writing a Control Word
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and then an initial count.
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8254 SYSTEM INTERFACE The Control Words are written into the Control Word
Register, which is selected when A1,A0 e 11. The
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The 8254 is a component of the Intel Microcomputer

Systems and interfaces in the same manner as all Control Word itself specifies which Counter is being
programmed.
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231164 6
Figure 6. 8254 System Interface
5
8254
Control Word Format

A1,A0 e 11 CS e 0 RD e 1 WR e 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
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SCSelect Counter MMode
SC1 SC0 M2 M1 M0
0 0 Select Counter 0 0 0 0 Mode 0
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0 1 Select Counter 1 0 0 1 Mode 1
1 0 Select Counter 2 X 1 0 Mode 2
1 1 Read-Back Command X 1 1 Mode 3
(see Read Operations)
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1 0 1 Mode 5
RWRead/Write
RW1 RW0
BCD
0 0 Counter Latch Command (see Read
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Operations) 0 Binary Counter 16-bits
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0 1 Read/Write least significant byte only 1 Binary Coded Decimal (BCD) Counter
1
1
a 0
1
Read/Write most significant byte only
Read/Write least significant byte first,
(4 Decades)
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then most significant byte
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NOTE:
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Dont care bits (X) should be 0 to insure compatibility with future Intel products.
Figure 7. Control Word Format

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By contrast, initial counts are written into the Coun- Since the Control Word Register and the three
ters, not the Control Word Register. The A1,A0 in- Counters have separate addresses (selected by the
puts are used to select the Counter to be written A1,A0 inputs), and each Control Word specifies the
into. The format of the initial count is determined by Counter it applies to (SC0,SC1 bits), no special in-
the Control Word used. struction sequence is required. Any programming
sequence that follows the conventions in Figure 7 is
acceptable.
Write Operations
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A new initial count may be written to a Counter at

The programming procedure for the 8254 is very any time without affecting the Counters pro-
flexible. Only two conventions need to be remem- grammed Mode in any way. Counting will be affected
bered: as described in the Mode definitions. The new count
1) For each Counter, the Control Word must be writ- must follow the programmed count format.
ten before the initial count is written.
If a Counter is programmed to read/write two-byte
2) The initial count must follow the count format counts, the following precaution applies: A program
specified in the Control Word (least significant must not transfer control between writing the first
byte only, most significant byte only, or least sig- and second byte to another routine which also writes
nificant byte and then most significant byte). into that same Counter. Otherwise, the Counter will
be loaded with an incorrect count.
6
8254
A1 A0 A1 A0
Control WordCounter 0 1 1 Control WordCounter 2 1 1
LSB of countCounter 0 0 0 Control WordCounter 1 1 1
MSB of countCounter 0 0 0 Control WordCounter 0 1 1
Control WordCounter 1 1 1 LSB of countCounter 2 1 0
LSB of countCounter 1 0 1 MSB of countCounter 2 1 0
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MSB of countCounter 1 0 1 LSB of countCounter 1 0 1
Control WordCounter 2 1 1 MSB of countCounter 1 0 1
LSB of countCounter 2 1 0 LSB of countCounter 0 0 0
MSB of countCounter 2 1 0 MSB of countCounter 0 0 0
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A1 A0 A1 A0
Control WordCounter 2 1 1 LSB of countCounter 1 0 1
LSB of countCounter 2 1 0 Control WordCounter 2 1 1
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LSB of countCounter 1
MSB of countCounter 0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
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MSB of countCounter 2 1 0 MSB of countCounter 2 1 0
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NOTE:
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In all four examples, all Counters are programmed to read/write two-byte counts. These are only four of many possible
programming sequences.
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Figure 8. A Few Possible Programming Sequences
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Read Operations A1,A0 e 11; CS e 0; RD e 1; WR e 0
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It is often desirable to read the value of a Counter D7 D6 D5 D4 D3 D2 D1 D0
without disturbing the count in progress. This is easi-
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ly done in the 8254. SC1 SC0 0 0 X X X X
There are three possible methods for reading the

counters: a simple read operation, the Counter SC1,SC0specify counter to be latched
Latch Command, and the Read-Back Command. SC1 SC0 Counter
Each is explained below. The first method is to per-
form a simple read operation. To read the Counter, 0 0 0
which is selected with the A1, A0 inputs, the CLK 0 1 1
input of the selected Counter must be inhibited by 1 0 2
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using either the GATE input or external logic. Other- 1 1 Read-Back Command
wise, the count may be in the process of changing
when it is read, giving an undefined result.
D5,D400 designates Counter Latch Command
COUNTER LATCH COMMAND Xdont care

The second method uses the Counter Latch Com- NOTE:
mand. Like a Control Word, this command is written Dont care bits (X) should be 0 to insure compatibility
to the Control Word Register, which is selected with future Intel products.
when A1,A0 e 11. Also like a Control Word, the Figure 9. Counter Latching Command Format
SC0, SC1 bits select one of the three Counters, but
two other bits, D5 and D4, distinguish this command
from a Control Word.
7
8254
The selected Counters output latch (OL) latches the A0, A1 e 11 CS e 0 RD e 1 WR e 0

count at the time the Counter Latch Command is
received. This count is held in the latch until it is read D7 D6 D5 D4 D3 D2 D1 D0
by the CPU (or until the Counter is reprogrammed). 1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0
The count is then unlatched automatically and the
OL returns to following the counting element (CE). D5: 0 e Latch count of selected counter(s)
This allows reading the contents of the Counters D4: 0 e Latch status of selected counters(s)
on the fly without affecting counting in progress. D3: 1 e Select Counter 2
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Multiple Counter Latch Commands may be used to D2: 1 e Select Counter 1
latch more than one Counter. Each latched Coun- D1: 1 e Select Counter 0
ters OL holds its count until it is read. Counter Latch D0: Reserved for future expansion; Must be 0
Commands do not affect the programmed Mode of
Figure 10. Read-Back Command Format
the Counter in any way.
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The read-back command may be used to latch multi-
If a Counter is latched and then, some time later,
ple counter output latches (OL) by setting the
latched again before the count is read, the second
COUNT bit D5 e 0 and selecting the desired coun-
Counter Latch Command is ignored. The count read
ter(s). This single command is functionally equiva-
will be the count at the time the first Counter Latch
lent to several counter latch commands, one for
Command was issued.
each counter latched. Each counters latched count
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With either method, the count must be read accord-
ing to the programmed format; specifically, if the
Counter is programmed for two byte counts, two
is held until it is read (or the counter is repro-
grammed). The counter is automatically unlatched
when read, but other counters remain latched until
they are read. If multiple count read-back commands
bytes must be read. The two bytes do not have to be
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are issued to the same counter without reading the
read one right after the other; read or write or pro-
count, all but the first are ignored; i.e., the count
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gramming operations of other Counters may be in-
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serted between them.
Another feature of the 8254 is that reads and writes

which will be read is the count at the time the first
read-back command was issued.
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The read-back command may also be used to latch
of the same Counter may be interleaved; for exam-
status information of selected counter(s) by setting
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ple, if the Counter is programmed for two byte
STATUS bit D4 e 0. Status must be latched to be
counts, the following sequence is valid.
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read; status of a counter is accessed by a read from
1) Read least significant byte. that counter.
2) Write new least significant byte.
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The counter status format is shown in Figure 11. Bits

3) Read most significant byte.
D5 through D0 contain the counters programmed
4) Write new most significant byte. Mode exactly as written in the last Mode Control
Word. OUTPUT bit D7 contains the current state of
If a Counter is programmed to read/write two-byte the OUT pin. This allows the user to monitor the
counts, the following precaution applies: A program counters output via software, possibly eliminating
must not transfer control between reading the first some hardware from a system.
and second byte to another routine which also reads
from that same Counter. Otherwise, an incorrect
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count will be read. D7 D6 D5 D4 D3 D2 D1 D0

Null
Output RW1 RW0 M2 M1 M0 BCD
READ-BACK COMMAND Count
The third method uses the Read-Back Command. D7 1 e OUT Pin is 1
This command allows the user to check the count 0 e OUT Pin is 0
value, programmed Mode, and current states of the D6 1 e Null Count
OUT pin and Null Count flag of the selected coun- 0 e Count available for reading
ter(s).
D5 D0 Counter programmed mode (see Figure
The command is written into the Control Word Reg- 7)
ister and has the format shown in Figure 10. The
Figure 11. Status Byte
command applies to the counters selected by set-
ting their corresponding bits D3, D2, D1 e 1.
8
8254
NULL COUNT bit D6 indicates when the last count COUNT and STATUS bits D5,D4 e 0. This is func-
written to the counter register (CR) has been loaded tionally the same as issuing two separate read-back
into the counting element (CE). The exact time this commands at once, and the above discussions ap-
happens depends on the Mode of the counter and is ply here also. Specifically, if multiple count and/or
described in the Mode Definitions, but until the count status read-back commands are issued to the same
is loaded into the counting element (CE), it cant be counter(s) without any intervening reads, all but the
read from the counter. If the count is latched or read first are ignored. This is illustrated in Figure 13.
before this time, the count value will not reflect the
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new count just written. The operation of Null Count If both count and status of a counter are latched, the
is shown in Figure 12. first read operation of that counter will return latched
status, regardless of which was latched first. The
next one or two reads (depending on whether the
This Action Causes counter is programmed for one or two type counts)
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A. Write to the control word register;(1) Null Count e 1 return latched count. Subsequent reads return un-
B. Write to the count register (CR);(2) Null Count e 1 latched count.
C. New Count is loaded into Null Count e 0
CE (CR x CE);
CS RD WR A1 A0
NOTE:
1. Only the counter specified by the control word will 0 1 0 0 0 Write into Counter 0
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have its Null Count set to 1. Null count bits of other
counters are unaffected.
2. If the counter is programmed for two-byte counts
(least significant byte then most significant byte) Null
0
0
1
1
0
0
0
1
1
0
Write into Counter 1
Write into Counter 2
Count goes to 1 when the second byte is written. 0 1 0 1 1 Write Control Word
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Figure 12. Null Count Operation 0 0 1 0 0 Read from Counter 0
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If multiple status latch operations of the counter(s)
are performed without reading the status, all but the
first are ignored; i.e., the status that will be read is
0
0
0
0
1
1
0
1
1
0
Read from Counter 1
Read from Counter 2
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the status of the counter at the time the first status 0 0 1 1 1 No-Operation (3-State)
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read-back command was issued. 1 X X X X No-Operation (3-State)
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Both count and status of the selected counter(s) 0 1 1 X X No-Operation (3-State)
may be latched simultaneously by setting both Figure 14. Read/Write Operations Summary
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Command
Description Result
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 0 1 0 Read back count and status of Count and status latched
Counter 0 for Counter 0
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1 1 1 0 0 1 0 0 Read back status of Counter 1 Status latched for Counter 1

1 1 1 0 1 1 0 0 Read back status of Counters 2, 1 Status latched for Counter
2, but not Counter 1
1 1 0 1 1 0 0 0 Read back count of Counter 2 Count latched for Counter 2
1 1 0 0 0 1 0 0 Read back count and status of Count latched for Counter 1,
Counter 1 but not status
1 1 1 0 0 0 1 0 Read back status of Counter 1 Command ignored, status
already latched for Counter 1
Figure 13. Read-Back Command Example
9
8254
Mode Definitions OUT will then go high and remain high until the CLK
pulse after the next trigger.
The following are defined for use in describing the
operation of the 8254. After writing the Control Word and initial count, the
CLK Pulse: a rising edge, then a falling edge, in Counter is armed. A trigger results in loading the
that order, of a Counters CLK in- Counter and setting OUT low on the next CLK pulse,
put. thus starting the one-shot pulse. An initial count of N
will result in a one-shot pulse N CLK cycles in dura-
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Trigger: a rising edge of a Counters GATE tion. The one-shot is retriggerable, hence OUT will
input. remain low for N CLK pulses after any trigger. The
Counter loading: the transfer of a count from the CR one-shot pulse can be repeated without rewriting the
to the CE (refer to the Functional same count into the counter. GATE has no effect on
Description) OUT.
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If a new count is written to the Counter during a one-
MODE 0: INTERRUPT ON TERMINAL COUNT shot pulse, the current one-shot is not affected un-
less the counter is retriggered. In that case, the
Mode 0 is typically used for event counting. After the
Counter is loaded with the new count and the one-
Control Word is written, OUT is initially low, and will
shot pulse continues until the new count expires.
remain low until the Counter reaches zero. OUT then
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goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Coun-
ter.
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is
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GATE e 1 enables counting; GATE e 0 disables typically used to generate a Real Time Clock inter-
counting. GATE has no effect on OUT. rupt. OUT will initially be high. When the initial count
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After the Control Word and initial count are written to
a Counter, the initial count will be loaded on the next
has decremented to 1, OUT goes low for one CLK
pulse. OUT then goes high again, the Counter re-
loads the initial count and the process is repeated.
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CLK pulse. This CLK pulse does not decrement the Mode 2 is periodic; the same sequence is repeated
count, so for an initial count of N, OUT does not go indefinitely. For an initial count of N, the sequence
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high until N a 1 CLK pulses after the initial count is repeats every N CLK cycles.
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written.
GATE e 1 enables counting; GATE e 0 disables
If a new count is written to the Counter, it will be counting. If GATE goes low during an output pulse,
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loaded on the next CLK pulse and counting will con- OUT is set high immediately. A trigger reloads the
tinue from the new count. If a two-byte count is writ- Counter with the initial count on the next CLK pulse;
ten, the following happens: OUT goes low N CLK pulses after the trigger. Thus
the GATE input can be used to synchronize the
1) Writing the first byte disables counting. OUT is set
Counter.
low immediately (no clock pulse required)
2) Writing the second byte allows the new count to After writing a Control Word and initial count, the
be loaded on the next CLK pulse. Counter will be loaded on the next CLK pulse. OUT
goes low N CLK Pulses after the initial count is writ-
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This allows the counting sequence to be synchroniz- ten. This allows the Counter to be synchronized by
ed by software. Again, OUT does not go high until software also.
N a 1 CLK pulses after the new count of N is written.
Writing a new count while counting does not affect
If an initial count is written while GATE e 0, it will the current counting sequence. If a trigger is re-
still be loaded on the next CLK pulse. When GATE ceived after writing a new count but before the end
goes high, OUT will go high N CLK pulses later; no of the current period, the Counter will be loaded with
CLK pulse is needed to load the Counter as this has the new count on the next CLK pulse and counting
already been done. will continue from the new count. Otherwise, the
new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
MODE 1: HARDWARE RETRIGGERABLE
ONE-SHOT
MODE 3: SQUARE WAVE MODE
OUT will be initially high. OUT will go low on the CLK
pulse following a trigger to begin the one-shot pulse, Mode 3 is typically used for Baud rate generation.
and will remain low until the Counter reaches zero. Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the
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8254
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231164 7
NOTE:
The following conventions apply to all mode timing diagrams:
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1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for Control Word; CW e 10 means a control word of 10 HEX is written to the counter.
4. LSB stands for Least Significant Byte of count.
5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the
most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read.
N stands for an undefined count.
Vertical lines show transitions between count values.
Figure 15. Mode 0
11
8254
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231164 8
Figure 16. Mode 1
initial count has expired, OUT goes low for the re- After writing a Control Word and initial count, the
mainder of the count. Mode 3 is periodic; the se- Counter will be loaded on the next CLK pulse. This
quence above is repeated indefinitely. An initial allows the Counter to be synchronized by software
count of N results in a square wave with a period of also.
N CLK cycles.
Writing a new count while counting does not affect
GATE e 1 enables counting; GATE e 0 disables the current counting sequence. If a trigger is re-
counting. If GATE goes low while OUT is low, OUT is ceived after writing a new count but before the end
set high immediately; no CLK pulse is required. A of the current half-cycle of the square wave, the
trigger reloads the Counter with the initial count on Counter will be loaded with the new count on the
the next CLK pulse. Thus the GATE input can be next CLK pulse and counting will continue from the
used to synchronize the Counter.
12
8254
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231164 9
NOTE:
A GATE transition should not occur one clock prior to terminal count.
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Figure 17. Mode 2
new count. Otherwise, the new count will be loaded Odd counts: OUT is initially high. The initial count
at the end of the current half-cycle. minus one (an even number) is loaded on one CLK
pulse and then is decremented by two on succeed-
Mode 3 is implemented as follows: ing CLK pulses. One CLK pulse after the count ex-
pires, OUT goes low and the Counter is reloaded
Even counts: OUT is initially high. The initial count is with the initial count minus one. Succeeding CLK
loaded on one CLK pulse and then is decremented pulses decrement the count by two. When the count
by two on succeeding CLK pulses. When the count expires, OUT goes high again and the Counter is
expires OUT changes value and the Counter is re- reloaded with the initial count minus one. The above
loaded with the initial count. The above process is process is repeated indefinitely. So for odd counts,
repeated indefinitely. OUT will be high for (N a 1)/2 counts and low for
(N b 1)/2 counts.
13
8254
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231164 10
NOTE:
A GATE transition should not occur one clock prior to terminal count.
Figure 18. Mode 3

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14
8254
MODE 4: SOFTWARE TRIGGERED STROBE initial count of N, OUT does not strobe low until N a
1 CLK pulses after the initial count is written.
OUT will be initially high. When the initial count ex-
pires, OUT will go low for one CLK pulse and then If a new count is written during counting, it will be
go high again. The counting sequence is triggered loaded on the next CLK pulse and counting will con-
by writing the initial count. tinue from the new count. If a two-byte count is writ-
ten, the following happens:
GATE e 1 enables counting; GATE e 0 disables 1) Writing the first byte has no effect on counting.
a
counting. GATE has no effect on OUT.
2) Writing the second byte allows the new count to
After writing a Control Word and initial count, the be loaded on the next CLK pulse.
Counter will be loaded on the next CLK pulse. This
CLK pulse does not decrement the count, so for an This allows the sequence to be retriggered by
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software. OUT strobes low N a 1 CLK pulses after
the new count of N is written.
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231164 11
Figure 19. Mode 4
15
8254
MODE 5: HARDWARE TRIGGERED STROBE A trigger results in the Counter being loaded with the
(RETRIGGERABLE) initial count on the next CLK pulse. The counting
sequence is retriggerable. OUT will not strobe low
OUT will initially be high. Counting is triggered by a for N a 1 CLK pulses after any trigger. GATE has
rising edge of GATE. When the initial count has ex- no effect on OUT.
pired, OUT will go low for one CLK pulse and then
go high again. If a new count is written during counting, the current
counting sequence will not be affected. If a trigger
a
After writing the Control Word and initial count, the occurs after the new count is written but before the
counter will not be loaded until the CLK pulse after a current count expires, the Counter will be loaded
trigger. This CLK pulse does not decrement the with the new count on the next CLK pulse and
count, so for an initial count of N, OUT does not counting will continue from there.
strobe low until N a 1 CLK pulses after a trigger.
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231164 12
Figure 20. Mode 5
16
8254
Signal Low Operation Common to All Modes

Status Or Going Rising High
Modes Low
PROGRAMMING
0 Disables Enables
Counting Counting When a Control Word is written to a Counter, all
Control Logic is immediately reset and OUT goes to
1 1) Initiates
a known initial state; no CLK pulses are required for
Counting
a
this.
2) Resets Output
after Next
Clock GATE
2 1) Disables
The GATE input is always sampled on the rising
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Counting Initiates Enables
2) Sets Output Counting Counting edge of CLK. In Modes 0, 2, 3, and 4 the GATE input
Immediately is level sensitive, and the logic level is sampled on
High the rising edge of CLK. In Modes 1, 2, 3, and 5 the
GATE input is rising-edge sensitive. In these Modes,
3 1) Disables a rising edge of GATE (trigger) sets an edge-sensi-
Counting Initiates Enables tive flip-flop in the Counter. This flip-flop is then sam-
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4
2) Sets Output
Immediately
High
Disables
Counting

Counting
Enables
pled on the next rising edge of CLK; the flip-flop is
reset immediately after it is sampled. In this way, a
trigger will be detected no matter when it occursa
high logic level does not have to be maintained until
Counting Counting the next rising edge of CLK. Note that in Modes 2
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5 Initiates and 3, the GATE input is both edge- and level-sensi-
a
tive. In Modes 2 and 3, if a CLK source other than
a Counting
Figure 21. Gate Pin Operations Summary
the system clock is used, GATE should be pulsed
immediately following WR of a new count value.
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COUNTER
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Min Max
Mode
Count Count
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New counts are loaded and Counters are decre-
0 1 0 mented on the falling edge of CLK.
1 1 0
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2 2 0 The largest possible initial count is 0; this is equiva-

lent to 216 for binary counting and 104 for BCD
3 2 0
counting.
4 1 0
5 1 0 The Counter does not stop when it reaches zero. In
Modes 0, 1, 4, and 5 the Counter wraps around to
NOTE: the highest count, either FFFF hex for binary count-
0 is equivalent to 216 for binary counting and 104 for ing or 9999 for BCD counting, and continues count-
BCD counting.
ing. Modes 2 and 3 are periodic; the Counter reloads
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Figure 22. Minimum and Maximum Initial Counts itself with the initial count and continues counting
from there.
17
8254
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias 0 C to 70 C
*WARNING: Stressing the device beyond the Absolute
Storage Temperature b 65 C to a 150 C Maximum Ratings may cause permanent damage.
Voltage on Any Pin with These are stress ratings only. Operation beyond the
Respect to Ground b 0.5V to a 7V Operating Conditions is not recommended and ex-
tended exposure beyond the Operating Conditions
Power Dissipation 1W may affect device reliability.
a
D.C. CHARACTERISTICS TA e 0 C to 70 C, VCC e 5V g 10%
Symbol Parameter Min Max Units Test Conditions
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VIL Input Low Voltage b 0.5 0.8 V
VIH Input High Voltage 2.0 VCC a 0.5V V
VOL Output Low Voltage 0.45 V IOL e 2.0 mA
VOH Output High Voltage 2.4 V IOH e b 400 mA
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IIL
IOFL
Input Load Current
Output Float Leakage
g 10
g 10
mA
mA
VIN e VCC to 0V
VOUT e VCC to 0.45V
ICC VCC Supply Current 170 mA
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CIN Input Capacitance 10 pF fc e 1 MHz
a
a
CI/0 I/O Capacitance 20 pF Unmeasured pins
returned to VSS(4)
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A.C. CHARACTERISTICS TA e 0 C to 70 C, VCC e 5V g 10%, GND e 0V
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Bus Parameters(1)
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READ CYCLE
8254 8254-2
Symbol Parameter Unit
Min Max Min Max
tAR Address Stable Before RD v 45 30 ns
tSR CS Stable Before RD v 0 0 ns
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tRA Address Hold Time After RD u 0 0 ns

tRR RD Pulse Width 150 95 ns
tRD Data Delay from RD v 120 85 ns
tAD Data Delay from Address 220 185 ns
tDF RD u to Data Floating 5 90 5 65 ns
tRV Command Recovery Time 200 165 ns
NOTE:
1. AC timings measured at VOH e 2.0V, VOL e 0.8V.
18
8254
A.C. CHARACTERISTICS TA e 0 C to 70 C, VCC e 5V g 10%, GND e 0V (Continued)
WRITE CYCLE
8254 8254-2
Min Max Min Max
tAW Address Stable Before WR v 0 0 ns
a
tSW CS Stable Before WR v 0 0 ns
tWA Address Hold Time After WR v 0 0 ns
tWW WR Pulse Width 150 95 ns
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tDW Data Setup Time Before WR u 120 95 ns
tWD Data Hold Time After WR u 0 0 ns
tRV
Di n Command Recovery Time 200 165 ns
CLOCK AND GATE

8254 8254-2
Min Max Min Max
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tCLK Clock Period 125 DC 100 DC ns
a
tPWH
tPWL
a High Pulse Width
Low Pulse Width
60(3)
60(3)
30(3)
50(3)
ns
ns
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tR Clock Rise Time 25 25 ns
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tF Clock Fall Time 25 25 ns
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tGW Gate Width High 50 50 ns
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tGL Gate Width Low 50 50 ns

tGS Gate Setup Time to CLK u 50 40 ns
tGH Gate Setup Time After CLK u 50(2) 50(2) ns
tOD Output Delay from CLK v 150 100 ns
tODG Output Delay from Gatev 120 100 ns
tWC CLK Delay for Loading v 0 55 0 55 ns
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tWG Gate Delay for Sampling b5 50 b5 40 ns

tWO OUT Delay from Mode Write 260 240 ns
tCL CLK Set Up for Count Latch b 40 45 b 40 40 ns
NOTES:
2. In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 8254-2) of
the rising clock edge may not be detected.
3. Low-going glitches that violate tPWH, tPWL may cause errors requiring counter reprogramming.
4. Sampled, not 100% tested. TA e 25 C.
5. If CLK present at TWC min then Count equals N a 2 CLK pulses, TWC max equals Count N a 1 CLK pulse. TWC min to
TWC max, count will be either N a 1 or N a 2 CLK pulses.
6. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWG
max Counter will be triggered.
7. If CLK present when writing a Counter Latch or ReadBack Command, at TCL min CLK will be reflected in count value
latched, at TCL max CLK will not be reflected in the count value latched.
19
8254
WAVEFORMS
WRITE
a
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a 231164 13
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READ
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231164 14
20
8254
WAVEFORMS (Continued)
RECOVERY
a
231164 15
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CLOCK AND GATE
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231164 16
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*Last byte of count being written.
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A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
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231164 17
A.C. Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V
for a Logic 0. Timing measurements are made at 2.0V for a
Logic 1 and 0.8V for a Logic 0. 231164 18
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CL e 150 pF
CL Includes Jig Capacitance
REVISION SUMMARY
The following list represents the key differences be-
tween Rev. 004 and Rev. 005 of the 8254 Data
Sheet.
1. References to and specifications for the 5 MHz
8254-5 are removed. Only the 8 MHz 8254 and
the 10 MHz 8254-2 remain in production.
21
8259A
PROGRAMMABLE INTERRUPT CONTROLLER
(8259A/8259A-2)
Y 8086, 8088 Compatible Y Single a 5V Supply (No Clocks)
Y MCS-80, MCS-85 Compatible Y Available in 28-Pin DIP and 28-Lead
Y Eight-Level Priority Controller PLCC Package
a
(See Packaging Spec., Order 231369)
Y Expandable to 64 Levels Y Available in EXPRESS
Y Programmable Interrupt Modes Standard Temperature Range
Extended Temperature Range
Y Individual Request Mask Capability
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The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU.
It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin
DIP, uses NMOS technology and requires a single a 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter-
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rupts. It has several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate
the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
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DIP
a
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231468 2
PLCC
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231468 31
Figure 2. Pin
231468 1
Figure 1. Block Diagram Configurations
December 1988 Order Number: 231468-003

8259A

Symbol Pin No. Type Name and Function
VCC 28 I SUPPLY: a 5V Supply.
GND 14 I GROUND
CS 1 I CHIP SELECT: A low on this pin enables RD and WR communication
between the CPU and the 8259A. INTA functions are independent of
a
CS.
WR 2 I WRITE: A low on this pin when CS is low enables the 8259A to accept
command words from the CPU.
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RD 3 I READ: A low on this pin when CS is low enables the 8259A to release
status onto the data bus for the CPU.
D7 D0 411 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector
information is transferred via this bus.
CAS0 CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control
a multiple 8259A structure. These pins are outputs for a master 8259A
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SP/EN 16 I/O
and inputs for a slave 8259A.
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.
When in the Buffered Mode it can be used as an output to control
buffer transceivers (EN). When not in the buffered mode it is used as
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an input to designate a master (SP e 1) or slave (SP e 0).
a
INT
a 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is

asserted. It is used to interrupt the CPU, thus it is connected to the
CPUs interrupt pin.
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IR0 IR7 1825 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request
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is executed by raising an IR input (low to high), and holding it high until
it is acknowledged (Edge Triggered Mode), or just by a high level on an
t
IR input (Level Triggered Mode).
INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A
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interrupt-vector data onto the data bus by a sequence of interrupt

acknowledge pulses issued by the CPU.
A0 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, and
RD pins. It is used by the 8259A to decipher various Command Words
the CPU writes and status the CPU wishes to read. It is typically
connected to the CPU A0 address line (A1 for 8086, 8088).
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2
8259A
FUNCTIONAL DESCRIPTION
Interrupts in Microcomputer Systems

Microcomputer system design requires that I.O de-
vices such as keyboards, displays, sensors and oth-
er components receive servicing in a an efficient
a
manner so that large amounts of the total system
tasks can be assumed by the microcomputer with
little or no effect on throughput.
The most common method of servicing such devic-
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es is the Polled approach. This is where the proces-
sor must test each device in sequence and in effect
ask each one if it needs servicing. It is easy to see
that a large portion of the main program is looping
through this continuous polling cycle and that such a
method would have a serious detrimental effect on
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system throughput, thus limiting the tasks that could
be assumed by the microcomputer and reducing the
cost effectiveness of using such devices. 231468 3
A more desirable method would be one that would Figure 3a. Polled Method
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allow the microprocessor to be executing its main
a
program and only stop to service peripheral devices
a
when it is told to do so by the device itself. In effect,
the method would provide an external asynchronous
input that would inform the processor that it should
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complete whatever instruction that is currently being
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executed and fetch a new routine that will service
the requesting device. Once this servicing is com-
t
plete, however, the processor would resume exactly
where it left off.
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This method is called Interrupt . It is easy to see that

system throughput would drastically increase, and
thus more tasks could be assumed by the micro-
computer to further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) func-

tions as an overall manager in an Interrupt-Driven
system environment. It accepts requests from the
peripheral equipment, determines which of the in-
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coming requests is of the highest importance (priori-

ty), ascertains whether the incoming request has a
higher priority value than the level currently being
serviced, and issues an interrupt to the CPU based
on this determination.
Each peripheral device or structure usually has a

special program or routine that is associated with
its specific functional or operational requirements;
this is referred to as a service routine. The PIC, 231468 4
after issuing an Interrupt to the CPU, must somehow
input information into the CPU that can point the Figure 3b. Interrupt Method
Program Counter to the service routine associated
with the requesting device. This pointer is an ad-
dress in a vectoring table and will often be referred
to, in this document, as vectoring data.
3
8259A
The 8259A is a device specifically designed for use INTA (INTERRUPT ACKNOWLEDGE)
in real time, interrupt driven microcomputer systems.
It manages eight levels or requests and has built-in INTA pulses will cause the 8259A to release vector-
features for expandability to other 8259As (up to 64 ing information onto the data bus. The format of this
levels). It is programmed by the systems software data depends on the system mode (mPM) of the
as an I/O peripheral. A selection of priority modes is 8259A.
available to the programmer so that the manner in
which the requests are processed by the 8259A can
a
be configured to match his system requirements. DATA BUS BUFFER
The priority modes can be changed or reconfigured
This 3-state, bidirectional 8-bit buffer is used to inter-
dynamically at any time during the main program.
face the 8259A to the system Data Bus. Control
This means that the complete interrupt structure can
words and status information are transferred
be defined as required, based on the total system
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through the Data Bus Buffer.
environment.
READ/WRITE CONTROL LOGIC

INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR) The function of this block is to accept OUTput com-
mands from the CPU. It contains the Initialization
The interrupts at the IR input lines are handled by
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two registers in cascade, the Interrupt Request Reg-
ister (IRR) and the In-Service (ISR). The IRR is used
to store all the interrupt levels which are requesting
service; and the ISR is used to store all the interrupt
Command Word (ICW) registers and Operation
Command Word (OCW) registers which store the
various control formats for device operation. This
function block also allows the status of the 8259A to
be transferred onto the Data Bus.
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levels which are being serviced.
a
a
PRIORITY RESOLVER
This logic block determines the priorites of the bits

CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading

or writing of the chip will occur unless the device is
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set in the IRR. The highest priority is selected and
selected.
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strobed into the corresponding bit of the ISR during
INTA pulse.
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WR (WRITE)
INTERRUPT MASK REGISTER (IMR) A LOW on this input enables the CPU to write con-
ec
trol words (ICWs and OCWs) to the 8259A.

The IMR stores the bits which mask the interrupt
lines to be masked. The IMR operates on the IRR.
Masking of a higher priority input will not affect the RD (READ)
interrupt request lines of lower quality.
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In
INT (INTERRUPT) Service Register (ISR), the Interrupt Mask Register
(IMR), or the Interrupt level onto the Data Bus.
This output goes directly to the CPU interrupt input.
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The VOH level on this line is designed to be fully

compatible with the 8080A, 8085A and 8086 input A0
levels.
This input signal is used in conjunction with WR and
RD signals to write commands into the various com-
mand registers, as well as reading the various status
registers of the chip. This line can be tied directly to
one of the address lines.
4
8259A
a
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231468 5
Figure 4a. 8259A Block Diagram

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5
8259A
a
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231468 6
Figure 4b. 8259A Block Diagram

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6
8259A
THE CASCADE BUFFER/COMPARATOR leased at the first INTA pulse and the higher 8-bit
address is released at the second INTA pulse.
This function block stores and compares the IDs of 7. This completes the 3-byte CALL instruction re-
all 8259As used in the system. The associated leased by the 8259A. In the AEOI mode the ISR
three I/O pins (CAS0-2) are outputs when the 8259A bit is reset at the end of the third INTA pulse.
is used as a master and are inputs when the 8259A Otherwise, the ISR bit remains set until an appro-
is used as a slave. As a master, the 8259A sends priate EOI command is issued at the end of the
the ID of the interrupting slave device onto the interrupt sequence.
a
CAS02 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data The events occuring in an 8086 system are the
Bus during the next one or two consecutive INTA same until step 4.
pulses. (See section Cascading the 8259A.)
4. Upon receiving an INTA from the CPU group, the
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highest priority ISR bit is set and the correspond-
INTERRUPT SEQUENCE ing IRR bit is reset. The 8259A does not drive the
Data Bus during this cycle.
The powerful features of the 8259A in a microcom-
puter system are its programmability and the inter- 5. The 8086 will initiate a second INTA pulse. Dur-
rupt routine addressing capability. The latter allows ing this pulse, the 8259A releases an 8-bit pointer
direct or indirect jumping to the specific interrupt rou- onto the Data Bus where it is read by the CPU.
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tine requested without any polling of the interrupting
devices. The normal sequence of events during an
interrupt depends on the type of CPU being used.
6. This completes the interrupt cycle. In the AEOI
mode the ISR bit is reset at the end of the sec-
ond INTA pulse. Otherwise, the ISR bit remains
set until an appropriate EOI command is issued
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The events occur as follows in an MCS-80/85 sys- at the end of the interrupt subroutine.
tem:
a
a
1. One or more of the INTERRUPT REQUEST lines
(IR70) are raised high, setting the correspond-
ing IRR bit(s).
If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration)
the 8259A will issue an interrupt level 7. Both the
vectoring bytes and the CAS lines will look like an
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2. The 8259A evaluates these requests, and sends interrupt level 7 was requested.
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an INT to the CPU, if appropriate.
When the 8259A PIC receives an interrupt, INT be-
t
3. The CPU acknowledges the INT and responds
with an INTA pulse. comes active and an interrupt acknowledge cycle is
started. If a higher priority interrupt occurs between
4. Upon receiving an INTA from the CPU group, the
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the two INTA pulses, the INT line goes inactive im-
highest priority ISR bit is set, and the correspond-
mediately after the second INTA pulse. After an un-
ing IRR bit is reset. The 8259A will also release a
specified amount of time the INT line is activated
CALL instruction code (11001101) onto the 8-bit
again to signify the higher priority interrupt waiting
Data Bus through its D70 pins.
for service. This inactive time is not specified and
5. This CALL instruction will initiate two more INTA can vary between parts. The designer should be
pulses to be sent to the 8259A from the CPU aware of this consideration when designing a sys-
group. tem which uses the 8259A. It is recommended that
6. These two INTA pulses allow the 8259A to re- proper asynchronous design techniques be fol-
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lease its preprogrammed subroutine address lowed.

onto the Data Bus. The lower 8-bit address is re-
7
8259A
a
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231468 7
Figure 4c. 8259A Block Diagram
INTERRUPT SEQUENCE OUTPUTS
MCS-80, MCS-85
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This sequence is timed by three INTA pulses. During

the first INTA pulse the CALL opcode is enabled
onto the data bus.
Content of First Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 D0
CALL CODE 1 1 0 0 1 1 0 1
During the second INTA pulse the lower address of

the appropriate service routine is enabled onto the
data bus. When Interval e 4 bits A5 A7 are pro-
grammed, while A0 A4 are automatically inserted by
the 8259A. When Interval e 8 only A6 and A7 are
231468 8 programmed, while A0 A5 are automatically insert-
ed.
Figure 5. 8259A Interface to
Standard System Bus
8
8259A
Content of Second Interrupt Vector Byte composed as follows (note the state of the ADI
mode control is ignored and A5 A11 are unused in
IR Interval e 4 8086 mode):
D7 D6 D5 D4 D3 D2 D1 D0 Content of Interrupt Vector Byte
for 8086 System Mode
7 A7 A6 A5 1 1 1 0 0
D7 D6 D5 D4 D3 D2 D1 D0
6 A7 A6 A5 1 1 0 0 0
IR7 T7 T6 T5 T4 T3 1 1 1
a
5 A7 A6 A5 1 0 1 0 0
IR6 T7 T6 T5 T4 T3 1 1 0
4 A7 A6 A5 1 0 0 0 0
IR5 T7 T6 T5 T4 T3 1 0 1
3 A7 A6 A5 0 1 1 0 0
IR4 T7 T6 T5 T4 T3 1 0 0
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2 A7 A6 A5 0 1 0 0 0
IR3 T7 T6 T5 T4 T3 0 1 1
1 A7 A6 A5 0 0 1 0 0
IR2 T7 T6 T5 T4 T3 0 1 0
0 A7 A6 A5 0 0 0 0 0
IR1 T7 T6 T5 T4 T3 0 0 1
IR Interval e 8 IR0 T7 T6 T5 T4 T3 0 0 0
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7
D7
A7
D6
A6
D5
1
D4
1
D3
1
D2
0
D1
0
D0
0
PROGRAMMING THE 8259A
6 A7 A6 1 1 0 0 0 0
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The 8259A accepts two types of command words
5 A7 A6 1 0 1 0 0 0 generated by the CPU:
a
4
3
aA7
A7
A6
A6
1
0
0
1
0
1
0
0
0
0
0
0
1. Initialization Command Words (ICWs): Before
normal operation can begin, each 8259A in the
system must be brought to a starting pointby a
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2 A7 A6 0 1 0 0 0 0 sequence of 2 to 4 bytes timed by WR pulses.
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1 A7 A6 0 0 1 0 0 0 2. Operation Command Words (OCWs): These are
the command words which command the 8259A
t
0 A7 A6 0 0 0 0 0 0 to operate in various interrupt modes. These
modes are:
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During the third INTA pulse the higher address of the a. Fully nested mode
appropriate service routine, which was programmed b. Rotating priority mode
as byte 2 of the initialization sequence (A8 A15), is
enabled onto the bus. c. Special mask mode
Content of Third Interrupt Vector Byte d. Polled mode
D7 D6 D5 D4 D3 D2 D1 D0
The OCWs can be written into the 8259A anytime
A15 A14 A13 A12 A11 A10 A9 A8 after initialization.
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8086, 8088 INITIALIZATION COMMAND WORDS

(ICWS)
8086 mode is similar to MCS-80 mode except that
only two Interrupt Acknowledge cycles are issued by
the processor and no CALL opcode is sent to the General
processor. The first interrupt acknowledge cycle is
similar to that of MCS-80, 85 systems in that the Whenever a command is issued with A0 e 0 and D4
e 1, this is interpreted as Initialization Command
8259A uses it to internally freeze the state of the
interrupts for priority resolution and as a master it Word 1 (ICW1). ICW1 starts the intiitalization se-
issues the interrupt code on the cascade lines at the quence during which the following automatically oc-
end of the INTA pulse. On this first cycle it does not cur.
issue any data to the processor and leaves its data a. The edge sense circuit is reset, which means that
bus buffers disabled. On the second interrupt ac- following initialization, an interrupt request (IR) in-
knowledge cycle in 8086 mode the master (or slave put must make a low-to-high transistion to gener-
if so programmed) will send a byte of data to the ate an interrupt.
processor with the acknowledged interrupt code
9
8259A
b. The Interrupt Mask Register is cleared. case SNGL e 0. It will load the 8-bit slave register.
c. IR7 input is assigned priority 7. The functions of this register are:
d. The slave mode address is set to 7. a. In the master mode (either when SP e 1, or in
buffered mode when M/S e 1 in ICW4) a 1 is
e. Special Mask Mode is cleared and Status Read is set for each slave in the system. The master then
set to IRR. will release byte 1 of the call sequence (for MCS-
f. If IC4 e 0, then all functions selected in ICW4 80/85 system) and will enable the corresponding
are set to zero. (Non-Buffered mode*, no Auto- slave to release bytes 2 and 3 (for 8086 only byte
a
EOI, MCS-80, 85 system). 2) through the cascade lines.
b. In the slave mode (either when SP e 0, or if BUF
*NOTE: e 1 and M/S e 0 in ICW4) bits 2 0 identify the
Master/Slave in ICW4 is only used in the buffered slave. The slave compares its cascade input with
mode.
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these bits and, if they are equal, bytes 2 and 3 of
the call sequence (or just byte 2 for 8086) are
released by it on the Data Bus.
Initialization Command Words 1 and 2
(ICW1, ICW2)
A5 A15: Page starting address of service routines .
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In an MCS 80/85 system, the 8 request levels will
generate CALLs to 8 locations equally spaced in
memory. These can be programmed to be spaced at
intervals of 4 or 8 memory locations, thus the 8 rou-
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tines will occupy a page of 32 or 64 bytes, respec-
tively.
a
a
The address format is 2 bytes long (A0 A15). When
the routine interval is 4, A0 A4 are automatically in-
serted by the 8259A, while A5 A15 are programmed
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externally. When the routine interval is 8, A0 A5 are
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automatically inserted by the 8259A, while A6 A15
are programmed externally.
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The 8-byte interval will maintain compatibility with
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current software, while the 4-byte interval is best for

a compact jump table.
In an 8086 system A15 A11 are inserted in the five

most significant bits of the vectoring byte and the
8259A sets the three least significant bits according
to the interrupt level. A10 A5 are ignored and ADI
(Address interval) has no effect.
LTIM: If LTIM e 1, then the 8259A will operate in
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the level interrupt mode. Edge detect logic

on the interrupt inputs will be disabled.
ADI: CALL address interval. ADI e 1 then inter-
val e 4; ADI e 0 then interval e 8.
SNGL: Single. Means that this is the only 8259A in
the system. If SNGL e 1 no ICW3 will be
issued.
IC4: If this bit is setICW4 has to be read. If
ICW4 is not needed, set IC4 e 0.
231468 9
Initialization Command Word 3 (ICW3) Figure 6. Initialization Sequence

This word is read only when there is more than one
8259A in the system and cascading is used, in which
10
8259A
Initialization Command Word 4 (ICW4) master, M/S e 0 means the 8259A is pro-
grammed to be a slave. If BUF e 0, M/S
SFNM: If SFNM e 1 the special fully nested mode
has no function.
is programmed.
AEOI: If AEOI e 1 the automatic end of interrupt
BUF: If BUF e 1 the buffered mode is pro-
mode is programmed.
grammed. In buffered mode SP/EN be-
comes an enable output and the master/ mPM: Microprocessor mode: mPM e 0 sets the
slave determination is by M/S. 8259A for MCS-80, 85 system operation,
a
mPM e 1 sets the 8259A for 8086 system
M/S: If buffered mode is selected: M/S e 1
operation.
means the 8259A is programmed to be a
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231468 10
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231468 11
Figure 7. Initialization Command Word Format
11
8259A
a
231468 12
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a 231468 13
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231468 14
NOTE:
Slave ID is equal to the corresponding master IR input.
Figure 7. Initialization Command Word Format (Continued)
12
8259A
OPERATION COMMAND WORDS Operation Control Words (OCWs)

(OCWS) OCW1
A0 D7 D6 D5 D4 D3 D2 D1 D0
After the Initialization Command Words (ICWs) are
programmed into the 8259A, the chip is ready to ac- 1 M7 M6 M5 M4 M3 M2 M1 M0
cept interrupt requests at its input lines. However,
during the 8259A operation, a selection of algo- OCW2
rithms can command the 8259A to operate in vari-
a
0 R SL EOI 0 0 L2 L1 L0
ous modes through the Operation Command Words
(OCWs). OCW3
0 0 ESMM SMM 0 1 P RR RIS
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231468 15
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231468 16
Figure 8. Operation Command Word Format
13
8259A
Operation Control Word 1 (OCW1) Operation Control Word 2 (OCW2)

OCW1 sets and clears the mask bits in the interrupt R, SL, EOIThese three bits control the Rotate and
Mask Register (IMR). M7 M0 represent the eight End of Interrupt modes and combinations of the two.
mask bits. M e 1 indicates the channel is masked A chart of these combinations can be found on the
(inhibited), M e 0 indicates the channel is enabled. Operation Command Word Format.
L2, L1, L0These bits determine the interrupt level
a
acted upon when the SL bit is active.
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231468 17
Figure 8. Operation Command Word Format (Continued)
14
8259A
Operation Control Word 3 (OCW3) When a mode is used which may disturb the fully
nested structure, the 8259A may no longer be able
ESMMEnable Special Mask Mode. When this bit to determine the last level acknowledged. In this
is set to 1 it enables the SMM bit to set or reset the case a Specific End of Interrupt must be issued
Special Mask Mode. When ESMM e 0 the SMM bit which includes as part of the command the IS level
becomes a dont care. to be reset. A specific EOI can be issued with OCW2
(EOI e 1, SL e 1, R e 0, and L0 L2 is the binary
SMMSpecial Mask Mode. If ESMM e 1 and SMM level of the IS bit to be reset).
a
e 1 the 8259A will enter Special Mask Mode. If
ESMM e 1 and SMM e 0 the 8259A will revert to It should be noted that an IS bit that is masked by an
normal mask mode. When ESMM e 0, SMM has no IMR bit will not be cleared by a non-specific EOI if
effect. the 8259A is in the Special Mask Mode.
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Fully Nested Mode Automatic End of Interrupt (AEOI)
Mode
This mode is entered after initialization unless anoth-
er mode is programmed. The interrupt requests are If AEOI e 1 in ICW4, then the 8259A will operate in
ordered in priority from 0 through 7 (0 highest). AEOI mode continuously until reprogrammed by
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When an interrupt is acknowledged the highest pri-
ority request is determined and its vector placed on
the bus. Additionally, a bit of the Interrupt Service
register (ISO-7) is set. This bit remains set until the
ICW4. in this mode the 8259A will automatically per-
form a non-specific EOI operation at the trailing
edge of the last interrupt acknowledge pulse (third
pulse in MCS-80/85, second in 8086). Note that
microprocessor issues an End of Interrupt (EOI) from a system standpoint, this mode should be used
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command immediately before returning from the only when a nested multilevel interrupt structure is
a
service routine, or if AEOI (Automatic End of Inter- not required within a single 8259A.
a
rupt) bit is set, until the trailing edge of the last INTA.
While the IS bit is set, all further interrupts of the
same or lower priority are inhibited, while higher lev-
The AEOI mode can only be used in a master 8259A
and not a slave. 8259As with a copyright date of
r
els will generate an interrupt (which will be acknowl- 1985 or later will operate in the AEOI mode as a
ad
edged only if the microprocessor internal Interupt master or a slave.
enable flip-flop has been re-enabled through soft-
t
ware).
Automatic Rotation
ec
After the initialization sequence, IR0 has the highest (Equal Priority Devices)
prioirity and IR7 the lowest. Priorities can be
changed, as will be explained, in the rotating priority In some applications there are a number of interrupt-
mode. ing devices of equal priority. In this mode a device,
after being serviced, receives the lowest priority, so
a device requesting an interrupt will have to wait, in
End of Interrupt (EOI) the worst case until each of 7 other devices are
serviced at most once . For example, if the priority
The In Service (IS) bit can be reset either automati- and in service status is:
cally following the trailing edge of the last in se-
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quence INTA pulse (when AEOI bit in ICW1 is set) or Before Rotate (IR4 the highest prioirity requiring
by a command word that must be issued to the service)
8259A before returning from a service routine (EOI
command). An EOI command must be issued twice
if in the Cascade mode, once for the master and
once for the corresponding slave.
There are two forms of EOI command: Specific and IS Status 231468 18
Non-Specific. When the 8259A is operated in modes
which perserve the fully nested structure, it can de-
termine which IS bit to reset on EOI. When a Non-
Specific EOI command is issued the 8259A will auto-
matically reset the highest IS bit of those that are
set, since in the fully nested mode the highest IS
Priority Status 231468 19
level was necessarily the last level acknowledged
and serviced. A non-specific EOI can be issued with
OCW2 (EOI e 1, SL e 0, R e 0).
15
8259A
After Rotate (IR4 was serviced, all other priorities ture during its execution under software control. For
rotated correspondingly) example, the routine may wish to inhibit lower priori-
ty requests for a portion of its execution but enable
some of them for another portion.
The difficulty here is that if an Interrupt Request is

acknowledged and an End of Interrupt command did
IS Status 231468 20
not reset its IS bit (i.e., while executing a service
a
routine), the 8259A would have inhibited all lower
priority requests with no easy way for the routine to
enable them.
That is where the Special Mask Mode comes in. In
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the special Mask Mode, when a mask bit is set in
Priority Status 231468 21
OCW1, it inhibits further interrupts at that level and
enables interrupts from all other levels (lower as well
There are two ways to accomplish Automatic Rota- as higher) that are not masked.
tion using OCW2, the Rotation on Non-Specific EOI
Command (R e 1, SL e 0, EOI e 1) and the Ro- Thus, any interrupts may be selectively enabled by
loading the mask register.
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tate in Automatic EOI Mode which is set by (R e 1,
SL e 0, EOI e 0) and cleared by (R e 0, SL e 0,
EOI e 0).
The special Mask Mode is set by OWC3 where:
SSMM e 1, SMM e 1, and cleared where SSMM e
1, SMM e 0.
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Specific Rotation
a
(Specific Priority) Poll Command
a
The programmer can change priorities by program-
ming the bottom priority and thus fixing all other pri-
In Poll mode the INT output functions as it normally
does. The microprocessor should ignore this output.
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orities; i.e., if IR5 is programmed as the bottom prior- This can be accomplished either by not connecting
ad
ity device, then IR6 will have the highest one. the INT output or by masking interrupts within the
microprocessor, thereby disabling its interrupt input.
t
The Set Priority command is issued in OCW2 where: Service to devices is achieved by software using a
R e 1, SL e 1, L0L2 is the binary priority level Poll command.
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code of the bottom priority device.

The Poll command is issued by setting P e 1 in
Observe that in this mode internal status is updated OCW3. The 8259A treats the next RD pulse to the
by software control during OCW2. However, it is in- 8259A (i.e., RD e 0, CS e 0) as an interrupt ac-
dependent of the End of Interrupt (EOI) command knowledge, sets the appropriate IS bit if there is a
(also executed by OCW2). Priority changes can be request, and reads the priority level. Interrupt is fro-
executed during an EOI command by using the Ro- zen from WR to RD.
tate on Specific EOI command in OCW2 (R e 1, SL
e 1, EOI e 1 and LOL2 e IR level to receive The word enabled onto the data bus during RD is:
bottom priority). D7 D6 D5 D4 D3 D2 D1 D0
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I W2 W1 W0
Interrupt Masks W0 W2: Binary code of the highest priority level

requesting service.
Each Interrupt Request input can bem masked indi-
I: Equal to 1 if there is an interrupt.
vidually by the Interrupt Mask Register (IMR) pro-
grammed through OCW1. Each bit in the IMR masks This mode is useful if there is a routine command
one interrupt channel if it is set (1). Bit 0 masks IR0, common to several levels so that the INTA se-
Bit 1 masks IR1 and so forth. Masking an IR channel quence is not needed (saves ROM space). Another
does not affect the other channels operation. application is to use the poll mode to expand the
number of priority levels to more than 64.
Special Mask Mode
Reading the 8259A Status
Some applications may require an interrupt service
routine to dynamically alter the system priority struc- The input status of several internal registers can be
read to update the user information on the system.
16
8259A
a
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NOTES:
a
231468 22
a 1. Master clear active only during ICW1.

2. FREEZE is active during INTA and poll sequences only.
3. Truth Table for a D-Latch.
C D Q Operation
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1 Di Di Follow
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0 X Qn-1 Hold
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Figure 9. Priority CellSimplified Logic Diagram
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The following registers can be read via OCW3 (IRR There is no need to write an OCW3 before every
and ISR or OCW1 [IMR] ). status read operation, as long as the status read
corresponds with the previous one; i.e., the 8259A
Interrupt Request Register (IRR): 8-bit register which remembers whether the IRR or ISR has been pre-
contains the levels requesting an interrupt to be ac- viously selected by the OCW3. This is not true when
knowledged. The highest request level is reset from poll is used.
the IRR when an interrupt is acknowledged. (Not af-
fected by IMR.) After initialization the 8259A is set to IRR.
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In-Service Register (ISR): 8-bit register which con- For reading the IMR, no OCW3 is needed. The out-
tains the priority levels that are being serviced. The put data bus will contain the IMR whenever RD is
ISR is updated when an End of Interrupt Command active and A0 e 1 (OCW1).
is issued.
Polling overrides status read when P e 1, RR e 1
Interrupt Mask Register: 8-bit register which con- in OCW3.
tains the interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a Edge and Level Triggered Modes
Read Register Command is issued with OCW3 (RR
e 1, RIS e 0.) This mode is programmed using bit 3 in ICW1.
The ISR can be read, when, prior to the RD pulse, a If LTIM e 0, an interrupt request will be recognized
Read Register Command is issued with OCW3 (RR by a low to high transition on an IR input. The IR
e 1, RIS e 1). input can remain high without generating another in-
terrupt.
17
8259A
a
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Di n Figure 10. IR Triggering Timing Requirements
231468 23
If LTIM e 1, an interrupt request will be recognized ing ICW4). This mode is similar to the normal nested
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by a high level on IR Input, and there is no need for mode with the following exceptions:
an edge detection. The interrupt request must be
a
a. When an interrupt request from a certain slave is
a
removed before the EOI command is issued or the
CPU interrupts is enabled to prevent a second inter-
rupt from occurring.
in service this slave is not locked out from the
masters priority logic and further interrupt re-
quests from higher priority IRs within the slave
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will be recognized by the master and will initiate
The priority cell diagram shows a conceptual circuit
ad
interrupts to the processor. (In the normal nested
of the level sensitive and edge sensitive input circuit- mode a slave is masked out when its request is in
t
ry of the 8259A. Be sure to note that the request service and no higher requests from the same
latch is a transparent D type latch. slave can be serviced.)
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In both the edge and level triggered modes the IR b. When exiting the Interrupt Service routine the
inputs must remain high until after the falling edge of software has to check whether the interrupt serv-
the first INTA. If the IR input goes low before this iced was the only one from that slave. This is
time a DEFAULT IR7 will occur when the CPU ac- done by sending a non-specific End of Interrupt
knowledges the interrupt. This can be a useful safe- (EOI) command to the slave and then reading its
guard for detecting interrupts caused by spurious In-Service register and checking for zero. If it is
noise glitches on the IR inputs. To implement this empty, a non-specific EOI can be sent to the
feature the IR7 routine is used for clean up simply master too. If not, no EOI should be sent.
executing a return instruction, thus ignoring the inter-
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rupt. If IR7 is needed for other purposes a default Buffered Mode

IR7 can still be detected by reading the ISR. A nor-
mal IR7 interrupt will set the corresponding ISR bit, a When the 8259A is used in a large system where
default IR7 wont. If a default IR7 routine occurs dur- bus driving buffers are required on the data bus and
ing a normal IR7 routine, however, the ISR will re- the cascading mode is used, there exists the prob-
main set. In this case it is necessary to keep track of lem of enabling buffers.
whether or not the IR7 routine was previously en-
tered. If another IR7 occurs it is a default. The buffered mode will structure the 8259A to send
an enable signal on SP/EN to enable the buffers. In
this mode, whenever the 8259As data bus outputs
The Special Fully Nest Mode are enabled, the SP/EN output becomes active.
This mode will be used in the case of a big system This modification forces the use of software pro-
where cascading is used, and the priority has to be gramming to determine whether the 8259A is a mas-
conserved within each slave. In this case the fully ter or a slave. Bit 3 in ICW4 programs the buffered
nested mode will be programmed to the master (us- mode, and bit 2 in ICW4 determines whether it is a
master or a slave.
18
8259A
CASCADE MODE The cascade bus lines are normally low and will con-
tain the slave address code from the trailing edge of
The 8259A can be easily interconnected in a system the first INTA pulse to the trailing edge of the third
of one master with up to eight slaves to handle up to pulse. Each 8259A in the system must follow a sep-
64 priority levels. arate initialization sequence and can be pro-
grammed to work in a different mode. An EOI com-
The master controls the slaves through the 3 line mand must be issued twice: once for the master and
cascade bus. The cascade bus acts like chip selects once for the corresponding slave. An address de-
a
to the slaves during the INTA sequence. coder is required to activate the Chip Select (CS)
input of each 8259A.
In a cascade configuration, the slave interrupt out-
puts are connected to the master interrupt request The cascade lines of the Master 8259A are activat-
inputs. When a slave request line is activated and ed only for slave inputs, non-slave inputs leave the
Ap git ic
afterwards acknowledged, the master will enable the cascade line inactive (low).
corresponding slave to release the device routine
address during bytes 2 and 3 of INTA. (Byte 2 only
for 8086/8088).
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231468 24
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Figure 11. Cascading the 8259A
19
8259A
Ambient Temperature Under Bias 0 C to 70 C
Storage Temperature b 65 C to a 150 C Maximum Ratings may cause permanent damage.
Voltage on Any Pin These are stress ratings only. Operation beyond the
with Respect to Ground b 0.5V to a 7V Operating Conditions is not recommended and ex-
tended exposure beyond the Operating Conditions
Power Dissipation 1W may affect device reliability.
a
D.C. CHARACTERISTICS TA e 0 C to 70 C, VCC e 5V g 10%
Symbol Parameter Min Max Units Test Conditions
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VIL Input Low Voltage b 0.5 0.8 V
VIH Input High Voltage 2.0* VCC a 0.5V V
VOL Output Low Voltage 0.45 V IOL e 2.2 mA
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VOH(INT) Interrupt Output High
Voltage
3.5
2.4
V
V
IOH e b 100 mA
IOH e b 400 mA
ILI Input Load Current b 10 a 10 mA 0V s VIN s VCC
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ILOL Output Leakage Current b 10 a 10 mA 0.45V s VOUT s VCC
a
a
ICC
ILIR
VCC Supply Current
IR Input Load Current
85
b 300
mA
mA VIN e 0
r
10 mA VIN e VCC
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*NOTE:
t
For Extended Temperature EXPRESS VIH e 2.3V.
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CAPACITANCE TA e 25 C; VCC e GND e 0V

Symbol Parameter Min Typ Max Unit Test Conditions
CIN Input Capacitance 10 pF fc e 1 MHz
CI/O I/O Capacitance 20 pF Unmeasured Pins Returned to VSS
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20
8259A
A.C. CHARACTERISTICS TA e 0 C to 70 C, VCC e 5V g 10%
TIMING REQUIREMENTS
8259A 8259A-2
Symbol Parameter Units Test Conditions
Min Max Min Max
TAHRL AO/CS Setup to RD/INTA v 0 0 ns
a
TRHAX AO/CS Hold after RD/INTA u 0 0 ns
TRLRH RD Pulse Width 235 160 ns
TAHWL AO/CS Setup to WR v 0 0 ns
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TWHAX AO/CS Hold after WRu 0 0 ns
TWLWH WR Pulse Width 290 190 ns
TDVWH Data Setup to WR u 240 160 ns
TWHDX Data Hold after WR u 0 0 ns
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TJLJH
TCVIAL
Interrupt Request Width (Low)
Cascade Setup to Second or Third
100
55
100
40
ns
ns
See Note 1
v
INTA (Slave Only)
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TRHRL End of RD to Next RD
a
TWHWL
a End of INTA to Next INTA within
an INTA Sequence Only
End of WR to Next WR
160
190
100
100
ns
ns
r
*TCHCL End of Command to Next Command
ad
500 150 ns
(Not Same Command Type)
t
End of INTA Sequence to Next
500 300
INTA Sequence.
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*Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A e
1.6 ms, 8085A-2 e 1 ms, 8086 e 1 ms, 8086-2 e 625 ns)
NOTE:
This is the low time required to clear the input latch in the edge triggered mode.
TIMING RESPONSES
8259A 8259A-2
Symbol Parameter Units Test Conditions
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Min Max Min Max

TRLDV Data Valid from RD/INTA v 200 120 ns
C of Data Bus e
100 pF
TRHDZ Data Float after RD/INTA u 10 100 10 85 ns C of Data Bus
Max Test C e 100 pF
TJHIH Interrupt Output Delay 350 300 ns
Min Test C e 15 pF
TIALCV Cascade Valid from First INTA v 565 360 ns CINT e 100 pF
(Master Only)
TRLEL Enable Active from RD v or INTAv 125 100 ns
CCASCADE e 100 pF
TRHEH Enable Inactive from RDu or INTAu 150 150 ns
TAHDV Data Valid from Stable Address 200 200 ns
TCVDV Cascade Valid to Valid Data 300 200 ns
21
8259A
A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
a
231468 25
A.C. Testing: Inputs are driven at 2.4V for a logic 1 and 0.45V 231468 26
for a logic 0. Timing measurements are made at 2.0V for a logic CL e 100 pF
1 and 0.8V for a logic 0. CL Includes Jig Capacitance
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WAVEFORMS
WRITE
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231468 27
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22
8259A
READ/INTA
a
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231468 28
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OTHER TIMING
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231468 29
23
8259A
INTA SEQUENCE
a
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NOTES:
Interrupt output must remain HIGH at least until leading edge of first INTA.
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1. Cycle 1 in 8086, 8088 systems, the Data Bus is not active.
Data Sheet Revision Review

The following changes have been made since revision 2 of the 8259A data sheet.
1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin.
2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin during
El
multiple interrupts.
3. A reference to PLCC packaging was added.
4. All references to the 8259A-8 have been deleted.
INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080
INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000
INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511
Printed in U.S.A./xxxx/1196/B10M/xx xx
8237A
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
(8237A-5)
Y Enable/Disable Control of Individual Y Directly Expandable to Any Number of
a
DMA Requests Channels
Y Four Independent DMA Channels Y End of Process Input for Terminating
Y Independent Autoinitialization of All Transfers
Channels Y Software DMA Requests
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Y Memory-to-Memory Transfers Y Independent Polarity Control for DREQ
Y Memory Block Initialization and DACK Signals
Y Address Increment or Decrement
Y Available in EXPRESS
Standard Temperature Range
Y High Performance: Transfers up to
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1.6M Bytes/Second with 5 MHz 8237A-5
Y Available in 40-Lead Cerdip and Plastic
Packages
(See Packaging Spec, Order 231369)
The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microproc-
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essor systems. It is designed to improve system performance by allowing external devices to directly transfer
a
a
information from the system memory. Memory-to-memory transfer capability is also provided. The 8237A
offers a wide variety of programmable control features to enhance data throughput and system optimization
and to allow dynamic reconfiguration under program control.
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The 8237A is designed to be used in conjunction with an external 8-bit address latch. It contains four indepen-
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dent channels and may be expanded to any number of channels by cascading additional controller chips. The
three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can
t
be individually programmed to Autoinitialize to its original condition following an End of Process (EOP). Each
channel has a full 64K address and word count capability.
ec
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231466 2
Figure 2. Pin
Configuration
231466 1
Figure 1. Block Diagram
September 1993 Order Number: 231466-005

8237A

VCC POWER: a 5V supply.
VSS GROUND: Ground.
CLK I CLOCK INPUT: Clock Input controls the internal operations of the
8237A and its rate of data transfers. The input may be driven at up
a
to 5 MHz for the 8237A-5.
CS I CHIP SELECT: Chip Select is an active low input used to select
the 8237A as an I/O device during the Idle cycle. This allows CPU
communication on the data bus.
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RESET I RESET: Reset is an active high input which clears the Command,
Status, Request and Temporary registers. It also clears the first/
last flip/flop and sets the Mask register. Following a Reset the
device is in the Idle cycle.
READY I READY: Ready is an input used to extend the memory read and
Di n write pulses from the 8237A to accommodate slow memories or
I/O peripheral devices. Ready must not make transitions during its
specified setup/hold time.
HLDA I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from
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the CPU indicates that it has relinquished control of the system
busses.
a
a
DREQ0 DREQ3 I DMA REQUEST: The DMA Request lines are individual
asynchronous channel request inputs used by peripheral circuits to
obtain DMA service. In fixed Priority, DREQ0 has the highest
r
priority and DREQ3 has the lowest priority. A request is generated
ad
by activating the DREQ line of a channel. DACK will acknowledge
the recognition of DREQ signal. Polarity of DREQ is
t
programmable. Reset initializes these lines to active high. DREQ
must be maintained until the corresponding DACK goes active.
ec
DB0DB7 I/O DATA BUS: The Data Bus lines are bidirectional three-state
signals connected to the system data bus. The outputs are
enabled in the Program condition during the I/O Read to output
the contents of an Address register, a Status register, the
Temporary register or a Word Count register to the CPU. The
outputs are disabled and the inputs are read during an I/O Write
cycle when the CPU is programming the 8237A control registers.
During DMA cycles the most significant 8 bits of the address are
output onto the data bus to be strobed into an external latch by
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ADSTB. In memory-to-memory operations, data from the memory

comes into the 8237A on the data bus during the read-from-
memory transfer. In the write-to-memory transfer, the data bus
outputs place the data into the new memory location.
IOR I/O I/O READ: I/O Read is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to
read the control registers. In the Active cycle, it is an output control
signal used by the 8237A to access data from a peripheral during a
DMA Write transfer.
IOW I/O I/O WRITE: I/O Write is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to
load information into the 8237A. In the Active cycle, it is an output
control signal used by the 8237A to load data to the peripheral
during a DMA Read transfer.
2
8237A
Table 1. Pin Description (Continued)

EOP I/O END OF PROCESS: End of Process is an active low bidirectional
signal. Information concerning the completion of DMA services is
available at the bidirectional EOP pin. The 8237A allows an
external signal to terminate an active DMA service. This is
accomplished by pulling the EOP input low with an external EOP
a
signal. The 8237A also generates a pulse when the terminal count
(TC) for any channel is reached. This generates an EOP signal
which is output through the EOP line. The reception of EOP, either
internal or external, will cause the 8237A to terminate the service,
reset the request, and, if Autoinitialize is enabled, to write the base
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registers to the current registers of that channel. The mask bit and
TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for Autoinitialize. In that
case, the mask bit remains unchanged. During memory-to-memory
transfers, EOP will be output when the TC for channel 1 occurs.
EOP should be tied high with a pull-up resistor if it is not used to
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A0A3 I/O
prevent erroneous end of process inputs.
ADDRESS: The four least significant address lines are
bidirectional three-state signals. In the Idle cycle they are inputs
and are used by the CPU to address the register to be loaded or
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read. In the Active cycle they are outputs and provide the lower 4
bits of the output address.
a
A4A7
a O ADDRESS: The four most significant address lines are three-state

outputs and provide 4 bits of address. These lines are enabled
only during the DMA service.
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HRQ O HOLD REQUEST: This is the Hold Request to the CPU and is
used to request control of the system bus. If the corresponding
t
mask bit is clear, the presence of any valid DREQ causes 8237A to
issue the HRQ.
ec
DACK0DACK3 O DMA ACKNOWLEDGE: DMA Acknowledge is used to notify the

individual peripherals when one has been granted a DMA cycle.
The sense of these lines is programmable. Reset initializes them
to active low.
AEN O ADDRESS ENABLE: Address Enable enables the 8-bit latch
containing the upper 8 address bits onto the system address bus.
AEN can also be used to disable other system bus drivers during
DMA transfers. AEN is active HIGH.
El
ADSTB O ADDRESS STROBE: The active high, Address Strobe is used to

strobe the upper address byte into an external latch.
MEMR O MEMORY READ: The Memory Read signal is an active low three-
state output used to access data from the selected memory
location during a DMA Read or a memory-to-memory transfer.
MEMW O MEMORY WRITE: The Memory Write is an active low three-state
output used to write data to the selected memory location during a
DMA Write or a memory-to-memory transfer.
PIN5 I PIN5: This pin should always be at a logic HIGH level. An internal
pull-up resistor will establish a logic high when the pin is left
floating. It is recommended however, that PIN5 be connected to
VCC.
3
8237A
FUNCTIONAL DESCRIPTION valid DMA requests pending. While in SI, the DMA
controller is inactive but may be in the Program Con-
The 8237A block diagram includes the major logic dition, being programmed by the processor. State
blocks and all of the internal registers. The data in- S0 (S0) is the first state of a DMA service. The
terconnection paths are also shown. Not shown are 8237A has requested a hold but the processor has
the various control signals between the blocks. The not yet returned an acknowledge. The 8237A may
8237A contains 344 bits of internal memory in the still be programmed until it receives HLDA from the
form of registers. Figure 3 lists these registers by CPU. An acknowledge from the CPU will signal that
a
name and shows the size of each. A detailed de- DMA transfers may begin. S1, S2, S3 and S4 are the
scription of the registers and their functions can be working states of the DMA service. If more time is
found under Register Description. needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted be-
tween S2 or S3 and S4 by the use of the Ready line
Ap git ic
Name Size Number
Base Address Registers 16 bits 4
on the 8237A. Note that the data is transferred di-
Base Word Count Registers 16 bits 4 rectly from the I/O device to memory (or vice versa)
Current Address Registers 16 bits 4 with IOR and MEMW (or MEMR and IOW) being ac-
Current Word Count Registers 16 bits 4 tive at the same time. The data is not read into or
Temporary Address Register 16 bits 1
Temporary Word Count Register 16 bits 1
driven out of the 8237A in I/O-to-memory or memo-
Status Register 8 bits 1 ry-to-I/O DMA transfers.
Di n
Command Register
Temporary Register
Mode Registers
Mask Register
Request Register
8 bits
8 bits
6 bits
4 bits
4 bits
1
1
4
1
1
Memory-to-memory transfers require a read-from
and a write-to-memory to complete each transfer.
The states, which resemble the normal working
states, use two digit numbers for identification. Eight
lic l
Figure 3. 8237A Internal Registers
states are required for a single transfer. The first four
a
states (S11, S12, S13, S14) are used for the read-
a
The 8237A contains three basic blocks of control
logic. The Timing Control block generates internal
timing and external control signals for the 8237A.
from-memory half and the last four states (S21, S22,
S23, S24) for the write-to-memory half of the trans-
fer.
r
The Program Command Control block decodes the
various commands given to the 8237A by the micro-
ad
processor prior to servicing a DMA Request. It also IDLE CYCLE
t
decodes the Mode Control word used to select the
type of DMA during the servicing. The Priority En- When no channel is requesting service, the 8237A
coder block resolves priority contention between will enter the Idle cycle and perform SI states. In
ec
DMA channels requesting service simultaneously. this cycle the 8237A will sample the DREQ lines ev-
ery clock cycle to determine if any channel is re-
The Timing Control block derives internal timing questing a DMA service. The device will also sample
from the clock input. In 8237A systems, this input CS, looking for an attempt by the microprocessor to
will usually be the w2 TTL clock from an 8224 or write or read the internal registers of the 8237A.
CLK from an 8085AH or 8284A. 33% duty cycle When CS is low and HLDA is low, the 8237A enters
clock generators, however, may not meet the clock the Program Condition. The CPU can now establish,
high time requirement of the 8237A of the same fre- change or inspect the internal definition of the part
quency. For example, 82C84A-5 CLK output violates by reading from or writing to the internal registers.
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the clock high time requirement of 8237A-5. In this Address lines A0 A3 are inputs to the device and
case 82C84A CLK can simply be inverted to meet select which registers will be read or written. The
8237A-5 clock high and low time requirements. For IOR and IOW lines are used to select and time reads
8085AH-2 systems above 3.9 MHz, the 8085 or writes. Due to the number and size of the internal
CLK(OUT) does not satisfy 8237A-5 clock LOW and registers, an internal flip-flop is used to generate an
HIGH time requirements. In this case, an external additional bit of address. This bit is used to deter-
clock should be used to drive the 8237A-5. mine the upper or lower byte of the 16-bit Address
and Word Count registers. The flip-flop is reset by
Master Clear or Reset. A separate software com-
DMA OPERATION mand can also reset this flip-flop.
The 8237A is designed to operate in two major cy- Special software commands can be executed by the
cles. These are called Idle and Active cycles. Each 8237A in the Program Condition. These commands
device cycle is made up of a number of states. The are decoded as sets of addresses with the CS and
8237A can assume seven separate states, each IOW. The commands do not make use of the data
composed of one full clock period. State I (SI) is the bus. Instructions include Clear First/Last Flip-Flop
inactive state. It is entered when the 8237A has no and Master Clear.
4
8237A
ACTIVE CYCLE Process (EOP) is encountered. DREQ need only be

held active until DACK becomes active. Again, an
When the 8237A is in the Idle cycle and a non- Autoinitialization will occur at the end of the service
masked channel requests a DMA service, the device if the channel has been programmed for it.
will output an HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA serv- Demand Transfer ModeIn Demand Transfer
ice will take place, in one of four modes: mode the device is programmed to continue making
transfers until a TC or external EOP is encountered
a
Single Transfer ModeIn Single Transfer mode or until DREQ goes inactive. Thus transfers may
the device is programmed to make one transfer only. continue until the I/O device has exhausted its data
The word count will be decremented and the ad- capacity. After the I/O device has had a chance to
dress decremented or incremented following each catch up, the DMA service is re-established by
transfer. When the word count rolls over from zero means of a DREQ. During the time between services
Ap git ic
to FFFFH, a Terminal Count (TC) will cause an Auto- when the microprocessor is allowed to operate, the
initialize if the channel has been programmed to do intermediate values of address and word count are
so. stored in the 8237A Current Address and Current
Word Count registers. Only an EOP can cause an
DREQ must be held active until DACK becomes ac- Autoinitialize at the end of the service. EOP is gener-
tive in order to be recognized. If DREQ is held active ated either by TC or by an external signal. DREQ
Di n
throughout the single transfer, HRQ will go inactive
and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another
single transfer will be performed. In 8080A, 8085AH,
has to be low before S4 to prevent another Transfer.
Cascade ModeThis mode is used to cascade

more than one 8237A together for simple system
8088, or 8086 system, this will ensure one full ma- expansion. The HRQ and HLDA signals from the ad-
lic l
chine cycle execution between DMA transfers. De- ditional 8237A are connected to the DREQ and
a
tails of timing between the 8237A and other bus DACK signals of a channel of the initial 8237A. This
a
control protocols will depend upon the characteris-
tics of the microprocessor involved.
allows the DMA requests of the additional device to
propagate through the priority network circuitry of
the preceding device. The priority chain is preserved
r
Block Transfer ModeIn Block Transfer mode the and the new device must wait for its turn to acknowl-
ad
device is activated by DREQ to continue making edge requests. Since the cascade channel of the
transfers during the service until a TC, caused by initial 8237A is used only for prioritizing the addition-
t
word count going to FFFFH, or an external End of al device, it does not output any address or control
ec
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231466 3
Figure 4. Cascaded 8237As
5
8237A
signals of its own. These could conflict with the out- The 8237A will respond to external EOP signals dur-
puts of the active channel in the added device. The ing memory-to-memory transfers. Data comparators
8237A will respond to DREQ and DACK but all other in block search schemes may use this input to termi-
outputs except HRQ will be disabled. The ready in- nate the service when a match is found. The timing
put is ignored. of memory-to-memory transfers is found in Figure
12. Memory-to-memory operations can be detected
Figure 4 shows two additional devices cascaded into as an active AEN with no DACK outputs.
an initial device using two of the previous channels.
a
This forms a two level DMA system. More 8237As AutoinitializeBy programming a bit in the Mode
could be added at the second level by using the register, a channel may be set up as an Autoinitialize
remaining channels of the first level. Additional de- channel. During Autoinitialize initialization, the origi-
vices can also be added by cascading into the chan- nal values of the Current Address and Current Word
nels of the second level device, forming a third level. Count registers are automatically restored from the
Ap git ic
Base Address and Base Word count registers of that
channel following EOP. The base registers are load-
TRANSFER TYPES ed simultaneously with the current registers by the
Each of the three active transfer modes can perform microprocessor and remain unchanged throughout
three different types of transfers. These are Read, the DMA service. The mask bit is not altered when
Write and Verify. Write transfers move data from an the channel is in Autoinitialize. Following Autoinitial-
Di n
I/O device to the memory by activating MEMW and
IOR. Read transfers move data from memory to an
I/O device by activating MEMR and IOW. Verify
transfers are pseudo transfers. The 8237A operates
ize the channel is ready to perform another DMA
service, without CPU intervention, as soon as a valid
DREQ is detected. In order to Autoinitialize both
channels in a memory-to-memory transfer, both
word counts should be programmed identically. If in-
lic l
as in Read or Write transfers generating addresses,
terrupted externally, EOP pulses should be applied
and responding to EOP, etc. However, the memory
a
in both bus cycles.
a
and I/O control lines all remain inactive. The ready
input is ignored in verify mode.
PriorityThe 8237A has two types of priority en-
coding available as software selectable options. The
r
Memory-to-MemoryTo perform block moves of
data from one memory address space to another first is Fixed Priority which fixes the channels in pri-
ad
with a minimum of program effort and time, the ority order based upon the descending value of their
number. The channel with the lowest priority is 3
t
8237A includes a memory-to-memory transfer fea-
ture. Programming a bit in the Command register followed by 2, 1 and the highest priority channel, 0.
selects channels 0 and 1 to operate as memory-to- After the recognition of any one channel for service,
ec
memory transfer channels. The transfer is initiated the other channels are prevented from interfering
by setting the software DREQ for channel 0. The with that service until it is completed.
8237A requests a DMA service in the normal man-
ner. After HLDA is true, the device, using four state After completion of a service, HRQ will go inactive
transfers in Block Transfer mode, reads data from and the 8237A will wait for HLDA to go low before
the memory. The channel 0 Current Address register activating HRQ to service another channel.
is the source for the address used and is decrement-
ed or incremented in the normal manner. The data The second scheme is Rotating Priority. The last
byte read from the memory is stored in the 8237A channel to get service becomes the lowest priority
channel with the others rotating accordingly.
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internal Temporary register. Channel 1 then per-

forms a four-state transfer of the data from the Tem-
porary register to memory using the address in its
Current Address register and incrementing or decre-
menting it in the normal manner. The channel 1 cur-
rent Word Count is decremented. When the word
count of channel 1 goes to FFFFH, a TC is generat-
ed causing an EOP output terminating the service.
231466 4
Channel 0 may be programmed to retain the same
address for all transfers. This allows a single word to
be written to a block of memory.
6
8237A
With Rotating Priority in a single chip DMA system, Current Word RegisterEach channel has a 16-
any device requesting service is guaranteed to be bit Current Word Count register. This register deter-
recognized after no more than three higher priority mines the number of transfers to be performed. The
services have occurred. This prevents any one actual number of transfers will be one more than the
channel from monopolizing the system. number programmed in the Current Word Count reg-
ister (i.e., programming a count of 100 will result in
Compressed TimingIn order to achieve even 101 transfers). The word count is decremented after
greater throughput where system characteristics each transfer. The intermediate value of the word
a
permit, the 8237A can compress the transfer time to count is stored in the register during the transfer.
two clock cycles. From Figure 11 it can be seen that When the value in the register goes from zero to
state S3 is used to extend the access time of the FFFFH, a TC will be generated. This register is load-
read pulse. By removing state S3, the read pulse ed or read in successive 8-bit bytes by the micro-
width is made equal to the write pulse width and a processor in the Program Condition. Following the
Ap git ic
transfer consists only of state S2 to change the ad- end of a DMA service it may also be reinitialized by
dress and state S4 to perform the read/write. S1 an Autoinitialization back to its original value. Auto-
states will still occur when A8A15 need updating initialize can occur only when an EOP occurs. If it is
(see Address Generation). Timing for compressed not Autoinitialized, this register will have a count of
transfers is found in Figure 14.
Di n FFFFH after TC.
Address GenerationIn order to reduce pin count, Base Address and Base Word Count Registers
the 8237A multiplexes the eight higher order ad- Each channel has a pair of Base Address and Base
dress bits on the data lines. State S1 is used to out- Word Count registers. These 16-bit registers store
put the higher order address bits to an external latch the original value of their associated current regis-
from which they may be placed on the address bus. ters. During Autoinitialize these values are used to
lic l
The falling edge of Address Strobe (ADSTB) is used restore the current registers to their original values.
a
to load these bits from the data lines to the latch. The base registers are written simultaneously with
a
Address Enable (AEN) is used to enable the bits
onto the address bus through a three-state enable.
The lower order address bits are output by the
their corresponding current register in 8-bit bytes in
the Program Condition by the microprocessor.
These registers cannot be read by the microproces-
r
8237A directly. Lines A0A7 should be connected sor.
ad
to the address bus. Figure 11 shows the time rela-
tionships between CLK, AEN, ADSTB, DB0 DB7 Command RegisterThis 8-bit register controls
t
and A0A7. the operation of the 8237A. It is programmed by the
microprocessor in the Program Condition and is
ec
During Block and Demand Transfer mode services, cleared by Reset or a Master Clear instruction. The
which include multiple transfers, the addresses gen- following table lists the function of the command
erated will be sequential. For many transfers the bits. See Figure 6 for address coding.
data held in the external address latch will remain
the same. This data need only change when a carry Mode RegisterEach channel has a 6-bit Mode
or borrow from A7 to A8 takes place in the normal register associated with it. When the register is being
sequence of addresses. To save time and speed written to by the microprocessor in the Program
transfers, the 8237A executes S1 states only when Condition, bits 0 and 1 determine which channel
updating of A8A15 in the latch is necessary. This Mode register is to be written.
means for long services, S1 states and Address
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Strobes may occur only once every 256 transfers, a Request RegisterThe 8237A can respond to re-
savings of 255 clock cycles for each 256 transfers. quests for DMA service which are initiated by soft-
ware as well as by a DREQ. Each channel has a
request bit associated with it in the 4-bit Request
REGISTER DESCRIPTION register. These are non-maskable and subject to pri-
oritization by the Priority Encoder network. Each reg-
Current Address RegisterEach channel has a ister bit is set or reset separately under software
16-bit Current Address register. This register holds control or is cleared upon generation of a TC or ex-
the value of the address used during DMA transfers. ternal EOP. The entire register is cleared by a Reset.
The address is automatically incremented or decre- To set or reset a bit, the software loads the proper
mented after each transfer and the intermediate val- form of the data word. See Figure 5 for register ad-
ues of the address are stored in the Current Address dress coding. In order to make a software request,
register during the transfer. This register is written or the channel must be in Block Mode.
read by the microprocessor in successive 8-bit
bytes. It may also be reinitialized by an Autoinitialize
back to its original value. Autoinitialize takes place
only after an EOP.
7
8237A
Command Register Mask RegisterEach channel has associated with

it a mask bit which can be set to disable the incom-
ing DREQ. Each mask bit is set when its associated
channel produces an EOP if the channel is not pro-
grammed for Autoinitialize. Each bit of the 4-bit
Mask register may also be set or cleared separately
under software control. The entire register is also set
by a Reset. This disables all DMA requests until a
a
clear Mask register instruction allows them to occur.
The instruction to separately set or clear the mask
bits is similar in form to that used with the Request
register. See Figure 5 for instruction addressing.
Ap git ic
Di n 231466 8
lic l
231466 5 All four bits of the Mask register may also be written
a
a
Mode Register
with a single command.
r
ad
t
ec
231466 9
Signals
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Register Operation
CS IOR IOW A3 A2 A1 A0
Command Write 0 1 0 1 0 0 0
231466 6 Mode Write 0 1 0 1 0 1 1
Request Write 0 1 0 1 0 0 1
Request Register Mask Set/Reset 0 1 0 1 0 1 0
Mask Write 0 1 0 1 1 1 1
Temporary Read 0 0 1 1 1 0 1
Status Read 0 0 1 1 0 0 0
Figure 5. Definition of Register Codes
Status RegisterThe Status register is available to

be read out of the 8237A by the microprocessor. It
contains information about the status of the devices
231466 7 at this point. This information includes which chan-
nels have reached a terminal count and which chan-
8
8237A
a
231466 10
Ap git ic
nels have pending DMA requests. Bits 03 are set Clear First/Last Flip-Flop: This command must be
every time a TC is reached by that channel or an executed prior to writing or reading new address
external EOP is applied. These bits are cleared upon or word count information to the 8237A. This ini-
Reset and on each Status Read. Bits 47 are set tializes the flip-flop to a known state so that sub-
whenever their corresponding channel is requesting sequent accesses to register contents by the mi-
Di n
service.
Temporary RegisterThe Temporary register is

used to hold data during memory-to-memory trans-
croprocessor will address upper and lower bytes
in the correct sequence.
Master Clear: This software instruction has the

fers. Following the completion of the transfers, the same effect as the hardware Reset. The Com-
lic l
last word moved can be read by the microprocessor mand, Status, Request, Temporary, and Internal
in the Program Condition. The Temporary register First/Last Flip-Flop registers are cleared and the
a
a
always contains the last byte transferred in the previ-
ous memory-to-memory operation, unless cleared
by a Reset.
Mask register is set. The 8237A will enter the Idle
cycle.
r
Clear Mask Register: This command clears the
ad
Software CommandsThese are additional spe- mask bits of all four channels, enabling them to
cial software commands which can be executed in accept DMA requests.
t
the Program Condition. They do not depend on any
specific bit pattern on the data bus. The three soft- Figure 6 lists the address codes for the software
ec
ware commands are: commands.
Signals
Operation
A3 A2 A1 A0 IOR IOW
1 0 0 0 0 1 Read Status Register
1 0 0 0 1 0 Write Command Register
1 0 0 1 0 1 Illegal
1 0 0 1 1 0 Write Request Register
1 0 1 0 0 1 Illegal
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1 0 1 0 1 0 Write Single Mask Register Bit

1 0 1 1 0 1 Illegal
1 0 1 1 1 0 Write Mode Register
1 1 0 0 0 1 Illegal
1 1 0 0 1 0 Clear Byte Pointer Flip/Flop
1 1 0 1 0 1 Read Temporary Register
1 1 0 1 1 0 Master Clear
1 1 1 0 0 1 Illegal
1 1 1 0 1 0 Clear Mask Register
1 1 1 1 0 1 Illegal
1 1 1 1 1 0 Write All Mask Register Bits
Figure 6. Software Command Codes
9
8237A
Signals Internal Data Bus

Channel Register Operation
CS IOR IOW A3 A2 A1 A0 Flip-Flop DB0 DB7
0 Base and Current Address Write 0 1 0 0 0 0 0 0 A0 A7
0 1 0 0 0 0 0 1 A8 A15
Current Address Read 0 0 1 0 0 0 0 0 A0 A7
0 0 1 0 0 0 0 1 A8 A15
a
Base and Current Word Count Write 0 1 0 0 0 0 1 0 W0 W7
0 1 0 0 0 0 1 1 W8 W15
Current Word Count Read 0 0 1 0 0 0 1 0 W0 W7
Ap git ic
0 0 1 0 0 0 1 1 W8 W15
0 1 0 0 0 1 0 1 A8 A15
0 0 1 0 0 1 0 1 A8 A15
Di n Base and Current Word Count
Current Word Count

Write
Read
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
W0 W7
W8 W15
W0 W7
lic l
0 0 1 0 0 1 1 1 W8 W15
a
a Current Address Read

0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
0
A8 A15
A0 A7
r
0 0 1 0 1 0 0 1 A8 A15
ad
t
0 1 0 0 1 0 1 1 W8 W15
ec
0 0 1 0 1 0 1 1 W8 W15
0 1 0 0 1 1 0 1 A8 A15
0 0 1 0 1 1 0 1 A8 A15
0 1 0 0 1 1 1 1 W8 W15
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0 0 1 0 1 1 1 1 W8 W15
Figure 7. Word Count and Address Register Command Codes
10
8237A
PROGRAMMING channels are unused. An invalid mode may force all

control signals to go active at the same time.
The 8237A will accept programming from the host
processor any time that HLDA is inactive; this is true
even if HRQ is active. The responsibility of the host APPLICATION INFORMATION (Note 1)
is to assure that programming and HLDA are mutual-
Figure 8 shows a convenient method for configuring
ly exclusive. Note that a problem can occur if a DMA
a DMA system with the 8237A controller and an
request occurs, on an unmasked channel while the
8080A/8085AH microprocessor system. The multi-
a
8237A is being programmed. For instance, the CPU mode DMA controller issues a HRQ to the processor
may be starting to reprogram the two byte Address
whenever there is at least one valid DMA request
register of channel 1 when channel 1 receives a
from a peripheral device. When the processor re-
DMA request. If the 8237A is enabled (bit 2 in the
plies with a HLDA signal, the 8237A takes control of
command register is 0) and channel 1 is unmasked,
Ap git ic
the address bus, the data bus and the control bus.
a DMA service will occur after only one byte of the
The address for the first transfer operation comes
Address register has been reprogrammed. This can
out in two bytesthe least significant 8 bits on the
be avoided by disabling the controller (setting bit 2 in
eight address outputs and the most significant 8 bits
the command register) or masking the channel be-
on the data bus. The contents of the data bus are
fore programming any other registers. Once the pro-
then latched into an 8-bit latch to complete the full
gramming is complete, the controller can be en-
16 bits of the address bus. The 8282 is a high
Di n
abled/unmasked.
After power-up it is suggested that all internal loca-

tions, especially the Mode registers, be loaded with
speed, 8-bit, three-state latch in a 20-pin package.
After the initial transfer takes place, the latch is up-
dated only after a carry or borrow is generated in the
least significant address byte. Four DMA channels
some valid value. This should be done even if some
lic l
are provided when one 8237A is used.
a
a
r
ad
t
ec
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231466 11
Figure 8. 8237A System Interface

NOTE:
1. See Application Note AP-67 for 8086 design information.
11
8237A
Ambient Temperature under Bias 0 C to 70 C
Case Temperature 0 C to a 75 C Maximum Ratings may cause permanent damage.
Storage Temperature b 65 C to a 150 C These are stress ratings only. Operation beyond the
Operating Conditions is not recommended and ex-
Voltage on Any Pin with tended exposure beyond the Operating Conditions
Respect to Ground b 0.5V to a 7V may affect device reliability.
a
Power Dissipation1.5 Watt
D.C. CHARACTERISTICS
Ap git ic
TA e 0 C to 70 C, TCASE e 0 C to 75 C, VCC e a 5.0V g 5%, GND e 0V
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 1)
3.3 V IOH e b 100 mA (HRQ Only)
Di n
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
2.0
b 0.5
0.40
VCC a 0.5
0.8
V
V
V
IOL e 3.2 mA
lic l
ILI Input Load Current g 10 mA 0V s VIN s VCC
a
ILO
ICC
a Output Leakage Current

VCC Supply Current 110
130
g 10
130
150
mA
mA
mA
0.45V s VOUT s VCC
TA e a 25 C
TA e 0 C
r
CO Output Capacitance 4 8 pF
CI
ad Input Capacitance 8 15 pF fc e 1.0 MHz, Inputs e 0V

t
CIO I/O Capacitance 10 18 pF
ec
NOTE:
1. Typical values are for TA e 25 C, nominal supply voltage and nominal processing parameters.
El
12
8237A
A.C. CHARACTERISTICSDMA (MASTER) MODE

TA e 0 C to 70 C, TCASE e 0 C to 75 C, VCC e a 5V g 5%, GND e 0V
8237A-5
Min Max
TAEL AEN HIGH from CLK LOW (S1) Delay Time 200 ns
TAET AEN LOW from CLK HIGH (SI) Delay Time 130 ns
a
TAFAB ADR Active to Float Delay from CLK HIGH 90 ns
TAFC READ or WRITE Float from CLK HIGH 120 ns
TAFDB DB Active to Float Delay from CLK HIGH 170 ns
Ap git ic
TAHR ADR from READ HIGH Hold Time TCY-100 ns
TAHS DB from ADSTB LOW Hold Time 30 ns
TAHW ADR from WRITE HIGH Hold Time TCY-50 ns
TAK DACK Valid from CLK LOW Delay Time (Note 1)220 170 ns
EOP HIGH from CLK HIGH Delay Time (Note 2) 170 ns
Di n
TASM
TASS
EOP LOW from CLK HIGH Delay Time
ADR Stable from CLK HIGH
DB to ADSTB LOW Setup Time 100
170
170
ns
ns
ns
TCH Clock High Time (Transitionss10 ns) 80 ns
lic l
TCL Clock LOW Time (Transitionss10 ns) 68 ns
a
TCY
TDCL
a CLK Cycle Time

CLK HIGH to READ or WRITE LOW Delay (Note 3)
200
190
ns
ns
r
TDCTR READ HIGH from CLK HIGH 190 ns
(S4) Delay Time (Note 3)
ad
TDCTW WRITE HIGH from CLK HIGH 130 ns
t
(S4) Delay Time (Note 3)
TDQ1 HRQ Valid from CLK HIGH Delay Time (Note 4) 120 ns
ec
TDQ2 120 ns
TEPS EOP LOW from CLK LOW Setup Time 40 ns
TEPW EOP Pulse Width 220 ns
TFAAB ADR Float to Active Delay from CLK HIGH 170 ns
TFAC READ or WRITE Active from CLK HIGH 150 ns
TFADB DB Float to Active Delay from CLK HIGH 200 ns
THS HLDA Valid to CLK HIGH Setup Time 75 ns
El
TIDH Input Data from MEMR HIGH Hold Time 0 ns

TIDS Input Data to MEMR HIGH Setup Time 170 ns
TODH Output Data from MEMW HIGH Hold Time 10 ns
TODV Output Data Valid to MEMW HIGH 125 ns
TQS DREQ to CLK LOW (SI, S4) Setup Time (Note 1) 0 ns
TRH CLK to READY LOW Hold Time 20 ns
TRS READY to CLK LOW Setup Time 60 ns
TSTL ADSTB HIGH from CLK HIGH Delay Time 130 ns
TSTT ADSTB LOW from CLK HIGH Delay Time 90 ns
13
8237A
A.C. CHARACTERISTICSPERIPHERAL (SLAVE) MODE

TA e 0 C to 70 C, TCASE e 0 C to 75 C, VCC e a 5V g 5%, GND e 0V
8237A-5
Min Max
TAR ADR Valid or CS LOW to READ LOW 50 ns
a
TAW ADR Valid to WRITE HIGH Setup Time 130 ns
TCW CS LOW to WRITE HIGH Setup Time 130 ns
TDW Data Valid to WRITE HIGH Setup Time 130 ns
Ap git ic
TRA ADR or CS Hold from READ HIGH 0 ns
TRDE Data Access from READ LOW (Note 5) 140 ns
TRDF DB Float Delay from READ HIGH 0 70 ns
TRSTD
Di n Power Supply HIGH to RESET LOW Setup Time 500 ns
TRSTS RESET to First IOWR 2TCY ns
TRSTW RESET Pulse Width 300 ns
TRW READ Width 200 ns
lic l
TWA ADR from WRITE HIGH Hold Time 20 ns
a
TWC CS HIGH from WRITE HIGH Hold Time 20 ns
a
TWD
TWWS
Data from WRITE HIGH Hold Time
Write Width
30
160
ns
ns
r
TWR End of Write to End of Read in DMA Transfer 0 ns
ad
t
NOTES:
1. DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high mode.
2. EOP is an open collector output. This parameter assumes the presence of a 2.2K pullup to VCC.
ec
3. The net IOW or MEMW Pulse width for normal write will be TCYb100 ns and for extended write will be 2TCYb100 ns.
The net IOR or MEMR pulse width for normal read will be 2TCY b50 ns and for compressed read will be TCY b50 ns.
4. TDQ is specified for two different output HIGH levels. TDQ1 is measured at 2.0V. TDQ2 is measured at 3.3V. The value
for TDQ2 assumes an external 3.3 KX pull-up resistor connected from HRQ to VCC.
5. Output Loading on the Data Bus is 1 TTL Gate plus 100 pF capacitance.
A.C. TESTING INPUT/OUTPUT WAVEFORM

El
231466 12
A.C. Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V
for a Logic 0. Timing measurements are made at 2.0V for a
Logic 1 and 0.8V for a Logic 0. Input timing parameters as-
sume transition times of 20 ns or less. Waveform measurement
points for both input and output signals are 2.0V for HIGH and
0.8V for LOW, unless otherwise noted.
14
8237A
WAVEFORMS
SLAVE MODE WRITE TIMING
a
Ap git ic
Di n 231466 13
NOTE:
lic l
1. Successive read and/or write operations by the external processor to program or examine the controller must be
timed to allow at least 400 ns for the 8237A-5 as recovery time between active read or write pulses. The same recovery
a
a
time is needed between an active read or write pulse followed by a DMA transfer.
Figure 9. Slave Mode Write

r
ad
SLAVE MODE READ TIMING
t
ec
El
231466 14
NOTE:
1. Successive read and/or write operations by the external processor to program or examine the controller must be
timed to allow at least 400 ns for the 8237A-5 as recovery time between active read or write pulses. The same recovery
time is needed between an active read or write pulse followed by a DMA transfer.
Figure 10. Slave Mode Read
15
8237A
DMA TRANSFER TIMING
a
Ap git ic
Di n
lic l
a
a
r
ad
t
ec
El
231466 15
NOTE:
1. DREQ should be held active until DACK is returned.
Figure 11. DMA Transfer
16
8237A
MEMORY-TO-MEMORY TRANSFER TIMING
a
Ap git ic
Di n
lic l
a
a
r
ad
t
231466 16
Figure 12. Memory-to-Memory Transfer

ec
READY TIMING
El
231466 17
Figure 13. Ready
17
8237A
COMPRESSED TRANSFER TIMING
a
Ap git ic
Di n
lic l
a
a
r
ad
t
231466 18
ec
Figure 14. Compressed Transfer
RESET TIMING
El
231466 19
Figure 15. Reset
18
8237A
DESIGN CONSIDERATIONS DATA SHEET REVISION REVIEW

1. Cascading from channel zero. When using mul- The following list represents key differences be-
tiple 8237s, always start cascading with channel tween this and the -003 data sheet. Please review
zero. Channel zero of the 8237 will operate incor- this summary carefully.
rectly if one or more of channels 1, 2, or 3 are 1. Item 6 was added to the Design Considerations
used in the cascade mode while channel zero is section.
used in a mode other than cascade.
a
2. Do not treat the DREQ signal as an asynchro-
nous input while the channel is in the de- REVISION SUMMARY
mand or cascade modes. If DREQ becomes
inactive at any time during state S4, an illegal The following list represents the key differences be-
tween rev. 004 and rev. 005 of the 1994 8237A Data
Ap git ic
state may occur causing the 8237 to operate im-
properly. Sheet.
3. HRQ must remain active until HLDA becomes
1. References to and specifications for the 8237A
active. If HRQ goes inactive before HLDA is re-
and 8237A-4 are removed. Only the 8237A-5 5 MHz
ceived the 8237 can enter an illegal state causing
device remains in production.
it to operate improperly.
Di n
4. Make sure the MEMR line has 50 pF loading
capacitance on it. When doing memory to mem-
ory transfers, the 8237 requires at least 50 pF
loading capacitance on the MEMR signal for
proper operation. In most cases board capaci-
lic l
tance is sufficient.
a
a
5. Treat the READY input as a synchronous in-
put. If a transition occurs during the setup/hold
window, erratic operation may result.
r
6. Any channel in cascade mode should have an
active DREQ before a HRQ.
ad
t
ec
El
19

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Electrnica

Pedro J. Sotorro Ruiz

Electrnica Digital Aplicada

Captulo 2.- Conceptos y Elementos bsicos

Captulo 7.- Dispositivos Perifricos

Captulo 1.- Presentacin

Captulo 1.- Presentacin

1.2.- Sobre la Electrnica Digital

Por otro lado, la Electrnica Digital se fundamenta en tres apartados: Electricidad,

En ningn caso, podemos olvidar que:

tendremos que utilizar conceptos de electricidad ya que los esquemas son

lic l comportamiento de los dispositivos no es tan ideal como asumimos.

Los Sistemas Electrnicos Digitales son siempre complejos. Se basan en

En el caso que nos atae, Electrnica Digital, la forma de construir es idntica;

3.3V, 5V y 10V. Dentro de cada valor de tensin encontramos diferentes dispositivos

excepciones) que la definen como sigue:

AVC - Advanced Very-Low-Voltage CMOS Logic FCT - Fast CMOS Technology

10V CD4000 - CMOS

Figura 1.1. Familias de circuitos digitales.

1. Fundamentos de Sistemas Digitales, Thomas L. Floyd, Edicin 7, Prentice

Hall. ISBN: 84-205-2994-X.

699-4314-6. Reimpresin 2013 Copicentro.

Captulo 2.- Conceptos y Elementos bsicos

Tema 2.- Conceptos y Elementos bsicos

a utilizar. Al igual que en otras especialidades, en ED existe un argot propio que es

introduccin a la nomenclatura que utilizamos en este documento y que se

0 a 9. El nmero 10 es una combinacin de dos smbolos numricos y no forma

2.1.2.- Niveles digitales

Nivel bajo (L) o 0" digital: Concretamente, hablando de un sistema que

Nivel alto (H) o 1" digital: De forma similar a lo dicho en el prrafo

Ap git ic Tercer nivel digital: Se denomina as al estado de desconexin de la

lic l un dispositivo desconectado no aporta informacin binaria (0" o 1"). Sin

2.1.3.- Representacin grfica de los niveles digitales

La representacin grfica de las distintas combinaciones funcionales posibles de

figura 2.2a) se ha representado un bus tpico de direcciones compuesto de 16 seales

Figura 2.2. Cronograma de buses homogneos. a) bus sin desconexin, b)

se encuentre a nivel H o a nivel L. Esto es importante para asegurar los niveles

las etapas de salida disponen de este tipo de salida.

Figura 2.3. Esquema

En la figura 2.3 se puede ver el esquema elctrico de esta etapa. La seal

Salida en colector abierto: Es tipo de salida es el mostrado en la figura 2.4. En

pero no es la ms frecuente en ED.

Figura 2.4. Esquema elctrico

Figura 2.5. Esquema elctrico de la

etapa de salida Totem-Pole con

2.2.- Componentes bsicos

Inversor: En electrnica digital, un inversor es un dispositivo cuyo valor elctrico

Ver la referencia 74LS04.

AND: El funcionamiento de una funcin AND de dos entradas (A y B) se describe

Como puede verse, es la funcin inversa de la funcin AND. Su circuito se

OR: La funcin OR de dos entradas se define por medio de la tabla de verdad

La figura 2.11 muestra el smbolo que la representa y un cronograma de

0 0 1 Figura 2.13. Tabla de verdad,

La figura 2.13 contiene el smbolo y un cronograma funcional de una puerta

XOR: Esta funcin lgica se define por medio de su tabla de verdad y el

El esquema lgico de esta funcin es el representado en la figura 2.15 junto

Figura 2.15. Esquema lgico y

salida triestado. Si vemos en la referencia 74LS244, veremos que el fabricante lo

invertida respecto a la entrada. Ver la referencia 74LS244.

Amplificador binario bidireccional: Se trata de un dispositivo amplificados como

lic l del dispositivo 74LS245.

2.4.- Referencias del captulo 2

D Package Options Include Plastic D Also Available as Dual 2-Input