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Power Quality Problems Study On IEEE 14 Bus

System And Their Mitigation Using UPQC With


Different Control Schemes
(Methodology for deciding the most sensitive load and voltage sag mitigation)

Vikas Singh Nita.R.Patne


M.Tech(Integrated Power System) Assistant Professor (Electrical Engineering Dept.)
VNIT VNIT
Nagpur , INDIA Nagpur , INDIA
vikas.singh.303@gmail.com nitapatne@yahoo.com

Abstract-In little more than ten years, electricity power quality device that can compensate almost all power quality
has grown from obscurity to a major issue. Power quality is problems such as voltage harmonics, voltage unbalance,
among the main things that is emphasized and is taken into voltage flickers, voltage sags & swells, current harmonics,
consideration by utilities in order to meet the demands of their current unbalance, reactive current, etc. The Unified Power
customer. At each passing day this issue has becoming more Quality Conditioner (UPQC) has evolved to be one of the
serious and at the same time the users demand on power most comprehensive custom power solutions for power
quality also gets more critical.Thus it is essential to establish a quality issues relating to non-linear harmonic producing
power quality monitoring system to detect power quality
loads and the effect of utility voltage disturbance on
disturbance. Several research studies regarding the power
quality have been done before and their aims frequently sensitive industrial loads. To investigate the performance of
concentrated on the collection of raw data for a further the proposed control schemes for the UPQC, simulations are
analysis, so the impacts of various disturbances can be carried out and validated with experimental results
investigated. This thesis deals with the implementation of fact
device UPQC on IEEE 14 BUS system. Different control II. SYSTEM CONFIGURATION[6]
schemes have been suggested for UPQC. Also a methodology is
shown for determining the most sensitive bus and the most The system configuration for UPQC is shown in the
sensitive load. UPQC is installed between the sensitive bus and Fig.1.The voltage at PCC may be or may not be distorted
the load with three different control schemes and results are
depending on the other non-linear loads connected at PCC.
shown for different types of fault at different-different
locations. Also a comparison is shown between all the control Also, these loads may impose the voltage sag or swell
schemes. condition during their switching ON and/or OFF operation.
Keywords: UPQC, Voltage Sag,Voltage Swell, Power The UPQC is installed in order to protect a sensitive load
Quality. Hysteresis control,Unit vector template generation from all disturbances. The UPQC consists of two voltage
technique,PWM technique source inverters connected back to back, sharing a common
dc link. Each inverter is realized by using six IGBT
I. INTRODUCTION switches. One inverter is connected parallel with the load,
acts as shunt APF, helps in compensating load harmonic
current,
DUE to the extensive use of power electronic based
equipments/loads almost in all areas, the point of
common coupling (PCC) could be highly distorted [1]-[3].
The switching ON/OFF of high rated load connected to
PCC may result into voltage sags or swells on the PCC.
There are several sensitive loads, such as computer or
microprocessor based AC/DC drive controller, with good
voltage profile requirement; can function improperly or
sometime can lose valuable data or in certain cases get
damaged due to these voltage sag and swell conditions.
One of the effective approaches is to use a unified power
quality conditioner (UPQC) at PCC to protect the sensitive
loads. A UPQC is a combination of shunt and series APFs, Figure.1 Block Diagram of UPQC
sharing a common dc link [1-3], [6-10]. It is a versatile

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reactive current and maintain the dc link voltage at constant characteristics and are constant for a particular type of load.
level. The second inverter is connected in series with the The complex power absorbed by the series APF can be
line using series transformers, acts as a controlled voltage expressed as,
source maintaining the load voltage sinusoidal and at S Sr =VSr .iS * (10)
desired constant voltage level. PSr =VSr .iS . coss =-k .VL .iS .coss (11)
QSr=VSr .iS .sinS (12)
III. STEADY- STATE POWER FLOW ANALYSIS[6] S = 0 , since UPQC is maintaining unity power factor
PSr = VSr .iS=k .VL .iS (13)
The UPQC is controlled in such a way that the voltage at QSr 0 (14)
load bus is always sinusoidal and at desired magnitude.In The complex power absorbed by the shunt APF can be
the following analysis the load voltage is assumed to be in expressed as,
phase with terminal voltage even during voltage sag and S Sh =VL .iSh * (15)
swell condition.In this particular condition, the series APF The current provided by the shunt APF, is the difference
could not handle reactive power and the load reactive power between the input source current and the load current, which
is supplied by shunt APF alone[5]. includes the load harmonics current and the reactive current.
Therefore, we can write;
i Sh = iS iL (16)
iSh = iS 00 iL L (17)
i Sh =iS ( iL .cosL j iL .sinL ) (18)
i Sh =(iS iL .cosL ) + j iL .sinL (19)
PSh =VL .iSh .cossh =VL .(iS iL .cosL) (20)
QSh = VL .iSh .sinsh V L .iL .sinL (21)
When a sag is detected such that |Vs2| <|Vs1| (rated), then
for UPQC-Q , Vinj is calculated from as.[21]
Vinj2 = (Vs12 Vs22)
Now from PWM method 2Vinj = MI (Vdc/2), where MI is
the desired modulation index (MI). Therefore,
Figure. 2 Equivalent Circuit of a UPQC
MI = (22 .Vinj)/Vdc
The source voltage, terminal voltage at PCC and load If x is the p. u. sag to be mitigated, minimum dc link voltage
voltage are denoted by Vs, Vt and VL respectively. The would be Vdc= 2 (2 )* (x(2-x)) * Vs1, for maximum
source and load currents are denoted by is and iL value of MI =1 (taking the injection transformer turns ratio
respectively. The voltage injected by series APF is denoted to be 1:1).
by VSr, whereas the current injected by shunt APF is denoted
by iSh. Taking the load voltage, VL, as a reference phasor IV. CONTROL SCHEMES FOR UPQC
and suppose the lagging power factor of the load is Cos L
then we can write;[5] The control strategy is basically the way to generate
VL=VL00 (1) reference signals for both shunt and series APF. The
effectiveness of the UPQC depends on its ability to follow
IL=IL-L (2)
the reference signals with a minimum error to compensate
Vt=VL(1+k) 00 (3)
the voltage sag and swell or any other undesirable condition.
Where factor k represents the fluctuation of source voltage,
The series APF acts as a controlled voltage source. The
defined as,
shunt APF acts as a control source for maintaining the DC
k= (4) link voltage. The shunt APF also provides required var to

The voltage injected by series APF must be equal to, the load such that the power factor at PCC is unity and only
VSr=VLVt=kVL00 (5) fundamental active power is supplied by the source. The
The UPQC is assumed to be lossless and therefore, the voltage injected by series APF can be varied from 0 o to360o
active power demanded by the load is equal to the active .The series injected voltage has to be in phase (out of phase)
power input at PCC. The UPQC provides a nearly unity with PCC voltage to compensate voltage sag swell.
power factor source current, therefore, for a given load
condition the input active power at PCC can be expressed A. Different Control Schemes for UPQC
by the following equations, Hystersis Control for Series and Shunt APF[18]
Pt=PL (6)
Vt.iS=VL.iL.cosL (7) Unit Vector Template Generation(UVTG)
VL(1+k).iS=VL.iL.cosL (8) Technique for Series and Shunt APF[16],[18]
iS =iL/(1+k)*cosL (9)
The above equation suggests that the source current i S Sinusoidal Pulse Width Modulation( SPWM)
depends on the factor k, since Land iL are load Technique for Series and Shunt APF[24][6]

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V. IEEE 14 BUS TEST SYSTEM
Table No.2
The IEEE 14 Bus Test Case represents a portion of the Bus No. IEEE Bus Voltages (kv) Simulation Results (kv)
American Electric Power System (in the Midwestern US) as 1 69 69.00
of February, 1962. A much-Xeroxed paper version of the 2 69 69.00
data was kindly provided by Iraj Dabbagchi of AEP and 3 69 69.00
entered in IEEE Common Data Format by Rich Christie at 4 69 67.18
the University of Washington in August 1993. 5 69 67.42
6 13.8 13.81
7 13.8 13.45
8 18 18.07
9 13.8 13.28
10 13.8 13.25
11 13.8 13.43
12 13.8 13.67
13 13.8 13.60
14 13.8 13.24

VI. .METHODOLOGY FOR DECIDING THE


LOCATION OF UPQC

As our test system is the IEEE 14 BUS system which has 22


lines and 14 buses. Bus 1 is Slack Bus and Buses 2,3,6,8 are
the generator buses. All the buses except bus 1 contains
loads also. So it is important to decide that which bus is the
most critical bus.
For deciding the location of UPQC a fault based technique
is suggested. The bus which is always affected by the
faults, no matter where the fault is taking place in the
Figure.5 IEEE 14 Bus System system, is called as most critical bus and the load connected
to that bus is called as the most critical load.
A. SYSTEM VARIFICATION FROM LOAD The location of UPQC is decided in two steps :
FLOW AND SIMULATION A. STEP 1 :
At first we created the 3 phase fault at the mid-
Table No.1
point of each line for a short period, as the 3
BUS Actual Bus Voltage Bus Voltages from phase fault is the most severe one.
NO Value From Load Simulation (p.u) Then we measured the voltages of all the buses
(p.u) Flow(p.u)
except the generator and slack bus.
1 1.06 1.06 1.06
Then we selected the 2 most critical lines. They are
2 1.0450 1.0448 1.0449 called critical because when we created the fault on
3 1.01 1.0097 1.0099 these lines, the effect of 3 phase fault was most
4 1.016 1.0162 0.9967 severe and they are affecting the most number of
5 1.018 1.01194 0.999 buses in the system.
6 1.0700 1.0698 1.069 After preparing the table for these results we
7 1.06 1.05947 1.0208 selected the line 7-9 and line 9-10 as the most
8 1.0901 1.08931 1.0900 critical lines.
9 1.05334 1.0524 1.0193 B. STEP 2 :
10 1.0489 1.0481 1.0243 After selecting the bus 9-10 & 7-9 as most critical
11 1.0559 1.05487 1.0438 line, we created the different types of faults at 5-5
12 1.0558 1.05422 1.0614 % distance on these line.
13 1.050 1.05494 1.05705 We plotted the graph between the distance and the
14 1.0339 1.03308 1.02889 voltage magnitude.
After analyzing all the graphs and tables, we
prepared the table for all conditions which shows
that during all types of faults which buses are
mostly affected.

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VII. ANALYSIS FROM ABOVE RESULTS

Sr.No FaultType Buses with Line 7- Line 9-10


sag 9 Most
Most Critical
Critical
1 3Phase 4,7,9,10 7,9,10 9,10
fault ,11,14
2 PhaseA 7,9,10, 7,9,10 9,10
fault 11,14
3 PhaseA-B 7,9,10 7,9,10 9,10
fault 11,14
Table. No.3
A. Conclusion from above Results
Above table shows that bus 9 and bus 10 are the
most critical buses because they are always Fig. 8.2.1 Hysteresis Control
suffering from sag created by different types of
faults at different different locations.
But we chose bus 9 as the most critical bus as
larger load is connected at that bus.

VIII. SIMULATION RESULTS WITH


DIFFERENT CONTROL SEHEMES

A. Load And Bus Voltages During Fault


Condition

Figure.8.2.2 Waveforms at Load Side with Hysteresis Controller

Figure.8.1 Source and Load side wave forms During fault condition C. SPWM Based Series And Shunt Controller

B. Hystersis Based Series And Shunt Controller

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Figure.8.3.1 SPWM based Controller

Figure.8.4.1 UVTG Technique

Figure.8.3.2 Load side waveforms with SPWM Technique Figure.8.4.2 Load Side Waveforms with UVTG Technique
E.CONCLUSION
D. Unit Vector Template Generation Technique If the sags are more frequent and for a very short
duration then it is better to use Hysteresis

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