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Microelectronic Circuits -10EC63

Prof. Dr. Noorullah Shariff C.

Single Stage IC Amplifiers (Unit-2)
S No Question and Answer Marks Mont
h-year
1 Q. What is MOSFET scaling? Compare MOSFET parameters before &
after scaling in constant field scaling & constant voltage scaling.
Mention the benefits of scaling
A.
Scaling is defined as the process of reducing the
horizontal and vertical dimensions of a MOS device by
some scaling factor S, which is greater than 1.
Thus, the scaled device is obtained by simply dividing the
key dimensions of the MOSFET such as channel length
(L), channel width (W),oxide thickness(tox), and junction
depth,by scaling factor S.
MOSFET scaling offers several benefits such as
increased component density, increase speed, reduction in
power consumption, and cost per chip.
Two type of schemes commonly used for MOSFET
scaling are constantfield scaling (full scaling) and
constant-voltage scaling (partial scaling).
In constant-field scaling, the MOSFET dimensions as
well as supply voltages are scaled by the same scaling
factor S, greater than 1. The scaling of supply and
terminal voltage maintains the same electric field as that
of original device; hence such scaling is termed
constant-field scaling.
In constant-voltage scaling, the geometrical dimensions
of the MOSFET are scaled by the scaling factor S while
the supply and terminal voltage are kept constant.

Constant-Field Scaling
Let MOSFET current before scaling be given by
Ids = (1/2) n Cox (W/L) (VGS Vt )2
After constant field scaling, the drain current
becomes,
Ids = (1/2) n SCox ((W/S)/(L/S)) ((VGS /S) (Vt /S))2
Ids = Ids /S
Hence, the drain current decreases by scaling
factor S.
Also, before scaling, delay is given by
= CV/I
Where C is the load capacitance, V is supply voltage,
and I is the charging current. We know that in constant
field scaling, C,V and I decrease by a factor of S;
hence, the delay after scaling is given by
= = /S
Constant-Voltage Scaling
After constant voltage scaling, the drain current
becomes,
Ids = (1/2) n SCox ((W/S)/(L/S)) (VGS Vt )2
Ids = S Ids
Gate capacitance CGS
CGS = Cox W L = (ox/Tox)WL
CGS = Cox (W/S) (L/S) = (ox/(Tox)/S) (W/S) (L/S) = CGS /S

2 Q. What are the benefits of short channel MOSFETS? Describe the

different short channel effects due to scaling
A.
The benefits of short channel MOSFETS are
Increased component density,
Increase speed,
Reduction in power consumption, and
Reduction in cost per chip.
However, in short-channel MOSFETs, such benefits
are obtained at the cost of increased short-channel
effects, such as the following:
1. Drain induced barrier lowering
2. Punch through effect
3. Threshold voltage roll-off
4. Gate tunneling currents
5. Hot carrier effect
Drain induced barrier lowering (DIBL) In a long-
channel MOSFET, when gate voltage is sufficiently
smaller than threshold voltage, electrons from the
source region are prevented from entering into the
channel due to the potential barrier of the source-
channel junction. However, in short-channel devices,
this barrier is lowered by the drain electric field,
which eventually allows electron flow into the
channel. This flow of electrons gives rise to the
drain current, which in turn gives rise to sub-
threshold leakage current and static leakage power.
In short-channel devices, DIBL effect is controlled
by increasing the channel doping; however, such
increased doping will degrade the carrier mobility and,
hence, the drain current.
Punch through effect We know that in short-channel
devices, channel lengths are of the order of the
source/drain depletion region thickness. When drain
voltage is increased, the drain depletion region touches
the source depletion region. This condition is known as
the punch through effect, in which gate voltage loses
the control of the channel and the drain current
increases sharply. The punch through effect is reduced
by using thin gate oxide and high channel doping.

Threshold voltage roll-off For MOSFETs, the

threshold voltage expression is derived with the
assumption that the depletion bulk charge in the
channel region is due to gate voltage. This assumption
is valid only for long-channel devices, as the
contribution of source/drain depletion charge to
channel depletion charge is negligible. However, as
channel lengths are reduced, the contribution of
source/drain depletion charge increases; hence, the
expression for threshold voltage predicts higher
threshold voltage than the actual value. Therefore, in
short-channel devices, as channel lengths are
reduced, the contribution of source/drain depletion
charge to total charge in the channel region
increases and, hence, the threshold voltage decreases as
shown in Fig. 1. The reduction in threshold voltage
eventually leads to higher sub-threshold leakage
currents, which results in increased static power
dissipation.

Fig 1
Gate tunneling currents Short-channel MOSFETs
require very thin gate oxide to control the various
short-channel effects, as mentioned earlier. For
example, MOSFETs with a channel length of 65 nm
require gate oxide thickness of about 1.2 nm. Such a
thin gate oxide consists of only four to five atomic
layers and electrons can easily tunnel through the thin
oxide. The direct tunneling of electrons across thin
gate oxide eventually leads to gate leakage current,
which also increases the power dissipation. Hence,
tunneling currents limit the further scaling of oxide
thickness. To overcome this problem, the
conventional silicon dioxide is replaced with high
dielectric constant (high-K) materials such as silicon
nitride, hafnium oxide, etc. The high-K material
allows higher physical thickness than the
conventional silicon dioxide thickness for the same
capacitance. Therefore, high-K materials decrease gate
tunneling currents and allow further scaling of MOS
transistors.
Hot carrier effect The reduction of MOSFET
dimensions to achieve higher integration density and
performance increases lateral and vertical electric
fields in the device. The increased electric field
increases the velocity of electrons and holes and,
hence, their kinetic energy. Electrons and holes with
high kinetic energy are known as hot electrons and
hot holes, respectively. Due to high vertical electric
field, hot electrons and holes strike or penetrate into
the oxide and get trapped at the Si-Si0 2 interface as
well as in the oxide. These trapped carriers modulate
the threshold voltage of MOSFETs and degrade the
reliability.
3 Q. Compare MOS & BJT
A.
4 Q. Draw the MOSFET constant current source circuit and explain it.
A.

Figure shows the circuit of a simple MOS constant-

current source. The transistor Q1s drain is shorted to
its gate, thereby forcing it to operate in the saturation
mode with
ID1 = IREF =(1/2) n Cox (W/L)1 (VGS Vt )2
where channel-length modulation is neglected. The
drain current of Q1 is supplied by VDD through resistor
R,. Since the gate currents are zero,
ID1 = IREF = (VDD VGS)/R
where the current through R is considered to be the
reference current of the current source and is denoted
by IREF. Above Equations can be used to determine the
value required for R. Now consider transistor Q2: It
has the same VGS as Q1; thus, if we assume that it
is operating in saturation, its drain current, which is
the output current lo of the current source, will be
Io = ID2 = (1/2) n Cox (W/L)2 (VGS Vt )2
where we have neglected channel-length modulation.
the above two equations enable us to relate the output
current Io to the reference current IRFF as follows:
Io /IREF = (W/L)2 /(W/L)1
Output current I0 is related to the reference current
IREF by the ratio of the aspect ratios of the transistors.
In other words, the relationship between Io and IREF
is solely determined by the geometries of the
transistors. In the special case of identical transistors, I0
= IREF, and the circuit simply replicates or mirrors
the reference current in the output terminal.

A.

Figure depicts the current mirror circuit with the input

reference current shown as being supplied by a current
source. The current gain or current transfer ratio
of the current mirror is given by
ID1 = IREF =(1/2) n Cox (W/L)1 (VGS Vt )2
Io = ID2 = (1/2) n Cox (W/L)2 (VGS Vt )2
Io /IREF = (W/L)2 /(W/L)1
Effect of V0 on I0 For the operation of the current
source of Fig, we assumed Q2 to be operating in
saturation. This is obviously essential if Q2 is to
supply a constant-current output. To ensure that Q2 is
saturated, the circuit to which the drain of Q2 is to be
connected must establish a drain voltage Vo that
satisfies the relationship
Vo =VGS- Vt or Vo = VOV
Also, channel-length modulation can have a significant
effect on the operation of the current source. Consider,
for simplicity, the case of identical devices Q1 and Q2.
The drain current of Q2, IO, will equal the current in
Q1, IREF, at the value of V0 that causes the two
devices to have the same VDS, that is, at V0 = VGS.
As V0 is increased above this value, I0 will increase
according to the incremental output resistance ro2 of
Q2. This is illustrated in Fig., which shows I0 versus
V0. Observe that since Q2 is operating at a constant
VGS (determined by passing IREF through the matched
device Q1), the curve in Fig. is simply the iD-vDS
characteristic curve of Q2 for VGS equal to the particular
value VGS.

Output resistance is given by

Ro = ( Vo/ Io) = ro2 =( VA2/Io )
Where is VA2 Early voltage
Now Io is given by
Io = (W/L)2 /(W/L)1 IREF (1 + (Vo - VGS)/ VA2)

A.

Once a constant current is generated, it can be

replicated to provide DC bias currents for the various
amplifier stages in the IC. Current mirrors can be
used to implement this current steering function.
Figure shows a simple current steering circuit. Here
Q1 together with R determine the reference current
IREF. Transistors Q1, Q2, and Q3 form a two-output
current mirror,
I2 = (W/L)2 /(W/L)1 IREF
I3 = (W/L)3 /(W/L)1 IREF
To ensure operation in the saturation region, the
voltages at the drains of Q2 and Q3 are constrained as
follows:
VD2,VD3 -VSS +VGS1-Vtn
VD2,VD3 -VSS +Vov1
where Vov1 is the overdrive voltage at which Q1, Q2,
and Q3 are operating. In other words, the drains of Q2
and Q3 will have to remain higher than - Vss by at
least the overdrive voltage, which is usually a few
tenths of a volt.
Also the current I3 is fed to the input side of a current
mirror formed by PMOS transistors Q4 and Qs. This
mirror provides
I5 = (W/L)2 /(W/L)1 I4
Where I4 = I3. To Keep Q5 in saturation, its drain voltage should
be VD5 VDD - VOV5 where V0V5 is the overdrive voltage
at which Q5 is operating.
Finally, an important point to note is that while Q2
pulls its current I2 from a load , Q5 pushes its current
I5 into a load. Thus Q5 is appropriately called a
current source, whereas Q2 should more properly be
called a current sink. In an IC, both current sources and
current sinks are usually needed.
7 Q. With neat circuit diagram, explain basic BJT current mirror & derive
an expression for current transfer ratio of BJT current mirror for finite
& for finite output resistance
A.
The basic BJT current mirror is shown in Fig. Assume Q1 and Q2
are matched and have the same VBE, then their collector currents
will be equal. Then

Since Io = IC

If approaches infinity then Io/ IREF approaches 1 or Io = IREF.

To obtain a current transfer ratio other than unity, say m,
we simply arrange that the area of the EBJ of Q2 is m
times that of Q1. In this case,

Io/ IREF = Area of EBJ of Q2/ Area of EBJ of Q1

Io/ IREF = m /(1+ (m+1)/)

8 Q. BJT current source

A.

Figure shows the BJT current source. Here the reference current s
IREF = (VCC VBE)/R
Where VBE is base emitter value corresponding to the desired value
of Io,
Io = IREF /(1+ 2/) (1 + (Vo - VBE)/ VA2)

A.

Assume high (i.e., negligible base current) & neglect

Early effect.
Q1 & Q3 form a current mirror; thus Q3 will supply a
constant current I1 = IREF.

Q3 can supply this current to any load as long as the

voltage that develops at the collector does not exceed
(Vcc-0.3V); If it exceeds, Q3 enters the saturation region.

To generate a dc current twice the value of IREF, TWO

transistors, Q5 and Q6, each of which is matched to
Q1, are connected in parallel, and the combination
forms a mirror with Q1 . Thus I3 = 2IREF. In an IC
implementation Q5 and Q6 can be replaced with a
transistor having a EBJ area two times that of Q1.

Similarly to generate a current three times IREF, t hree

transistors, Q7, Q8 and Q9 each of which is matched to
Q2, are connected in parallel, and the combination is
placed in a mirror arrangement with Q2. Again, in an
IC implementation, Q7, Q8, and Q9 shall be replaced
with a transistor having a EBJ area three times that of
Q2.
10 Q. Derive an expression for 3-db frequency fH for an amplifier
having two poles & two zeros.
A.
Consider, the case of a amplifier that has two poles and two zeros
in the high-frequency band; and so

results

H is usually smaller than the frequencies of all the

poles and zeros, we may neglect the III term in
numerator and denominator and solve for H to obtain

& fH = H /2
This relationship can be extended to any number of poles and
zeros as
Open circuit time constants
Another way of finding 3bd frequency fH is by finding the open
circuit time constants.
The amplifier gain can be represented as

where

FH(s) can be expressed in the form as shown below by (

expanding numerator & denominator)

the coefficients b and a are related to the frequencies of the poles

and zeros, respectively. The coefficient b1 can be written as

The value of b1 can be obtained by considering the various

capacitances in the high-frequency equivalent circuit one at a
time while all other capacitors are set to zero (replacing them
with open circuits)
This means, the value of b1 is obtained by adding the
individual time constants, called open-circuit time
constants.
A capacitance Ci is considered, we reduce all other
capacitances to zero, the input signal source is set to
zero, and we find the resistance Rio as seen by Ci .
This process is then repeated for all other capacitors in
the circuit. Therefore, b1 is now given by,

If the zeros are not dominant and if one of the poles, say P1, is
dominant, then we may write,

Also, the upper cut-off (3-dB) frequency can be approximated as

11 Q. Explain Millers Theorm

Consider the situation in Fig. We observe two

isolated circuit nodes, labeled 1 and 2, between
which an impedance Z is connected. Nodes 1 and 2
are also connected to other parts of the circuit, as
indicated by the dashed lines emanating from the
two nodes. Furthermore, it is assumed that the
voltage at node 2 is known and is related to that at node
1 by V2=KV1.
In typical situations K is a gain factor that can be +ve or
-ve and has a magnitude usually larger than one.

Miller's theorem states that impedance Z can

be equivalently replaced by two impedances: Z1
connected between node 1 and ground and Z2
connected between node 2 and ground, where
Z1 = Z / (1-K)
And
Z2 = Z / (1 1/K)
to obtain the equivalent circuit shown in Fig. (b).

Proof :
In the circuit of Fig.(a), from node-1 impedance Z
carries the current I. Therefore, to keep this current
unchanged in the equivalent circuit, we must choose
the value of Z1 so that it draws an equal current.

i.e., Z1= V1/I1 = Z/(1-K)

Similarly, to keep the current into node 2 unchanged,
we must choose the value of Z2 so that,
V2= K V1 = - I2 Z2 = I1 Z2 (since I2 =I1)

Thus Z2 = -K V1/ I1 = -K Z/(1-K)

i.e., Z2 = Z / (1 1/K)
The Miller equivalent circuit obtained is based on
the fact that the rest of the circuit remains
unchanged. If not, the ratio of V2 to V1 might
change.
12 Q. For the high-frequency equivalent circuit of a
common-source MOSFET amplifier. The amplifier is
fed with a signal generator Vsig having a resistance
Rsig. Resistance Rin is due to the biasing network.
Resistance R'L is the parallel equivalent of the load
resistance RL, the drain bias resistance RD, and the
FET output resistance r0. Capacitors Cgs and Cgd are
the MOSFET internal capacitances. For Rsig = 100
k, Rin = 420 k, Cgs = Cgd = 1pF, gm = 4 mA/V,
and R'L =3.33 k, find the mid-band voltage gain,
AM= V0/Vsig and the upper 3-dB frequency, fH.
A.

gs = CgsRgs = 1 x 10-12 x 80.8 x 103= 80.8 ns

The resistance Rgd as seen by Cgd is found by setting
Cgs = 0 and short-circuiting Vsig. The result is the
circuit in Fig.(d), to which we apply a test current Ix.
Writing a node equation at G gives
Ix = - (Vgs/Rin) (Vgs /Rsig) = - Vgs / R

Substituting for Vgs from Eq. (1) and

Ix = - gm Ix R [(- Ix R + Vx)/RL]

Ix RL + gm Ix R RL+ Ix R = Vx

The open-circuit time constant of Cgd is

gd = Cgd Rgd = 1 x 10-12 x 1.16 x 106 = 1160nS
The upper 3-dB frequency H can now be determined from
H = 1/ ( gs + gd ) = 806 krads/secs

13 Q. For the emitter follower biased by a constant current source I,

shown in the fig draw the high frequency eq ckt clearly naming all
the components.