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www.fairchildsemi.com
+
OSC
0.7V/0.2V -
+
+
Vref
0.35/0.55V
VCC good -
VCC Vref VBurst -
8V/12V
LEB
200ns
LPF
RC=80ns
AOCP
1
6V TSD S Q VOCP GND
VSD (1.1V)
2.5s time R Q
Sync delay
6V
Vovp
Vcc good
MOSFET.
When the diode current reaches zero, the drain-to- VoNp/Ns
VIN
source voltage (Vds) begins to oscillate by the resonance VIN -VoNp/Ns
between the primary-side inductor (Lm) and the MOSFET
output capacitor (Coss) with an amplitude of VoNp/Ns on
tON tD
the offset of VIN, as depicted in Figure 2. Quasi-resonant
switching is achieved by turning on the MOSFET when tS
Vds reaches its minimum value. Doing this reduces the
MOSFET turn-on switching loss caused by the Figure 2. Typical Waveform of Quasi-Resonant
capacitance loading between the drain and source of Flyback Converter
MOSFET. If the transformer is designed so that the
resonance amplitude is larger than VIN by increasing the
turns ratio, Np/Ns, "Zero-Voltage-Switching (ZVS)" of the
MOSFET is achieved. 3. Control Method of FSQ-Series
Other than turning on the MOSFET with minimum drain-to- To overcome the frequency increase problem at light load,
source voltage, a quasi-resonant converter provides "soft" FSQ-series employs an advanced control technique
switching conditions to the switching devices. The MOSFET illustrated in Figure 3 with typical switching waveforms.
turns on at zero current and the diode turns off at zero Once the MOSFET is turned on, the next turn-on is
current. This soft switching not only reduces the switching prohibited during the blanking time (tB). After the blanking
losses, but also lowers the switching noise caused by diode time, the controller finds the valley within the detection time
reverse recovery. window (tW) and turns on the MOSFET (Case B and C). If
The major drawback of applying a quasi-resonant converter no valley is found within tW, the MOSFET is forced to turn
topology is that it causes the switching frequency to increase on at the end of tW (Case A). Thus, the converter can operate
as the load decreases and/or input voltage increases. As the with a fixed frequency when operating in continuous
load decreases and/or input voltage increases, the MOSFET conduction mode (CCM). Meanwhile, when the converter
ON time (tON) diminishes and, therefore, the switching operates in discontinuous conduction mode (DCM), the
frequency increases. This results in severe switching losses, controller turns on the MOSFET at the valley within tW.
as well as intermittent switching and audible noise. Due to Accordingly, the switching frequency is limited between
these problems, the conventional quasi-resonant converter 55kHz and 67kHz, as shown in Figure 3 and 4. This allows
topology has limitations for applications with wide input and converter design as simple as in conventional PWM
load ranges. converters.
Vds
tB=15s tW=3s 1. Determine the system specifications
(Vlinemin, Vlinemax, fL , Po , Eff )
Ids ID Ids ID
3. Determine the reflected output voltage (V RO)
B
Vds
4. Determine the transformer primary side
inductance (L m)
tB=15s
5. Choose proper FPS considering input power and
tW=3s Idspeak
tB=15s tW=3s
Is the winding window Y
area (Aw) enough ?
tsmax=18s
N
Design finished
Vin
Figure 4. Frequency Variation as Input Voltage Varies Figure 5. Flow Chart of Design Procedure
2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ-Series Rev. 1.0.0 10/23/06 3
AN-4150 APPLICATION NOTE
DR(n) LP(n)
VO(n)
NS(n)
CO(n) CP(n)
Np
DR2 LP2
CDC VO2
AC
IN NS2 C CP2
FSQ-Series Vstr O2
Drain
DR LP1
Sync
PWM 1 VO1
GND
NS1 CP1
VFB Rcc CO1
VCC Da
CB
Ca Na
Dzc DSY
Rd Rbias
RSY1
H11A817A R1
RSY2
CSY CF
RF
KA431
RSY3 R2
[STEP-1] Define the System Specifications [STEP-2] Determine DC Link Capacitor (CDC) Value and
When designing a power supply the following specifications Calculate the DC Link Voltage Range
should be determined first: In offline SMPS applications, a crude DC voltage (VDC) is
obtained first on the DC link capacitor (CDC) by rectifying
Line voltage range (Vlinemin and Vlinemax).
the AC mains. Then, the crude DC voltage is converted into
Line frequency (fL).
pure DC outputs. Typically, the DC link capacitor is selected
Maximum output power (Po).
as 2-3F per watt of input power for universal input range
Estimated efficiency (Eff): The power conversion
(85~265Vrms) and 1F per watt of input power for European
efficiency must be estimated to calculate the maximum input
input range (195~265Vrms). With the DC link capacitor
power. If no reference data is available, set Eff = 0.7~0.75 for
selected, the minimum DC link voltage is obtained as:
low-voltage output applications and Eff = 0.8~0.85 for high-
voltage output applications. With the estimated efficiency, P in ( 1 D ch )
min min 2
the maximum input power is given by: V DC = 2 ( V line ) ------------------------------------ (EQ 3)
C DC f L
P
P in = ------o- (EQ 1)
E ff
where CDC is the DC link capacitor value; Dch is the duty
For multiple output SMPS, the load occupying factor for cycle ratio for CDC to be charged as defined in Figure 7,
each output is defined as: which is typically about 0.2; Pin, Vlinemin and fL are specified
Po ( n ) in STEP-1.
K L ( n ) = ------------
- (EQ 2)
Po
where Po(n) is the maximum output power for the n-th The maximum DC link voltage is given as:
output. For single output SMPS, KL(1)=1. It is assumed that max max
V DC = 2V line (EQ 4)
Vo1 is the reference output that is regulated by the feedback
control in normal operation, as shown in Figure 6.
where Vlinemax is specified in STEP-1.
MOSFET, too small Dmax should be avoided. Once Dmax 1, 3, 6, and 7, respectively, and fs is the FPS free-running
is determined, the primary-side inductance (Lm) of the switching frequency.
transformer is obtained as:
2
[STEP-5] Choose the Proper FPS Considering Input
min
( V DC D max ) Power and Peak Drain Current
Lm = ---------------------------------------------
- (EQ 9)
2P in f s With the resulting maximum peak drain current of the
MOSFET (Idspeak) from Equation 10, choose the proper FPS
where VDCmin is specified in Equation 3, Pin is specified in for which the pulse-by-pulse current limit level (ILIM) is
STEP-1, and fs is the free-running switching frequency of higher than Idspeak. Since FPS has 12% tolerance of ILIM,
the FPS device. there should be some margin in choosing the FPS device.
[STEP-6] Determine the Proper Core and the Minimum
primary Turn
Lm
Im VRO The initial selection of the core is bound to be crude since
there are too many variables. One way to select the proper
VDCmin
core is to refer to the manufacture's core selection guide. If
ID
Ids
there is no reference, use Table 1 as a starting point. The core
I recommended in Table 1 is typical for the universal input
K RF =
2IEDC range, 55kHz switching frequency, and single-output appli-
cation. When the input voltage range is 195-265 VAC or the
KRF < 1 switching frequency is higher than 55kHz, a smaller core can
I IEDC Idspeak
be used. For an application with multiple outputs, a larger
core than recommended in the table should usually be used.
Ids ID
Im
With the chosen core, calculate the minimum number of
turns for the transformer primary side to avoid the core satu-
VRO ration with the following:
Dmax =
VRO + VDC min min L m I LIM 6
NP = ------------------ 10 (turns) (EQ 14)
B sat A e
K RF = 1
Idspeak
I where Lm is specified in Equation 7, ILIM is the FPS pulse-
by-pulse current limit level, Ae is the cross-sectional area of
IEDC
the core in mm2, as shown in Figure 10, and Bsat is the satu-
Ids ID ration flux density in tesla. Figure 11 shows the typical char-
Im acteristics of ferrite core from TDK (PC40). Since the
saturation flux density (Bsat) decreases as the temperature
VRO
Dmax goes high, the high temperature characteristics should be
VRO +VDC min considered. 12% tolerance of ILIM should be considered.
I ds
peak I
= I EDC + -----
2 (EQ 10)
Aw
I 2 D max
-----
rms 2
I ds = 3 ( I EDC ) + -------------- (EQ 11)
2 3
P in
I EDC = -------------------------------------
- (EQ 12)
min
V DC D max
min
DC V D
max Ae
I = ----------------------------------- (EQ 13)
Lm fs
Figure 10. Window Area and Cross-Sectional Area
where Pin, VDCmin, Dmax, and Lm are specified in Equations
2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ-Series Rev. 1.0.0 10/23/06 6
AN-4150 APPLICATION NOTE
100 C
400
120 C
The number of turns for Vcc winding is determined as:
Flux density B (mT)
300
V cc * + V Fa
200 - N s1
N a = --------------------------- ( turns ) (EQ 17)
V o1 + V F1
100
where Vcc* is the nominal value of the supply voltage of the
FPS device and VFa is the forward voltage drop of Da as
0 defined in Figure 12. It is typical to set Vcc* 3~4V below Vcc
0 800 1600
Magnetic field H (A/m) maximum rating (refer to the datasheet).
- DR(n)
Output EI Core EE Core EPC Core EER Core +
Power VRO Np VO(n)
NS(n)
0-10W EI12.5 EE8 EPC10
EI16 EE10 EPC13 + -
EI19 EE13 EPC17
EE16
10-20W EI22 EE19 EPC19
- VFa + + VF1 -
20-30W EE22 EPC25 EER25.5
EI25
Da DR1 +
30-50W EI28 EE25 EPC30 EER28
+ VO1
EI30
Vcc*
50-70W EI35 EE30 EER28L Na NS1
-
-
Table 1. Core Quick selection Table (for Universal Input
Range, fs=55kHz and Single Output)
NP V RO 2
NP 1
n = --------- = -------------------------
- (EQ 15) G = 0.4 A e ----------------
- ------ ( mm ) (EQ 18)
N s1 V o1 + V F1 10 L m A L
9
where Np and Ns1 are the number of turns for primary side where AL is the AL-value with no gap in nH/turns2; Ae is the
and reference output, respectively, Vo1 is the output voltage cross-sectional area of the core in mm2, as shown in Figure
and VF1 is the diode (DR1) forward voltage drop of the refer- 10; Lm is specified in Equation 7; and Np is the number of
ence output. turns for the primary-side of the transformer.
Then, determine the proper integer for Ns1 so that the
2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ-Series Rev. 1.0.0 10/23/06 7
AN-4150 APPLICATION NOTE
[STEP-8] Determine the Wire Diameter for Each Winding where KL(n), VDCmax, VRO, and Idsrms are specified in
Based on the rms Current of Each Output
Equations 2, 4, STEP-3 and Equation 11, respectively; Dmax
The rms current of the n-th secondary winding is obtained as:
is specified in Equation 6; Vo(n) is the output voltage of the n-
th output; and VF(n) is the diode (DR(n)) forward voltage. The
rms rms 1 D max V RO K L ( n ) typical voltage and current margins for the rectifier diode are:
I sec ( n ) = I ds ----------------------- -------------------------------------- (EQ 19)
D max ( V o ( n ) + VF ( n ) )
peak
I
o ( n ) max D I V R K
RO C ( n ) L ( n )
A wr = A c K F (EQ 20) V o ( n ) = ------------------------ ds
- + ----------------------------------------------------------
- (EQ 26)
Co ( n ) fs ( Vo ( n ) + VF ( n ) )
Idspeak
Figure 13. Circuit Diagram of the Snubber Network
Ids2peak
where fs is the FPS free-running switching frequency. In where VDCmax is specified in Equation 4.
general, 5~10% ripple of the selected capacitor voltage is
2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ-Series Rev. 1.0.0 10/23/06 9
AN-4150 APPLICATION NOTE
Sync VCC Na
VDC max
Figure. 16 Synchronization Circuit
0V
TR LmCeo
=
4 2
[STEP-12] Design the Synchronization Network
TR L m C eo Gate
------
- = ---------------------------------
- (EQ 32)
4 2
where Na and Ns1 are the numbers of the turns for Vcc wind-
ing and Vo1, respectively, and VF1 is the forward voltage drop v o1
of D1. G vc = --------
- (EQ 36)
v FB
Choose the voltage divider RSY1, RSY2, and RSY3 so that the
peak value of sync voltage (Vsyncpk) is lower than the OVP K R L V DC ( N p N s1 ) ( 1 + s w z ) ( 1 s w rz )
= ----------------------------------------------------- ----------------------------------------------------------
threshold voltage (6V) to avoid triggering OVP in normal 2V RO + v DC 1 + s wp
operation. It is typical to set Vsyncpk to be 4~5V.
where VDC is the DC input voltage; RL is the effective total
load resistance of the controlled output, defined as Vo12/Po;
[STEP-13] Design the Feedback Loop Np and Ns1 are specified in STEP-7; VRO is specified in
Since FSQ-series employs current-mode control, the STEP-3; Vo1 is the reference output voltage; Po is specified
feedback loop can be simply implemented with a one-pole in STEP-1; and K is specified in Equation 35. The pole and
and one-zero compensation circuit, as shown in Figure 18. In zeros of Equation 36 are defined as:
the feedback circuit analysis, it is assumed that the current
transfer ratio (CTR) of the opto-coupler is 100%. 2
1 RL ( 1 D ) (1 + D)
w z = -------------------- , w rz = ----------------------------------------
- and w p = -------------------
The current control factor of FPS, K is defined as: R c1 C o1 DL m ( N s1 N p )
2 R L C o1
(EQ 37)
I pk I LIM
K = ---------
- = ----------------- (EQ 35) where Lm is specified in Equation 7, D is the duty cycle of
V FB V FBsat the FPS, Co1 is the reference output capacitor, and RC1 is the
ESR of Co1.
where Ipk is the peak drain current and VFB is the feedback
voltage, respectively, for a given operating condition; ILIM is When the converter has more than one output, the low
the current limit of the FPS; and VFBsat is the feedback frequency control-to-output transfer function is proportional
saturation voltage, which is typically 2.5V. to the parallel combination of all load resistance, adjusted by
the square of the turns ratio. Therefore, the effective load
To express the small signal AC transfer functions, the small resistance is used in Equation 36 instead of the actual load
signal variations of feedback voltage (vFB) and controlled resistance of Vo1.
output voltage (vo1) are introduced as v FB and v o1 .
Notice that there is a right half plane (RHP) zero (wrz) in the
control-to-output transfer function of Equation 36. Because
FPS vo1' vo1 the RHP zero reduces the phase by 90, the crossover
frequency should be placed below the RHP zero.
vFB RD
ibias Figure 19 shows the variation of a CCM flyback converter
Rbias
control-to-output transfer function for different input
iD
CB
voltages. This figure shows the system poles and zeros,
RB
1:1 together with the DC gain change, for different input
CF RF R1 voltages. The gain is highest at the high input voltage
condition and the RHP zero is lowest at the low input voltage
KA431
condition.
v FB w i 1 + s w zc
- = - ----
-------- - --------------------------- (EQ 39)
v o1 s 1 + 1 w pc
RB 1 1
where w i = ----------------------
- ;w =--------------------------------- ; w pc =--------------- ;
R 1 R D C F zc ( R F + R 1 )C F RB CB Figure 21. DCM Flyback Converter Control-to-Output
TransferFunction Variation for Different Loads
RB is the internal feedback bias resistor of FPS, which is
typically 2.8k; and R1, RD, RF, CF and CB are shown in
When the input voltage and the load current vary over a wide
Figure 18.
range, it is not easy to determine the worst case for the
feedback-loop design. The gain, together with zeros and
poles, varies according to the operating condition. Even
though the converter is designed to operate in CCM or at the
boundary of DCM and CCM in the minimum input voltage
and full-load condition, the converter enters into DCM,
changing the system transfer functions as the load current
decreases and/or input voltage increases.
One simple and practical solution to this problem is
designing the feedback loop for low input voltage and full-
load condition with enough phase and gain margin. When
the converter operates in CCM, the RHP zero is lowest in
low input voltage and full-load condition. The gain increases
about 6dB as the operating condition is changed from the
lowest input voltage to the highest input voltage condition
under universal input condition. When the operating mode
Figure 19. CCM Flyback Converter Control-to-Output
Transfer Function Variation for Different Input Voltages changes from CCM to DCM, the RHP zero disappears,
making the system stable. Therefore, by designing the
feedback loop with more than 45 of phase margin in low
input voltage and full load condition, the stability over the
operating ranges can be guaranteed.
frequency is too close to the corner frequency, the The resistors Rbias and RD, used together with opto-cou-
controller should be designed to have a phase margin pler H11A817A and shunt regulator KA431, should be
greater than 90 when ignoring the effect of the post filter. designed to provide proper operating current for the
KA431 and to guarantee the full swing of the feedback
Determine the DC gain of the compensator (wi/wzc) to
voltage for the FPS device chosen. In general, the mini-
cancel the control-to-output gain at fc.
mum cathode voltage and current for the KA431 are 2.5V
Place a compensator zero (fzc) around fc/3. and 1mA, respectively. Therefore, Rbias and RD should be
designed to satisfy the following conditions:
Place a compensator pole (fpc) above 3fc.
V o1 V OP 2.5
----------------------------------------
- > I FB (EQ 42)
40 dB
Loop gain T RD
V OP
-------------
- > 1mA (EQ 43)
20 dB fzc R bias
Compensator
fp fpc
where Vo1 is the reference output voltage; VOP is opto-
0 dB
fc diode forward voltage drop, which is typically 1V; and IFB
Control to output
is the feedback current of FPS, which is typically 1mA.
frz
-20 dB For example, Rbias < 1k and RD < 1.5k for Vo1=5V.
fz
-40 dB
Determining the feedback circuit component includes some Vcc resistor (Ra): The typical value for Ra is 5-20. In
restrictions, such as: the case of multiple outputs flyback converter, the voltage
of the lightly loaded output, such as Vcc, varies as the load
The voltage divider network of R1 and R2 should be currents of other outputs change due to the imperfect
designed to provide 2.5V to the reference pin of the coupling of the transformer. Ra reduces the sensitivity of
KA431. The relationship between R1 and R2 is given as: Vcc to other outputs and improves the regulations of Vcc.
2.5 R 1
R 2 = ------------------------ (EQ 40)
V o1 2.5
Design Example
1. Schematic
C209
47pF
T101
L201
EER2828
16V, 0.3A
RT101 11
1 D201 C201 C202
5D-9 UF4003 470F
470F
R105 C104 C210 35V 35V
R102 2
100k 56k 10nF 47pF
1kV L202
C103 D101
R108 1N 4007 12V, 0.4A
33F
62 3
400V 10 D202 C203 C204
2 UF4003 470F 470F
IC101 35V 35V
FSQ0365RN 12
BD101 5 8
1 3 Vstr Drain
Bridge 7
Drain L203
Diode 4 6
Drain C106 C107
Sync 6 5.1V, 1A
100nF 22uF R103
SMD 50V 5
4
3
Vfb Vcc 2 D203
C205 C206
GND 4 1000F 1000F
C102 C105 D102 SB360
1 10V 10V
100nF,400V 47nF 1N 4004 R104
50V 12k 5 L204
9
ZD101 3.4V, 1A
1N4746A D204 C207 C208
C110
6.2k 6.2k
1000F
R106 R107
10V 10V
50V
D103
LF101
40mH
8
C302
3.3nF R201
C101 510
100nF R203
400V 6.2k
R202
R204 C209
1k
20k 100nF
IC202
TNR
FOD817A
F101
FUSE IC201 R205
KA431 6k
AC IN
2. Transformer Specifications
Electrical Characteristics
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
1.Life support devices or systems are devices or systems which, (a) 2.A critical component is any component of a life support
are intended for surgical implant into the body, or (b) support or sus- device or system whose failure to perform can be
tain life, or (c) whose failure to perform when properly used in accor- reasonably expected to cause the failure of the life support device or
dance with instructions for use provided in the labeling, can be system, or to affect its safety or effectiveness.
reasonably expected to result in significant injury to the user.