Introduction to Mixer

The basic configuration of a single mixer is that it has two inputs and
one output. It multiplies or mixes the carrier signal, either RF or
intermediate frequency (IF) depending on an up conversion or down
conversion mixer, with another input from the local oscillator (LO).
The LO signal input terminal is used to assist in the heterodyning
process, produces the difference and sum frequencies of the two
input terminals of interest. After, the output frequencies come out of
the output terminal. This subject is built upon and expanded in more
depth in the paragraphs below.
In an ideal nonlinear mixer the heterodyning process will become
clearer in the following equations, which were obtained and
summarized from [1].
If both input signals show:

a = A cos w1t
(2.1)
and
b = B cos w2t
(2.2)

The mixer output signal after mixing yields,

(2.3)

This shows that the mixers output consists of the difference and
summation of both input frequencies. A mixer can cater to either
output function where the unwanted function can be filtered out.
The chosen function, which can be either the differences or
summation of the input frequencies, receives the term down
conversion mixer or up conversion mixer respectively.
In a typical mixer design there are four primary defined
specifications that are shown and explained below: Conversion Gain
(CG), Linearity, Noise Figure (NF), and Port isolations. The CG is a
ratio between the output signal and the input signal usually in the
measure in decibels (dB) or, milli-decibels (dBm). The linearity of the
mixer is defined as how well the mixer reacts to the mixing of
frequencies and ideal law of superposition in the ideal case
explained in above text. NF is a ratio of the signal-tonoise ratio
(SNR) at the IF output and the SNR at the RF input port. Finally, the
port isolation parameter shows how much leakage of signal occurs
between two ports.

The Gilbert Cell

The Gilbert cell mixer is shown in the Fig. It commutates the RF
signals in current instead of in voltage. The transistor M3 acts as a
transconductor and converts the input RF voltage into a current that
is passed to the transistors M1 and M2. Then the differential pair of
transistors M1 and M2 commutate the current to the complementary
IF outputs for each LO period. As a large swing is not needed
between the gates of the differential pair to commutate the current,
the requirement of the LO drive gets largely reduced.
There is no direct path from LO to RF and hence better isolation
between LO and RF is provided. However, there is still LO leakage
into the IF port through the parasitic capacitance present between
the gate and drain of the differential pair transistors. This problem
can be solved by using a double balanced Gilbert cell mixer which
couples differential LO signals into the same IF output.
A double balanced Gilbert cell mixer is shown in the Fig . The
transistors M3 and M6 form the differential pair transconductance
that converts the RF input voltage into a current. This current is then
commutated by the switching action of the transistors M1 M2 and
M4 M5. It can be seen from the Fig 3.13 that each side of the IF
output is connected with two transistors with 180o phased LO
signals so that the LO leakage from the two transistors cancels each
other. That is, the LO feedthrough from the transistor M1 will be
canceled by that from M5, and any feedthrough from M4 will be
canceled by that from M2.Therefore, we will observe only the mixed
products of RF and LO at the IF outputs [YongWang].
 Mixer Analysis and design
The double balanced Gilbert cell mixer used in the design of the
transmitter is shown in the Fig . Several design issues must be taken
under consideration when designing the Gilbert cell as an up-
conversion mixer. The main problem associated with an up-
conversion Gilbert cell mixer is the mixer being loaded with PMOS
active loads. As the PMOS devices have a lower unity current gain
frequency compared to NMOS devices, the PMOS load devices will
limit the maximum operating frequency of the mixer [J P Sullivan].
The PMOS active loads can be replaced with resistors R1 and R2 as
shown in the Fig. This adds gain without the frequency limiting
effects of the PMOS devices.
The transistors M7 and M8 form the RF input differential pair. The RF
signal is applied to these transistors which perform the voltage to
current conversion. For proper operation of the circuit signals
considerably less than the 1dB compression point are used. The
transistors M7 and M8 are biased to operate in subthreshold region.
The drain current in the subthreshold region is dominated by the
diffusion mechanism and so it has an exponential dependence on
the gate voltage resulting in a higher gm to IDS ratio. Since this is a
low power design it is appropriate to have the transistors operating
in subthreshold region as such circuits have a reduced DC power
dissipation.
The digital data is applied to transistors M2-M5 which act as
switches. The local+ input of the mixer i.e., the transistors M2 and
M5, is tied to VDD. The digital data is applied to local-input of the
mixer i.e., to the transistors M3 and M4. These transistors form the
multiplication function, multiplying the RF signal current from the
transistors M7 and M8 with the digital data LO signal applied across
the transistors M2-M5 which provide the switching function.
The load resistors R1 and R2 form the current to voltage
transformation providing the differential output IF signals.
where Gc is the mixer voltage gain, gm is the transconductance of
the differential pair M7 and M8, and RL is the effective load
resistance. The above equation can be considered to be a good
approximation when the square wave local oscillator voltage driving
the transistors M2-M5 is large compared to the (Vgs-Vt) of the
switching transistors M2-M5. The above equation is the product of
the differential voltage gain of the input RF transistors M7-M8 and
the frequency translated first harmonic of the modulating square
wave.
The RF buffer circuit consisting of transistors M1 and M9 and M6 and
M11 is a simple differential source follower amplifier. The reason for
using a common source amplifier configuration is its simplicity in
implementation, and the circuit also provides a wide band match to
the balun transformer.
The primary design technique to combat any offsets associated with
the differential pairs in the mixer is to use the common centroid
geometry for layout of devices in order to minimize the device
mismatch due to process variations. Thus to offset any process
variations, the transistors M7, M8, M2, M3 and M4, M5 are laid out
using a common centroid layout technique.
When it comes to the mixer definitions, the DB Gilbert cell mixer is
better in most areas compared to the SB mixer design. The CG is
better in DB because it has the capacity to maintain a higher
transconductance. As for linearity, in the DB Gilbert cell the ports
suppress the input frequencies better than the SB mixer allowing
better control over harmonic products. In the area of port isolation
the DB architecture is higher due to the transistor stacking and
schematic setup. This provides better isolation between the input
and output ports. The cost of gaining these improvements comes
with the cost of higher NF and power consumption. The NF is
typically higher in the DB design, because there are more
transistors. Also the design has a higher probability of noise being
created by non ideal switching transistors. Another sacrifice is a
higher power consumption that occurs from an increased supply
voltage. This voltage raise is needed to properly operate the
multiple transistors that are needed to build the larger DB design.
Circuit Diagram
Component Specifications:
VDD = 15V
M1 w=29.15u l=200n
M2 w=40u l=200n
M3 w=40u l=200n
M4 w=40u l=200n
M5 w=40u l=200n
M6 w=29.15u l=200n
M7 w=29.15u l=200n
M8 w=29.15u l=200n
M9 w=29.15u l=200n
M10 w=29.15u l=200n
M10 w=29.15u l=200n
Rload=6k ohms
R3 and R4=200 ohms
Capacitor = 101pF
V4 and V5 Vpulse Amp=2V Freq=0.1GHz
V2 and V3 Vsin Amp=1v Freq=0.2GHz
Spice Code:
* C:\Users\Keerti Vardhan\Desktop\vlsi\final1.asc

M1 N001 x N002 0 NMOS l=200n w=29.15u

M2 x N003 N006 0 NMOS l=200n w=40u

M3 y N004 N006 0 NMOS l=200n w=40u

M4 x N004 N005 0 NMOS l=200n w=40u

M5 y N003 N005 0 NMOS l=200n w=40u

M6 N001 y N007 0 NMOS l=200n w=29.15u

M7 N006 N009 N011 0 NMOS l=200n w=29.15u

M8 N005 N010 N011 0 NMOS l=200n w=29.15u

M9 N002 N008 0 0 NMOS l=200n w=29.15u

M10 N011 N012 0 0 NMOS l=200n w=29.15u

M11 N007 N008 0 0 NMOS l=200n w=29.15u

M12 N008 N008 0 0 NMOS l=200n w=29.15u

M13 N012 N012 0 0 NMOS l=200n w=29.15u

R1 N001 x 6k

R2 N001 y 6k

C1 N009 N013 101f

C2 N010 N014 101f

R3 N001 N008 200

R4 N001 N012 200

V1 N001 0 15

V2 N013 0 SINE(0 -1 0.2G)

V3 N014 0 SINE(0 1 0.2G)

V4 N003 0 PULSE(0 2 0 0.01n 0.01n 5n 10n)

V5 N004 0 PULSE(2 0 0 0.01n 0.01n 5n 10n)

.model NMOS NMOS

.model PMOS PMOS

.lib C:\Users\Keerti Vardhan\Documents\LTspiceXVII\lib\cmp\standard.mos

.tran 10n

Design:
Theoretical
RL= RD||Ron = 6k ohms|| (4/(1.245mA/2))
= 6k || 6.425k
=3.1026k ohms

Av=gm 2/pi Rl
=sqrt( 2 unCox W/L Iref) * 2/pi * Rl
=sqrt ( 2 * 21.22u * 40u/200n * 1.25m/2 ) *0.6366 *
3.1026k
=2.303m * 0.6366 * 3.1026k
= 4.547

Practical gain :
Vout p-p = 8V
Vin p-p = 2V
Analysis
Input Voltage:

Local Oscillator:
Output Waveform:

Single ended:

Differential output:
Applications:
Four Quadrant Analog multiplier
Variable gain multiplier
Automatic gain control currents
Balanced Modulator
Frequency Mixer
Phase Detector