--Divisor de frecuencia de 50MHz a 1Hz para parpadeo de LED

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk1Hz is
Port (
clk50Mhz: in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC;
phase_a : out STD_LOGIC;
phase_b : out STD_LOGIC;
phase_c : out STD_LOGIC;
phase_d : out STD_LOGIC;
led_a : out STD_LOGIC;
led_b : out STD_LOGIC;
led_c : out STD_LOGIC;
led_d : out STD_LOGIC);
end clk1Hz;

architecture Behavioral of clk1Hz is

signal coils: std_logic_vector(3 downto 0) := "0000";
signal i: integer range 0 to 3 := 0;
signal pulso: STD_LOGIC;
signal contador: integer range 0 to 24999999 := 0;
begin
divisor_frecuencia: process (reset, clk50Mhz) begin
if (reset = '0') then
pulso <= '0';
contador <= 0;
end if;
if (reset = '1') then
if rising_edge(clk50Mhz) then
if (contador = 24999999) then
if i = 0 then
coils <= "0101";
end if;
if i = 1 then
coils <= "0110";
end if;
if i = 2 then
coils <= "1010";
end if;
if i = 3 then
coils <= "1001";
end if;
i <= i+1;
pulso <= not (pulso);
contador <= 0;
end if;
contador <= contador+1;
end if;
end if;
end process;
phase_a <= coils(0);
phase_b <= coils(1);
phase_c <= coils(2);
phase_d <= coils(3);
led_a <= coils(0);
led_b <= coils(1);
led_c <= coils(2);
 led_d <= coils(3);
led <= pulso;
end Behavioral;