BiCMOS055 Technology Offer

STMicroelectronics
Technology & Design Platforms, Crolles

February 2016
 Best-in-class BiCMOS
BiCMOS055 (B55)* is:
fT
HS cells: ST data IBM data
The latest BiCMOS technology developed

Standard cells density (Kgate/mm)

fMAX HD cells: ST data
600 1200

HS NPN peak fT and fMAX(GHz)

Wafer size
in STMicroelectronics to address 200 mm 300 mm
500 1000

SG13G2 (IHP)

BiCMOS055
BICMOS9HP
demanding Optical, Wireless and High-

BICMOS8XP

(IBM)

(ST)
BiCMOS9MW
400 800

(IBM)
Performance Analog Applications

(ST)
300 600

The only high-speed BiCMOS technology in

INTEL
200 400

55-nm CMOS fabricated in 300-mm 100 200

manufacturing facility 0 0
130 nm 90 nm 55 nm
Pre-production qualified CMOS node

(*) P. Chevalier et al, 55 nm Triple Gate Oxide 9 Metal Layers SiGe BiCMOS Technology Featuring 320 GHz fT / 370 GHz fMAX HBT and High-Q Millimeter-Wave Passives
Proceedings of the 2014 International Electron Devices Meeting (IEDM), San Francisco, CA (USA), 15-17 December 2014, pp. 7779
BiCMOS055 February 2016
 15 years BiCMOS at ST
Continuous improvement of SiGe HBT performance with CMOS scaling
fT and fMAX increased by a factor of ~6 from 0.35m to 55nm CMOS nodes
400
BiCMOS6G
BiCMOS7
BiCMOS7RF
300 BiCMOS9
BiCMOS9MW
BiCMOS055

fT (GHz)
200

100

0
0.1 1 10 100
Collector current density JC (mA/m)

400
BiCMOS6G
BiCMOS7
BiCMOS7RF
300 BiCMOS9
BiCMOS9MW
BiCMOS055

fMAX (GHz)
200

100

0
0.1 1 10 100

BiCMOS055 February 2016 Collector current density JC (mA/m)

Technology offer & devices targets

BiCMOS055 February 2016

 Overview
55nm triple-gate oxide CMOS baseline
LP & GP HVT, SVT & LVT* CMOS w/ 2.5V IOs + LP SVT & HVT SRAM*
High-Performance Analog GO1 LP LVT CMOS*
Natural bipolar transistors, resistors & capacitors + 6 k/sq. HIPO resistor*

+ + +
SiGe NPN HBTs AMOS varactors Thick copper BEOL
(High-Speed Diode varactors 5 fF/m MIM*
Medium-Voltage Thin Film Resistor*
& High-Voltage*) Transmission lines
Inductors

55-nm SiGe BiCMOS technology = BiCMOS055

Core process: 50 masks / Options: Up to +11 masks (w/o bumping)
(*) Option

BiCMOS055 February 2016

Technology cross-sections

BiCMOS055 February 2016

 BEOL schematic cross-section
9 metal layers (including Aluminum capping) BEOL obtained by the
introduction of a thick Via/Line copper module :
3m thick M8U and 1.5m thick V7U
MIM integrated in V5Z BiCMOS055 CMOS055
TFR integrated in V6Z 8M4X2Z1U 7M4X2Z0U
AP
CB

All the 55-nm CMOS libraries

M8U
are therefore compatible AP
Via7U
with BiCMOS055 M7Z M7Z
Via6Z TFR Via6Z
M6Z M6Z
Via5Z MIM Via5Z
M5X M5X
Via4X Via4X

M1 M1
polySi polySi
M2 to Last Metal Layer 5.5m 3.1m

BiCMOS055 February 2016

 BiCMOS055 devices list (DK2.3)
Core Options
LP/GP HVT & SVT CMOS w/ 2.5V GO2 LP & GP CMOS LVT
(incl. RF SVT for LP, GP & GO2) (incl. RF models for LP & GP)
High-Speed & Medium-Voltage SiGe HBTs SRAM SVT + HVT
Natural devices High-Performance Analog (HPA) CMOS
NPN & PNP bipolar transistors (incl. RF models)
Resistors (active, poly & metal incl. RF resistors) High-Voltage SiGe HBTs
Diodes (N+/Pwell, P+/Nwell, Deep Nwell/Psub,) 6k/sq. HIPO resistor
DC capacitors (poly, plate) (incl. RF model)
Varactors 5fF/m MIM capacitor
Single & Diff. GO1/GO2 P+ poly/Nwell varactors (incl. RF model)
P+/Nwell diode varactor Thin Film Resistor
RF MOM Flip-Chip bumping
MMW, HQ & LOHQ inductors
strip transmission line

BiCMOS055 February 2016

Devices targets
LP & GP CMOS
Low Power (LP) and General Purpose (GP) CMOS
Low Power MOS (TOX=18.5) General Purpose MOS (TOX=13)
Device
ION (A/m) IOFF (nA/m) ION (A/m) IOFF (nA/m)
Low VT NMOS 740 5 970 382

Low VT PMOS 390 2.4 460 204

Standard VT NMOS 610 0.35 830 51

Standard VT PMOS 305 0.1 395 36

High VT NMOS 430 0.015 669 5

High VT PMOS 210 0.010 300 4

Ldrawn=0.06m, Wdrawn= 1.0 m, T=25C

BiCMOS055 February 2016

Devices targets
SiGe HBTs
3 collector flavors sharing the same E/B system
Scalable emitter widths and lengths
fT fMAX BVCBO BVCEO High-speed SiGe HBT schematic cross-section
Device
(GHz) (GHz) (V) (V)
Pedestal B in-situ doped As in-situ doped B doped
HS NPN SiGe HBT 320 370 5.2 1.5 oxide SiGe:C Base Emitter Polybase
npnvhs, npnvhs_t VCB=0.5V VCB=0.5V ICB=10A IB=0A
C C C B E B C C C
VBE=0.90V VBE=0.90V

MV NPN SiGe HBT 180 380 7.2 1.8

npnvmv, npnvmv_t VCB=1.0V VCB=1.0V ICB=10A IB=0A
VBE=0.87V VBE=0.87V
Localized Collector Collector Sinker

Epitaxial Collector Shallow Trench Isolation (STI)

HV NPN SiGe HBT 70 250 13.5 3.2
Buried Layer Deep Trench Isolation (DTI)
npnvhv, npnvhv_t VCB=2.0V VCB=2.0V ICB=10A IB=0A
VBE=0.80V VBE=0.80V Double Polysilicon Self-Aligned (DPSA) architecture
featuring a Selective Epitaxial Growth (SEG) of the base

CBEBC: Wdrawn= 0.2 m, Ldrawn=5.56m, T=25C

BiCMOS055 February 2016

Devices targets
Varactors & capacitors
P+ Poly/NWell GO1 & GO2 benefit from short gate lengths
Typical Max Q Freq_res
Capacitance
Oxide tuning ratio @ C =100 fF @ C =100 fF
range
Device type @ 25 GHz @ 25 GHz @ 1,2 V (GO1)
(Cmin / max)
@ C =100 fF @ V =1,2 V @ 2,5 V (GO2)
Varactor P+/NWell GO1 SE GO1 5 fF / 1 pF 3 20 > 110 GHz
cpo12nw_var 1,2 V (max 5)
Varactor P+/NWell GO2 SE GO2 5 fF / 1 pF 3 30 > 110 GHz
cpo25nw_var 2,5 V (max 5)

RF MOM
C0~0.9 fF/m (M1-M2) to ~3.0 fFm (M1-M5) / CV1 < 1 ppm/V

MIM
C0=5.0 fF/m / CV1 < 150 ppm/V / CV2 < 100 ppm/V

BiCMOS055 February 2016

Devices targets
Inductors & transmission lines
Inductors & TL benefit from the 8ML BEOL with thick V7/M8
Self
Device Stack L Qmax resonance
frequency
MMW Inductor Coil M8U From 65pH > 10 From 27GHz
ind_mmw_8m4x0y2z1u Upath M7Z to 1.6nH to 300GHz
Gnd ring M1
Inductors geometry: 1-turn inductor 3D view
Number of coil turns (n): 1 to 4.25 4.25-turn inductor 3D view
Internal coil diameter (d): 10 to 50 m
Coil width (w): 0.6 to 4 m M8 line

Device Stack Zc IL M1 gnd

-strip TL Line in M8U From 35 0.5dB/mm
microstrip_8m4x0y2z1u Gnd in M1 or M4 to 70 @60GHz Lateral wall
3D schematic view

BiCMOS055 February 2016

 Masks count
All options are compatible with each other*
Process options Masks count
Core process 50
SRAM 3
Triple-VT Low-VT (LVT, SVT and HVT transistors) 2
High-Performance Analog (HPA) CMOS 2/4*
HIPO (6k/sq poly resistor) 1
HV (High-Voltage) NPN 0
MIM (5fF/m) 2
TFR (Thin Film Resistor) 1
Flip-Chip 1
(*) HPA CMOS are LVT MOS devices. This option requires 2 masks in addition
to LVT option, then 4 masks if standard LVT MOS devices are not used
BiCMOS055 February 2016
Design kit & design platform

BiCMOS055 February 2016

 Design kit
Front-end/Schematic capture EDA tools EDA Vendors

Schematic Capture (Composer) IC Cadence

Simulation model libraries Eldo Mentor

Spectre Cadence

Hspice Synopsys

RF Simulation ADS (RFDE) Agilenteesof

GoldenGate Agilenteesof

ADS environment ADSKit ST

Layout Entry & Finishing EDA tools EDA Vendors

Layout Placement Virtuoso Layout Editor Cadence

Layout Verification : DRC/LVS Calibre Mentor

DFM YA/YE/YS pvs Cadence
Parasitic Extraction : interconnect RC StarRCXT Synopsys
ext Cadence
Post Layout Simulation flow PLSKit ST
Totem Apache

BiCMOS055 February 2016

Design platform content

BiCMOS055 February 2016

 Design platform flows

BiCMOS055 February 2016

Design platform version

BiCMOS055 February 2016

 Design flow

BiCMOS055 February 2016