IEEE TRANSACTIONS ON BROADCASTING, VOL. 48, NO.
1, MARCH 2002
channel conditions and different number of users. The simulation pa-
rameters of the test system are summarized in Table II. Fig. 3 shows the
comparative performance of slot synchronization with different pulse
shaping filters in a multipath multiuser environment. It can be seen that
the performance is more or less same for different filter coefficients.
The system is tested for path detection error and subsequent bit error
rate for different number of users. Fig. 4 shows the BER performance of
a multiuser DS-CDMA system with the proposed pulse shaping func-
tion in a slow fading Rayleigh channel. Both pulse shaping functions
(with continuous coefficients and with modified coefficients) give al-
most identical performance for similar channel conditions. Hence, from
the simulation studies, it can be concluded that significant computa-
tional reduction can be obtained without much of performance degra-
dation. This is significant, especially when considering the fact that the
modified coefficients do not require any multipliers in the hardware
implementation. Hence this kind of architecture is highly suitable for
pulse-shaping filters for very high data rate communications.
VII. CONCLUSION
This correspondence presents an efficient algorithm to generate
optimum coefficients of pulse shaping filters for efficient VLSI im-
plementation. By discarding end coefficients and by representing the
modified coefficients in powers-of-two, one can achieve significantly
simpler pulse shaping functions. Using PFP representation, which
represents coefficients in terms of a shift and span, can further reduce
the word length of filter coefficients. PFP representation lead to
power and reliability advantages as shown recently [11]. Due to their
very simple structure, these filters could potentially operate at very
high data rates and hence are ideally suited for high-speed wireless
transmission and reception. The new filter coefficients are extensively
simulated for different channel conditions.
REFERENCES
[1] C. K. Chen and J. H. Lee, Design of linear-phase quadrature mirror
filters with powers-of-two coefficients, IEEE Trans. Circuits Syst. II:
Analog and Digital Signal Processing, vol. 41, July 1994.
[2] , Design of QMF with linear-phase in the frequency domain,
IEEE Trans. on Circuits Syst. II: Analog and Digital Signal Processing,
vol. 39, pp. 593605, Sept. 1992.
[3] H. Samueli, The design of multiplierless digital data transmission fil-
ters with powers-of-two coefficients, IEEE Conf. Vehic. Traffic, pp.
19.2.119.2.4, 1990.
[4] K. Hwang, Advanced Computer Architecture: Parallelism, Scalability,
Programmability. New York: McGraw-Hill, 1993.
[5] Matlab Reference Manual, Communications Tool Box Users Guide.
[6] A. B. Premkumar and A. P. Vinod, A modified algorithm to eliminate
pass band anomaly in QMF designed in frequency domain, IEEE Signal
Processing Letters, to be published.
[7] J. D. Johnston, A filter family designed for use in QMF banks, in Proc.
IEEE Int. Conf. Acoust., Speech and Signal Processing, Apr. 1980, pp.
291294.
[8] C. K. Chen and J. H. Lee, Design of QMFs with linear phase in the
frequency domain, IEEE Trans. Circuits Syst. II, vol. 309, pp. 593605,
Sept. 1992.
[9] A. B. Premkumar, M. Bhardwaj, and A. S. Madhukumar, Pseudo
floating point MAC units for programmable high performance QMF
banks, in 7th Annual NASA Symp. VLSI Design, Alburquerque, NM,
USA, Oct. 1998, pp. 3.4.13.4.14.
[10] A. S. Madhukumar and F. Chin, Code synchronization and path delay
estimation for a CDMA system using long code masking, in Proc., Int.
Symp. Circuits Syst. 2000, Switzerland, May 2000.
[11] M. Bhardwaj and A. Balaram, Low power signal processing architec-
tures using residue arithmetic, in Proc. ICASSP 98, Seattle, WA, USA,
May 1998, pp. 30173020.
0018-9316/02$17.00 2002 IEEE
57
Design of a 3780-Point IFFT Processor for TDS-OFDM
Zhi-Xing Yang, Yu-Peng Hu, Chang-Yong Pan, and Lin Yang
AbstractThis correspondence presents a design of 3780-point IFFT
Processor for TDS-OFDM terrestrial DTV transmitter using FPGA. It
demonstrates the algorithm design and error analysis of the processor,
which can achieve a throughput of 7.56M complex IFFT operations
per second. This design meets the signal-to-quantization noise ratio
requirement of the TDS-OFDM system. It consists of two FPGA and one
dual-port RAM. The data stream pipeline algorithm is implemented.
Index TermsCircuit optimization, FFT, HDTV, pipeline processing,
signal processing.
I. INTRODUCTION
Time Domain Synchronous-OFDM (TDS-OFDM) [1], [2] is the key
technology of the Terrestrial Digital Multimedia/Television Broad-
casting (DMB-T) [1], [2] proposed by Tsinghua University, Beijing
China, as an important candidate for the Chinese HDTV territorial
transmission standard. It uses 8 MHz bandwidth and 3780 subcarriers
to transfer HDTV signal. To implement TDS-OFDM technology, the
implementation and optimization of 3780-point IFFT/FFT processor
is a crucial work.
By discomposing 3780 into 9 2 7 2 3 2 5 2 4, and using Winograd
Fourier transform algorithm (WFTA) [3][5] for computing the 7, 9,
3, 5, 4-point DFT, and GoodThomas prime factor algorithm (PFA)
[6], [7], [13], an algorithm and its implementation for 3780-point IFFT
is proposed in Section II. Its fixed-point error is derived based on the
theoretical analysis of Robert W. Patterson and James H. Mcclellan [8]
in Section III. The comparison of the computation complexity, buffer
requirement, and latency of the proposed 3780-point IFFT and radix-4
4096-point IFFT is listed in Section IV.
II. ALGORITHM DESIGN AND ITS IMPLEMENTATION
N
If , a large number with composite factor, is not the power of 2. The
N
approach of implement -point DFT is to implement its small factor
N
DFT and build up the -point DFT with index mapping algorithm. We
use WFTA to implement the small number DFT.
WFTA can be represented in matrix notation by
X = ODIx
(1)
x I
where is the input vector, is a rectangular matrix requires only addi-
D O
tions and subtractions, is a diagonal matrix, is a rectangular matrix
X x
requiring only additions and subtractions, and is the DFT of .
Due to this none radix-2 FFT, the implementation of WFTA is the
key of the processor. Their implementation is hardware-consume.
Moreover, because the RAM is a common and inexpensive component
in IC design, this design focus on the limiting the hardware cost in
arithmetic unit. This correspondence proposed a data stream pipeline
algorithm as shown in Fig. 1, which has only one rotator.
Besides the conjugate and 64QAM mapping module, this algorithm
consists of a 63-point PFA module, a rotator, a 60-point PFA module,
and the Cache I and the Cache III to perform row and column
Manuscript received December 26, 2001; revised February 12, 2002.
The authors are with the Department of Electronic Engineering, Tsinghua
University, Tsinghua, Beijing, P.R. China.
Publisher Item Identifier S 0018-9316(02)04000-3.
58
Fig. 1. The data stream pipeline algorithm of 3780-point IFFT algorithm.
Fig. 2. 3-point WFTA module.
Fig. 3. The data stream of the I stage of 3-point WFTA.
index-mapping. The 63-point PFA module consists of a 7-point WFTA
module, Cache II, and a 9-point WFTA module. The 60-point PFA
module consists of a 15-point PFA module, Cache V, and a 4-point
DFT module. The 15-point PFA module consists of a 3-point WFTA
module, Cache IV, and a 5-point DFT module. The Cache II, Cache IV,
and Cache V perform prime factor algorithm (PFA) index-mapping.
As Fig. 1, the input conjugate module and output conjugate module
together with FFT module constitute the IFFT processor. The output of
processor is not sequential unless another index mapping cache is used.
The hardware implementation of WFTA has been studied exten-
sively [9][11]. Some of the implementation performs word parallel
butterfly operation. By using above caches to rearrange data stream
for word in serials and bits in parallel, the complexity of 7, 9, 3, 5,
4-point WFTA modules can be decreased. Since X = ODI x, the
small number WFTA module consists of three stages (I ; D; O).
The 3-point WFTA module is shown in Fig. 2. The data stream of
I stage of 3-point WFTA is shown in Fig. 3. As shown in Fig. 2, the
input data pass through the shift registers R1, R2, and R3. It produces
time-skewed input for accumulator AC1, AC2, and AC3, respectively,
IEEE TRANSACTIONS ON BROADCASTING, VOL. 48, NO. 1, MARCH 2002
as shown in Fig. 3. The time-skewed coefficient input, which corre-
sponding to I matrix, control the addition and subtraction of these ac-
cumulators. At last, they output the result serially in time. The operation
of O stage is similar to it. The operation of D stage requires two real
multipliers, and its coefficient generator.
Consisting of three stages (I ; D; O), the structure of 7, 9, 5-point
WFTA module is similar to 3-point WFTA. The structure of 4-point
DFT module is similar to their I stage. Their data operation is
regularized and meet throughput requirement. They perform word
serials and bits parallel operation. Each stage is activated by a frame
synchronization signal, which identify the valid data from last stage.
After operation, it also sends frame synchronization signal to activate
next stage. There is no global control signal among modules. These
modules can be debugged separately, and cascaded in serials to
construct whole processor. So it is a rapid implementation of data
stream pipeline system.
In each WFTA module, the word length of I stage and O stage is
only determined by accumulators. So it is convenient to adjust the word
length of them. So is the coefficient of multipliers in D stage.
IEEE TRANSACTIONS ON BROADCASTING, VOL. 48, NO. 1, MARCH 2002 59

TABLE I
THE DYNAMIC RANGE AND OVERFLOW PROBABILITY OF EACH MODULE

III. OPTIMIZING WORD LENGTH method, by multiplied by factor 2m , xr (n) cos((2=N )kn) and
The required TDS-OFDM transmitter output signal-to-quantization
xi (n) sin((2=N )kn) are changed to integer random variables. The
probability distribution of Xr (K ) can be derived by convolution.
noise ratio is 45 dB to 60 dB. We can limit hardware cost by decreasing
When m increase, the precision of estimated probability distribution
unnecessary word length in each stage while fulfilling signal-to-quan-
increases. But the computation complexity increases sharply. Approx-
tization noise ratio requirement. There are two approaches, one is to
imately, We assume that the probability distribution PX (k) of Xr (k)
efficiently utilize the dynamic range of each WFTA module by appro-
equals to PX (0) , so is the dynamic range. The analysis of imaginary
priate scaling method, and the other is to limit necessary word length
part is similar with the real part. Similarly, we assume that the rotator
of each module by analysis.
has no influence of probability distribution of its output.
To utilize the dynamic range of each module efficiently, the common
We assume that the output X (k) of 63-point DFT are independent,
method is dynamic scaling method, such as block float-point method.
ignoring that X (k)s relativity will lead to the decrease of practical
But because this processor uses various index-mapping methods be-
output dynamic range and corresponding overflow probability of the
tween two computing modules, the complexity of block float-point
modules behind it. So is the 3-point and 5-point DFT.
method is close to the complexity of float-point computation. To reduce
The dynamic range and probability distribution of all WFTA output
complexity, this processor use fixed-point computing and fixed-scaling
is solved by convolution stage by stage based on above assumption. If
method. In this processor, the input of 7-point WFTA is scaled by 1/8.
fixed-point decimal in this processor exceed 1, it produces overflow.
The input of 9-point WFTA is scaled by 1/4. Then the 63-point WFTA
The dynamic range and overflow probability of each module is listed
is scaled by 1/32. The input of 3-point WFTA, the input of 5 points
in Table I.
WFTA, and the input of 4 points WFTA all are scaled by 1/2. It will pro-
The FFT processor output BER in the receiver led by the overflow
duce overflow in the output of 63-point WFTA, 3-point WFTA, 5-point
in IFFT processor in the transmitter is considerable. We assume that
WFTA, and 4-point WFTA in some case. But based on the below anal-
the overflow of each WFTA module in the IFFT processor will result
ysis, the overflow probability is very small.
in error diffusion in the FFT processor, which will lead all symbols and
We assume that the real and imaginary parts [xr (n) and xi (n)] of
bits of one OFDM frame to error. In this case, symbol error rate (SER)
the 64QAM symbol x(n) of a good information source are indepen-
equals to bit error rate (BER). The overflow probability of each module
dent uniform distribution discrete random variables. Their value range
among f07=8; 05=8; 01=8; 03=8; 3=8; 1=8; 5=8; 7=8g. Because
multiplied by 3780 is the SER due to its overflow. We assume that the
overflow is independent. The overall BER equals to the sum of them.
they are zero-symmetry, the conjugation before FFT does not change
It equals to 6.33e-9.
their range.
Based upon the above analysis, we find that this fixed-scaling
By multiplied by factor 8, xr (n) is converted to an integer random
method is appropriate so that the BER due to overflow is trivial and
variable. Because the probability distribution of the sum of integer
close to the BER of channel transmission. It efficiently utilizes the
random variables can be get by convolution of the probability distri-
dynamic range in these modules, limit hardware cost, and it simplifies
bution of them. By convolution, we can get output scaled dynamic
the implementation.
range and its probability distribution. The practical dynamic range cor-
To limit necessary word lengths in the multipliers, adders, and
responds to the scaled dynamic range divided by a factor. The proba-
memories of each module based on the output signal-to-quantization
bility distribution is corresponded to each other. We use this method to
noise ratio requirement, we use the theoretical analysis of Robert
estimate overflow probability.
Due to N -point DFT, since X (k) = N 01 0j (2=N )kn k = W. Patterson and James H. Mcclellan [8] to derive the fixed-point
n=0 x(n)e
0; 1 1 1 1 N 0 1.
arithmetic error of this algorithm.
If k = 0, Xr (0) = N 01 GoodThomas Prime factor algorithm (PFA) consists of cascading
n=0 xr (n), we can get PX (0) , the proba- several modules made up of three stages and can be represented as
bility distribution of Xr (0)
X = (ON DN IN ) 2 1 1 1 2 (O D I )x (3)
PX (0) = Px (0) 3 Px (1) 3 Px
1 1 1 3 Px N 0
(2) ( (2)
1)
1 1 1

where 2 denotes the Kronecker product operation.

where Px (n) is the probability distribution of xr (n), 3 denotes the We assume that the errors at the input of each ODI module due to
convolution operation. error sources in previous ODI modules are independent, identically
If k 6= 0, Xr (k) = N 01 fx (n) cos((2=N )kn) + distributed random variables [8]. Due to the ith module, Ni denotes
n=0 r
xi (n) sin((2=N )kn)g. If this algorithm will be implemented its dimension, si denotes total scaling from input to output of it, N
2

in fixed-point system, and its word length is m bits. By similar denotes its output average scaled error variance, which is produced by
60 IEEE TRANSACTIONS ON BROADCASTING, VOL. 48, NO. 1, MARCH 2002

TABLE II
THE WORD LENGTHS EXAMPLE OF EACH STAGE IN 3780 POINTS IFFT ALGORITHM

TABLE III
COMPARISON

the error sources in it. Then the system output error variance due to where bN denotes the word lengths of stage D multiplication output
error source in the ith module is [8] in it.
2 ,
Due to Nj module, its output total average scaled error variance N
t
2
N Nj =sj2 1 it due to error sources in it, is the sum of (7) and (8) [8].
j=i+1 (4) Due to rotator, its average output scaled error variance due to error
2
N i = t:
sources in it is

2 02b 02q
k2
2 2
The total average error variance at the output is [8] rotator = + (9)
t01 t 3 6

2 = 2
N Nj =sj2 + N
2 : (5) where brotator denotes the word lengths of multiplication output of it,
i=1 j=i+1 qrotator denotes word lengths of multiplication coefficient of it. Be-
Based on (5), the total average error variance of this algorithm is cause the 4-point WFTA has no multiplication, it can be ignored.
If the word lengths of O , D , and I stage of every module is deter-
72 1024
540 + 92 60 + rotator
64
2 60 2 20 24
64 + 3 16 + 5 4 + 4
2 (6) mined, based on (6)(9), we can derive the output error variance of this
2
where rotator denotes average error variance at the output of the ro- algorithm. By simulation and theoretical analysis, two groups of word
tator due to error sources in it. lengths designed for output 45 dB and 60 dB signal-to-quantization
The error variance N 2 for each module depends on three types of noise ratio are derived, which is showed in Table II. In case of 45 dB
errors: scaling errors, coefficient quantification errors, and rounding er- design, due to 50 simulation runs, the average output signal-to-quanti-
rors of a multiplication. In this design, if the input of A stage is scaled zation noise ratio is 44.58 dB. Due to theoretical analysis, it is 44.31 dB.
by 1=sA , where sA = 2k , k is an integer, the A stage word lengths is In case of 60 dB design, due to 50 simulation runs, the average output
k bits more than the word lengths of input, scaling error can be elimi- signal-to-quantization noise ratio is 60.40 dB. Due to theoretical anal-
nated. We can focus on coefficient quantification errors and rounding ysis, it is 60.12 dB. The error variance of simulation is a little lower
errors of a multiplication in D stage of each module. than the error variance of the theoretical analysis. This could be due to
Due to Nj module, its output average scaled error variance due to the correlation of error source, which was assumed to be zero in the
coefficient quantification error in it is [8] theoretical analysis.
In the Table II, the word length of I stage of 7 points WFTA is 7
02q
k2 ON F IN INT T
2 bits, because 4 bits is used to denote the real/imaginary part of uniform
ON (7)
mapped 64QAM input data, and it divided by 8 is to prevent from over-
12
where qN denotes the word lengths of stage D multiplication coeffi- flow. The fixed-scaling method decided the word length of the O stage
cient in it, k2 is the variance of input, F (Q) is the diagonal matrix made of 7-point WFTA is 2 bits less than the I stage of next 9-point-WFTA.
up of the diagonal elements of the matrix Q, AT denotes the conjugate So are others.
transpose of the matrix A.
Due to Nj module, its output average scaled error variance due to IV. CONCLUSION
product round error in it is [8] A comparison between this 3780-point IFFT and radix-4 4096-point
02b IFFT/FFT is listed in Table III. Comparing to the efficient radix-4 split-
2 T
ON ON (8)
6
radix algorithm [12], the real additions and real multiplication of pro-
IEEE TRANSACTIONS ON BROADCASTING, VOL. 48, NO. 1, MARCH 2002
posed algorithm is close to it. It contributes to the decrease of arithmetic
unit complexity.
The latency of this 3780-point IFFT processor is appropriately 1.97
times greater than the latency of the 4096-point IFFT processor. Its la-
tency is approximate 1068 s with interleaved output. Its output will
be sequential by adding a cache. Then its latency will be approximate
1568 s. Due to broadcasting application, which meets the design re-
quirement.
To compare the buffer requirement, we assume that the each stage
output word length of radix-4 4096 FFT processor is 13 bits. The total
buffer requirement of it is 4095 3 13 3 2 = 106 470 bits. The word
length of all the caches of this 3780-point IFFT is listed in Table II.
The buffer requirement of Cache I, Cache II, Cache III, Cache IV, and
Cache V, respectively, are 4275 3 3 3 2 = 25 650 bits, 126 3 11 3 2
= 2772 bits, 4215 3 13 3 2 = 109 590 bits, 30 3 12 3 2 = 720 bits,
and 120 3 12 3 2 = 2880 bits. Where Cache I and Cache III require
the greatest capacity. They are used for matrix transpose and index-
mapping. So the total buffer requirement of this processor are 141 612
bits. It is appropriately 1.33 times greater than the buffer requirement
of 4096-point IFFT cascade processor.
Due to hardware cost, this 3780-point IFFT is close to 4096-point
IFFT.
In TDS-OFDM system, base-band symbol rate is 7.56 MHz. If we
use 4096-point IFFT and interpolation algorithm to implement 3780-
point IFFT, the hardware cost will increase proportion to the precision
of interpolation algorithm. The other problem is that the sample rate of
4096-point IFFT frame will be different from the system sample rate.
It increases extra complexity to timing synchronization. So this rapid
implementation is suit for TDS-OFDM system.
At the case of output signal-to-quantization noise ratio of 45 dB, the
processor is implemented in two XILINX VirtexE XCV300E FPGAs
and one general dual-port RAM. Based on the regular data stream in
this processor, the buffer-consume Cache III is implemented off-chip,
in the general dual-port RAM. It saves hardware cost of FPGA. The
circuit works as the design requirement. For output signal-to-quantiza-
tion noise ratio of 60 dB, the implementation is under testing.
REFERENCES
[1] Terrestrial digital multimedia/television broadcasting system,
P.R.China Patent 00 123 597.4 filed Aug. 25, 2000, issued Mar. 21,
2001.
[2] ITU-T Document 6E/50-E and Document 6P/36-E, Terrestrial digital
multimedia/television broadcasting system development in China, Int.
Telecommun. Union, Geneva, Mar. 26, 2001.
[3] S. Winograd, On computing the discrete Fourier transform, Proc. Nat.
Acad. Sci. USA, vol. 73, no. 4, pp. 10051006, Apr. 1976.
[4] , On computing the discrete Fourier transform, Math. Compet.,
vol. 32, no. 141, pp. 175199, Jan. 1978.
[5] H. F. Silverman, An introduction to programming the Winograd Fourier
transform algorithm, IEEE Trans. Acoust., Speech, Signal Processing,
vol. ASSP-25, no. 2, pp. 152164, Apr. 1977.
[6] D. P. Kolba and T. W. Parks, A prime factor FFT algorithm using high-
speed convolution, IEEE Trans. Acoust., Speech, Signal Processing,
vol. ASSP-25, pp. 281294, Aug. 1977.
[7] I. J. Good, The interaction algorithm and practical Fourier series, J.
Royal Stat. Soc., ser. B, vol. 20, pp. 361372, 1958.
[8] R. W. Patterson and J. H. Mcclellan, Fixed-point error analysis of Wino-
grad Fourier transform algorithms, IEEE Trans. Acoust., Speech, Signal
Processing, vol. ASSP-26, pp. 447455, Oct. 1978.
[9] R. M. Owens and J. JaJa, A VLSI chip for the Winograd/prime factor
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[10] M. D. MacLeod and N. L. Bragg, Fast hardware inplementation of the
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0018-9316/02$17.00 2002 IEEE
61
[11] C. M. Wu, R. T. Wang, and C. T. Yen, Adder-based SIMD-systolic ar-
chitectures and VLSI chip for computing the Winograd small FFT algo-
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dendum, vol. 22, pp. 372375, 1960.
Comments on Spectral Efficiency of VMSK
Saso Tomazic
AbstractThis correspondence demonstrates that no ultra narrow band
modulation (UNBM) method, which includes very minimum shift keying
(VMSK) and VPSK, can have substantially greater efficiency than con-
ventional methods, such as quadrature amplitude modulation (QAM), in
transmission in the same frequency band.
Index TermsQuadrature amplitude modulation (QAM), ultra narrow
band modulation (UNBM), very minimum shift keying (VMSK), VPSK.
I. INTRODUCTION
Recently, the exceptional properties of a new modulation method
named VMSK (very minimum shift keying) have been heavily adver-
tised, especially on the Internet. Two companies in particular are active
in this area: AlphaCom Communications and Pegasus Data Systems.
To quote only two of their most typical marketing statements: What
this means to the end user is data transmission speeds up to 1000 times
faster than present 56 Kbpswith less distortion, at probably half the
price of current monthly DSL and cable ISP rates [1]; VMSK mod-
ulation is a very unique modulation method for transmitting digital in-
formation that does not require a spreading of the bandwidth, therefore
20 to 50 times as many radio stations could be put on the dial [2].
The story begins in 1997 with a paper by Walker [3], to which
most of the advertising claims also refer. Although the same author
later presented his idea at several places, e.g., [4][7], it is safe to
say that the publication of the paper in the IEEE TRANSACTIONS
ON BROADCASTING carried the greatest scientific weight and thus
contributed the most to the creation of the illusion spread by VMSK
proponents. It is thus appropriate that this illusion should be refuted
in the same TRANSACTIONS.
The purpose of this correspondence is not to conduct a precise anal-
ysis of the VMSK modulation method or to determine where the au-
thor went wrong in his rather vague presentation of the method. We
wish merely to show that no modulation method can increase the ef-
ficiency of conventional modulation methods to the extent promised
by VMSK proponents. The same conclusion thus applies to any ultra
narrow band modulation (UNBM) which has appeared (or may yet ap-
pear) as a derivative of VMSK or its alternative.
II. SIMPLE PROOF
The basic assertion made by VMSK proponents is that, in the ultra
narrow frequency band occupied by VMSK, we can achieve a much
Manuscript received July 26, 2001.
The author is with the Faculty of Electrical Engineering, University of Ljubl-
jana, Trzaska 25, 1000 Ljubljana, Slovenia (e-mail: saso.tomazic@fe.uni-lj.si).
Publisher Item Identifier S 0018-9316(02)03289-4.