Analysis of Pulse Clocks in

PrimeTime
Application Note
April 2014
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Contents
Introduction ................................................................................................................................... 1
Functional Behavior of Pulse Latches and Pulse Clocks .............................................................. 1
Pulse Clock Behavior in PrimeTime .............................................................................................. 2
Edge Relationship Between Master Clock and Pulse Clock ..................................................... 2
Types of Pulse Clocks and Pulse Generator Cell ..................................................................... 3
Modeling Pulse Clock Generators................................................................................................. 3
Using a Library Model for the Pulse Generator (Recommended) ............................................. 3
Specifying a Pulse Clock at Each Pulse Generation Point ....................................................... 5
Specifying the Sense of an Existing Clock ................................................................................ 5
Constraining a Pulse Clock Generator .......................................................................................... 5
Merging Pulse Clocks Generated From the Same Clock With Conflicting Pulse Sense .......... 6
Merging a Normal Clock and a Pulse Clock Not Generated From the Same Clock ................. 6
Reporting Undefined Pulse Generators and Ignored Pulse Constraints ................................... 7
Handling Pulse Types Set by the set_sense Command ........................................................... 7
Analyzing Designs With Pulse Clocks........................................................................................... 7
Design Rule Checks ................................................................................................................. 8
Minimum and Maximum Slew Limits ..................................................................................... 8
Minimum and Maximum Pulse Width .................................................................................... 9
Pulse Latches Not Driven by the Pulse Clock ..................................................................... 10
Analyzing a Path With a Pulse Clock ...................................................................................... 10
Setup and Hold Checks ...................................................................................................... 10
Pulse Width Check .............................................................................................................. 12
Conclusion .................................................................................................................................. 12

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Introduction
In a system-on-chip (SoC), the clock network consumes a large amount of dynamic
power because of the switching of flip-flops, which contain two latches triggered by a
clock signal. One method of reducing dynamic power uses pulse latches and pulse
clocks. A pulse latch is similar to an edge-triggered flip-flop, but it consumes much less
power.
This application note describes how to use PrimeTime to analyze designs using pulse
latches and pulse clocks.

Functional Behavior of Pulse Latches and Pulse Clocks

A latch captures data during the active window determined by the width of clock
waveform. If the pulse clock waveform triggers a latch, it is synchronized with the clock
similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock
are almost identical in terms of timing.
A pulsed latch needs a pulse generator that generates a pulse clock waveform from the
source clock. The generated pulses must meet the minimum pulse width requirement to
be usable. Figure 1 shows a pulse generator that generates a pulse clock waveform.
Figure 1 Pulse generator and waveform

Typically, pulse latches that use a rise-triggered pulse have setup checks verified on the
rising edge and hold checks verified on the falling edge of the clock. Flip-flops use a
single clock edge to check both the setup and hold checks; in the case of a rise-
triggered flip-flop, this occurs on the rising edge of the clock. Figure 2 describes the
timing arc for setup and hold checks.

1
Figure 2 Timing arc for setup and hold check

Pulse Clock Behavior in PrimeTime

Edge Relationship Between Master Clock and Pulse Clock
Types of Pulse Clocks and Pulse Generator Cell

Edge Relationship Between Master Clock and Pulse Clock

Figure 3 shows the edge relationship between the master clock and pulse clock. This
example describes the rising edge of the master clock to the pulse generator generates
both rising and falling edge at the output.
Figure 3 Edge relationships between master clock and pulse clock

Figure 4 shows the output of the pulse generator to be non-unate because there are
both inverting and non-inverting paths through the logic. The non-inverting path is direct
path through the AND gate and the inverting path is through the inverter.
Figure 4 Non-unate clock sense for pulse generator

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 Types of Pulse Clocks and Pulse Generator Cell
PrimeTime supports four types of pulse clocks and pulse generator cell. Figure 5 to
Figure 8 explain the clock sense and pulse types.
Figure 5 Rise-triggered high pulse

Figure 6 Rise-triggered low pulse

Figure 7 Fall-triggered high pulse

Figure 8 Fall-triggered low pulse

Modeling Pulse Clock Generators

To define a pulse generator, use one of the following methods:
Using a Library Model for the Pulse Generator (Recommended)
If the library is missing a pulse generator description, use one of these methods:
o Specifying a Pulse Clock at Each Pulse Generation Point
o Specifying the Sense of an Existing Clock

Using a Library Model for the Pulse Generator (Recommended)

PrimeTime supports specific syntax of .lib model. In the library, there must be an
attribute that specifies a pulse generator. The generator of a pulse clock does not add an
additional clock domain to the analysis. This is elaborated in the following .lib syntax:
pulse_clock : pulse_type

The following are valid pulse_type values:

rise_triggered_high_pulse

3
 rise_triggered_low_pulse
fall_triggered_high_pulse
fall_triggered_low_pulse

For example:
pin(Y) {
...
pulse_clock : rise_triggered_low_pulse ;
...
}

The following example shows a .lib definition of a rise-triggered high pulse:

cell(rise_high_pulse){
pin(i){
max_transition : 0.03;
direction : input;
capacitance : 0.0222;
}
pin(z){
max_capacitance : 1.33;
direction : output;
pulse_clock : rise_triggered_high_pulse;
timing() {
related_pin : "i";
timing_type : combinational_rise ;
timing_sense : positive_unate ;
cell_rise(load_7x3){
index_1 ( xxxx );
index_2 ( xxxx );
values( xxx );
}
rise_transition(load_3x4){
index_1 ( xxxx );
index_2 ( xx);
values( xxxx);
}
}
timing() {
related_pin : "i";
timing_type : combinational_fall ;
timing_sense : negative_unate ;
cell_fall(load_7x4){
index_1 ( xxxx );
index_2 ( xxxx );
values(xxx );
}
fall_transition(load_3x3){
index_1 ( xxx );
index_2 ( xxx );
values( xxx );
}
}
}
}

4
 Specifying a Pulse Clock at Each Pulse Generation Point
If the library is missing a pulse generator definition, you can specify the pulse clock
characteristics at each pulse generation point in the design by using the
create_generated_clock command. For example:
create_generated_clock edges {1 1 3} name PULSE_CLK source CLK \
{PULSE_GENERATOR/Z}
Figure 9 Defining non-increasing edges (rise_triggered_high_pulse)

In Figure 9, the position of the repeated digit determines whether an active-high or

active-low pulse is generated. The edge number that is repeated determines the type of
edge in the master clock used to trigger the pulse:
-edges {1 1 3} Rising edge of source triggers high pulse
-edges {2 2 4} Falling edge of source triggers high pulse
-edges {1 3 3} Rising edge of source triggers low pulse
-edges {2 4 4} Falling edge of source triggers low pulse

By using the create_generated_clock command, you can create a new clock domain
at a pulse generation point.

Specifying the Sense of an Existing Clock

If the library is missing a pulse generator description, you can specify the sense of the
existing clock by using the set_sense command. For example:
pt_shell> set_sense pulse rise_triggered_high_pulse and/z

In this case, the pulse clock is not defined as a separate clock domain. Instead, it is just
a different sense (rise-triggered high pulse sense) of the source clock downstream from
the specified point in the clock network.

Constraining a Pulse Clock Generator

When applying timing constraints in a design with pulse clocks, consider these issues:
Merging Pulse Clocks Generated From the Same Clock With Conflicting Pulse
Sense
Merging a Normal Clock and a Pulse Clock Not Generated From the Same Clock
Reporting Undefined Pulse Generators and Ignored Pulse Constraints
Handling Pulse Types Set by the set_sense Command

5
 Merging Pulse Clocks Generated From the Same Clock With
Conflicting Pulse Sense
If pulse clocks with conflicting senses merge, an error message is generated during a
timing update. If you set the set_sense command at the merge point, the sense and
pulse type of one pulse clock is propagated. For example, in Figure 10, a rise-triggered
high pulse clock is merged with a rise-triggered low pulse clock, and the following error
message is reported.
Error: pulse clock sense merging at pin: 'gater/Z'for clock: 'clk'
The clock will not propagate forward from this pin.
(PTE-080)
Figure 10 Pulse generator

Merging a Normal Clock and a Pulse Clock Not Generated From

the Same Clock
In PrimeTime, if a pulse clock and a normal clock (which is not a pulse clock) propagate
in the pulse clock network, the tool issues a warning message during the check_timing
command. Figure 11 shows an example of merging a normal clock (clk1) and a pulse
clock.
Figure 11 Pulse clock and normal clock merge

pt_shell> check_timing

Information: Checking 'pulse_clock_non_pulse_clock_merge'

Warning: There is 1 pin where pulse clock and non pulse clock merge

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 Reporting Undefined Pulse Generators and Ignored Pulse
Constraints
The tool does not issue warning messages when pulse constraints are ignored because
of undefined pulse generators. Instead, you must use the check_timing command with
the pulse_clock_no_pulse_generator option. For example:
pt_shell> check_timing -override_defaults \
{pulse_clock_no_pulse_generator} \
verbose

Information: Checking 'pulse_clock_no_pulse_generator'.

Warning: There are 2 objects where pulse clock constraints are applied
without pulse generator
Object type Object name Limit type
---------------------------------------------------------------------
cell and1 pulse_clock_min_width_transitive_fanout

Handling Pulse Types Set by the set_sense Command

In PrimeTime, you can apply pulse types by using the set_sense -pulse command.
These error messages are different than the propagating pulse in the pulse generator
network.
pt_shell> set_sense -pulse rise_triggered_low_pulse [get_pin PG/z]
1
pt_shell> report_pulse_clock_max_width -significant_digits 4
Error: Cannot honor set_sense -pulse option at pin 'PG/z'.
Clock 'clk' is missing needed rise and/or fall, or has
conflicting high or low pulse types at this pin (PTE-081)

Analyzing Designs With Pulse Clocks

To enable pulse clock analysis, set the timing_enable_pulse_clock_constraints
variable to true (the default). Figure 12 shows a logic example that explains how to
analyze pulse clocks in PrimeTime.
Figure 12 Logic example to analyze pulse clock

To learn about analyzing pulse clocks in PrimeTime, see these topics:

Design Rule Checks
Analyzing a Path With a Pulse Clock

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Design Rule Checks
You must check the following design rules:
Minimum and Maximum Slew Limits
Minimum and Maximum Pulse Width
Pulse Latches Not Driven by the Pulse Clock

Minimum and Maximum Slew Limits

Use the following commands for a maximum transition constraint:
To apply a maximum transition check to the pulse clock network from the pulse
generator point, use the set_pulse_clock_max_transition -transitive_fanout
command.
To report the results, use the report_pulse_clock_max_transition -
transitive_fanout command.

To remove the constraint, use the remove_pulse_clock_max_transition

command. By removing the constraint, you can change the constraint on the object.
The following example shows a maximum transition at the transitive fanout of the pulse
generator:
pt_shell> set_pulse_clock_max_transition -transitive_fanout 0.04 \
[current_design]
pt_shell> set_pulse_clock_max_transition -transitive_fanout 0.03 \
[get_clock clk]
pt_shell> set_pulse_clock_max_transition -transitive_fanout 0.02 \
{"celllib/pulse_rise_high"}
pt_shell> set_pulse_clock_max_transition -transitive_fanout 0.01 PG

pt_shell> report_pulse_clock_max_transition -transitive_fanout

pulse_clock_max_transition_rise_transitive_fanout

Required Actual
Pin Transition Transition Slack
-------------------------------------------------------
PL1/cp 0.01 0.08 -0.07 (VIOLATED)
buf1/z 0.01 0.08 -0.07 (VIOLATED)
buf2/i 0.01 0.08 -0.07 (VIOLATED)
PL2/cp 0.01 0.07 -0.06 (VIOLATED)
buf2/z 0.01 0.07 -0.06 (VIOLATED)
PG/z 0.01 0.02 -0.01 (VIOLATED)
buf1/i 0.01 0.02 -0.01 (VIOLATED)

pulse_clock_max_transition_fall_transitive_fanout

Required Actual
Pin Transition Transition Slack
-------------------------------------------------------
PL1/cp 0.01 0.06 -0.05 (VIOLATED)
buf1/z 0.01 0.06 -0.05 (VIOLATED)
buf2/i 0.01 0.06 -0.05 (VIOLATED)
PL2/cp 0.01 0.04 -0.03 (VIOLATED)

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buf2/z 0.01 0.04 -0.03 (VIOLATED)
PG/z 0.01 0.02 -0.01 (VIOLATED)
buf1/i 0.01 0.02 -0.01 (VIOLATED)

You can apply, report, or remove a minimum transition constraint only at the input of the
pulse generator. This restriction ensures the proper functioning of pulse generators. The
following example reports only the pulse generator input pin, PG/i:
pt_shell> set_pulse_clock_min_transition 0.01 [current_design]
pt_shell> set_pulse_clock_min_transition 0.02 [get_clock clk]
pt_shell> set_pulse_clock_min_transition 0.03 \
{"celllib/pulse_rise_high"}
pt_shell> set_pulse_clock_min_transition 0.04 PG
pt_shell> report_pulse_clock_min_transition

pulse_clock_min_transition_rise

Required Actual
Pin Transition Transition Slack
------------------------------------------------------------
PG/i 0.04 0.08 0.04 (MET)

pulse_clock_min_transition_fall

Required Actual
Pin Transition Transition Slack
------------------------------------------------------------
PG/i 0.04 0.05 0.01 (MET)

pt_shell> remove_pulse_clock_min_transition PG

pulse_clock_min_transition_rise

Required Actual
Pin Transition Transition Slack
------------------------------------------------------------
PG/i 0.03 0.08 0.05 (MET)

pulse_clock_min_transition_fall

Required Actual
Pin Transition Transition Slack
------------------------------------------------------------
PG/i 0.03 0.05 0.02 (MET)

Minimum and Maximum Pulse Width

To apply minimum and maximum pulse width constraints on the fanout of a pulse
generator network, use the set_pulse_clock_min_width and
set_pulse_clock_max_width commands. The following example shows a minimum
pulse width check at the transitive fanout of a pulse clock network:
pt_shell> set_pulse_clock_min_width 0.005 [current_design]

pt_shell> report_pulse_clock_min_width -significant_digits 3

sequential_pulse_clock_min_width_transitive_fanout

9
 Required Actual
Pin pulse width pulse width Slack
-------------------------------------------------------------------
PL2/cp (high) 0.500 0.471 -0.029 (VIOLATED)
PL1/cp (high) 0.500 0.507 0.007 (MET)

clock_tree_pulse_clock_min_width_transitive_fanout

Required Actual
Pin pulse width pulse width Slack
--------------------------------------------------------------
buf2/i (high) 0.005 0.507 0.502 (MET)
PG/z (high) 0.005 0.530 0.525 (MET)
buf1/i (high) 0.005 0.530 0.525 (MET)
buf1/z (high) 0.005 0.507 0.502 (MET)
buf2/z (high) 0.005 0.471 0.466 (MET)

Pulse Latches Not Driven by the Pulse Clock

Currently, PrimeTime does not check whether the pulse latches are driven by a pulse
clock or a normal clock.

Analyzing a Path With a Pulse Clock

When analyzing paths with pulse clock, you should consider these checks:
Setup and Hold Checks
Pulse Width Check

Setup and Hold Checks

For setup analysis, the launching edge is the rise edge of rise_high_pulse and the
capturing edge is the next rise edge of rise_high_pulse. In PrimeTime, clock
reconvergence pessimism (CRP) removal with pulse clock is similar to normal clock. For
hold analysis, the launching edge is the rise edge of rise_high_pulse and the
capturing edge is the fall edge of rise_high_pulse.
Figure 13 Launch edges used for setup and hold checks

setup
hold

For example,

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Startpoint: PL1 (rising edge-triggered flip-flop clocked by clk(rise
high pulse))
Endpoint: PL2 (rising edge-triggered flip-flop clocked by clk(rise high
pulse))
Path Group: clk
Path Type: max

Point Trans Incr Path

---------------------------------------------------------------------
clock clk(rise high pulse) (rise edge) 0.00 0.00
clock source latency 0.00 0.00
clk (in) 0.00 0.00 0.00 r
mbuf1/z (buf) 0.08 0.09 0.09 r
PG/z (pulse_rise_high) 0.02 0.11 0.21 r
buf1/z (buf) 0.08 0.11 0.31 r
PL1/cp (ff) 0.08 0.00 0.31 r
PL1/qn (ff) 0.05 0.22 0.54 r
buf3/z (buf) 0.05 0.09 0.63 r
PL2/d (ff) 0.05 0.00 0.63 r
data arrival time 0.63

clock clk(rise high pulse) (rise edge) 5.00 5.00

clock source latency 0.00 5.00
clk (in) 0.00 0.00 5.00 r
mbuf1/z (buf) 0.08 0.09 5.09 r
PG/z (pulse_rise_high) 0.02 0.11 5.21 r
buf1/z (buf) 0.08 0.11 5.31 r
buf2/z (buf) 0.07 0.12 5.43 r
PL2/cp (ff) 0.07 0.00 5.43 r
clock reconvergence pessimism 0.00 5.43
library setup time -0.15 5.28
data required time 5.28
---------------------------------------------------------------------
data required time 5.28
data arrival time -0.63
---------------------------------------------------------------------
slack (MET) 4.65

Startpoint: PL1 (rising edge-triggered flip-flop clocked by clk(rise

high pulse))
Endpoint: PL2 (rising edge-triggered flip-flop clocked by clk(rise high
pulse))
Path Group: clk
Path Type: min

Point Trans Incr Path

---------------------------------------------------------------------
clock clk(rise high pulse) (rise edge) 0.00 0.00
clock source latency 0.00 0.00
clk (in) 0.00 0.00 0.00 r
mbuf1/z (buf) 0.08 0.09 0.09 r
PG/z (pulse_rise_high) 0.02 0.11 0.21 r
buf1/z (buf) 0.08 0.11 0.31 r
PL1/cp (ff) 0.08 0.00 0.31 r
PL1/qn (ff) 0.04 0.19 0.50 f
buf3/z (buf) 0.04 0.07 0.56 f
PL2/d (ff) 0.04 0.00 0.56 f
data arrival time 0.56

11
 clock clk(rise high pulse) (fall edge) 0.00 0.00
clock source latency 0.00 0.00
clk (in) 0.00 0.00 0.00 r
mbuf1/z (buf) 0.08 0.09 0.09 r
PG/z (pulse_rise_high) 0.02 0.64 0.74 f
buf1/z (buf) 0.06 0.08 0.82 f
buf2/z (buf) 0.04 0.08 0.90 f
PL2/cp (ff) 0.04 0.00 0.90 f
clock reconvergence pessimism 0.00 0.90
library hold time -0.12 0.78
data required time 0.78
---------------------------------------------------------------------
data required time 0.78
data arrival time -0.56
---------------------------------------------------------------------
slack (VIOLATED) -0.21

Pulse Width Check

For more information about applying minimum and maximum pulse width, see the
Design Rule Checks section. You can do a detailed analysis of the pulse clock open
edge and close edge clock latency. If clock reconvergence pessimism removal (CRPR)
is enabled, the clock reconvergence pessimism (CRP) value is applied to the pulse width
as a credit. For example:
Pin: PL2/cp
Related clock: clk
Check: sequential_pulse_clock_min_width_transitive_fanout

Point Incr Path

------------------------------------------------------------------
clock clk(rise high pulse) (rise edge) 0.00 0.00
clock network delay (propagated) 0.43 0.43 r
PL2/cp 0.00 0.43 r
open edge clock latency 0.43

clock clk(rise high pulse) (fall edge) 0.00 0.00

clock network delay (propagated) 0.90 0.90 f
PL2/cp 0.00 0.90 f
clock reconvergence pessimism 0.00 0.90
close edge clock latency 0.90
------------------------------------------------------------------
required pulse width (high) 0.50
actual pulse width 0.47
------------------------------------------------------------------
slack (VIOLATED) -0.03

Conclusion
This document described in detail the functional behavior of pulse clocks and modeling
of the pulse generator cell. It also described the rules of pulse clock constraint check in
PrimeTime. Finally, it explains how to analyze pulse clocks including setup and hold
analysis in PrimeTime.

12