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You are on page 1of 17

CMOS CIRCUITS

Outline

CMOS Inverter: Propagation Delay

CMOS Inverter: Power Dissipation

CMOS: Static Logic Gates

Reading Assignment:

Howe and Sodini; Chapter 5, Sections 5.4 & 5.5

1. Complementary MOS (CMOS) Inverter

Circuit schematic:

VDD

VIN VOUT

CL

Basic Operation:

VGSn = 0 ( < VTn ) NMOS OFF

VSGp = VDD ( > - VTp ) PMOS ON

VIN = VDD VOUT = 0

VGSn = VDD ( > VTn ) NMOS ON

VSGp = 0 ( < - VTp ) PMOS OFF

2. CMOS inverter: Propagation delay

and output signals; figure of merit of logic speed.

per clock cycle.

VIN

VDD

tCYCLE

0

t

VDD

50% tCYCLE

0

t

1

tp = (t PHL + t PLH )

2

CMOS inverter:

Propagation delay high-to-low

VDD

VIN: VOUT:

LO HI HI LO

CL

VIN=VDD VOUT=VDD

CL CL CL

and PMOS is cut-off.

1

charge on C L @t = 0

t pHL 2

NMOS discharge current

CMOS inverter:

Propagation delay high-to-low (contd.)

Charge in CL at t=0-:

QL t = 0 (

)= C L VDD

Wn

nCox (VDD VTn )

2

I Dn =

2Ln

Then: CL VDD

t PHL

Wn

n Cox (VDD VTn )

2

Ln

Graphical Interpretation

ID VOUT

t = tPHL t = 0+

VIN = VOH

VOH

t = 0

VOH

VIN = 0V

2

0 0

0 VOUT 0 tPHL t

VOH VOH

2

(a) (b)

CMOS inverter:

Propagation delay low-to-high

VDD

VIN: VOUT:

HI LO LO HI

CL

VIN=0 VOUT=0

CL CL CL

and NMOS is cut-off.

1

charge on C L @t =

t PLH 2

PMOS charge current

CMOS inverter:

Propagation delay high-to-low (contd.)

Charge in CL at t= :

Q L (t = ) = CL VDD

Charge Current (PMOS in saturation):

IDp =

Wp

2Lp

pCox VDD + VTp ( )

2

Then:

CL VDD

t PLH

( )

Wp 2

p Cox VDD + VTp

Lp

VDD tp

Reason: VDD Q(CL ) , but ID goes as square

Trade-off: VDD more power consumed.

L tp

Reason: L ID

Trade-off: manufacturing cost!

Components of load capacitance CL:

Following logic gates: must add capacitance of

each gate of every transistor the output is connected

to.

Interconnect wires that connects output to input of

following logic gates

Own drain-to-body capacitances

VDD

W

L p2

VDD VDD 2

W

W L n2

L p1

VIN VIN 1

+ VDD

CL VOUT W

L n1 W

L p3

3

W

L n3

(a) (b)

Gate Capacitance of Next Stage

Estimation of the input capacitance:

n- and p-channel transistors in the next stage

switch from triode through saturation to cutoff

during a high-low or low-high transition

accurately model

CG for example circuit

C G = C ox (WL) p2 + Cox (WL)n2 +

Cox (WL) p3 + Cox (WL)n3

Interconnect Capacitance

;;

Wires consist of metal lines connecting the output of

the inverter to the input of the next stage

;;;;;

;;;;;

;;;;;

;;;;;

;;;;;

;;;;;

;;;;;

;;;;;

polysilicon metal interconnect

;

;

;;

;

0.5 m thermal oxide

p+

p (grounded)

gate oxide

the thick thermal oxide (500 nm = 0.5 mm) and deposited

oxide (600 nm = 0.6 mm) depletes only slightly when

positive voltages appear on the metal line, so the

capacitance is approximately the oxide capacitance:

can dominate the load capacitance

Parasitic Capacitance-Drain/Bulk

Depletion

source gate oxide bulk

deposited

interconnect n+ polysilicon gate drain interconnect

oxide

interconnect

;;;;

;;;;

;;;

;;;;

;;;;

;;

;;;;

;;;;

;;;;

;

L

n+ drain diffusion p+

n+ source diffusion Ldiff

field

oxide [ p-type ]

(a )

;;

active area (thin

;;;;; ; ; ; ; ;

;;;;; ; ; ; ; ; ;

;;;;; ;;;;;;;;;;;;

; ; ;;;;;;;;;;;;;;

oxide area)

gate contact

;

interconnect

contact

;

n+ polysilicon gate

;;; metal

;;

interconnect

;;;;;;;;;;;;

;

;;;;;;;;

;

; ;

;

A

;

; ;

;

;;

source contacts

;

;

W

;

bulk

contact

;

;;

drain

;

;

contacts

;

source edge of

;

drain

interconnect interconnect active area

;

;

L

(b)

L

;

W

Ldiff

(c)

Calculation of Parasitic Drain/Bulk Junction

Depletion Capacitance

Depletion qJ(vD) is non-linear --> take the worst case and use the zero-

bias capacitance Cjo as a linear charge-storage element during the transient.

contribute a depletion capacitance:

Where: CJn and CJp are the zero-bias bottom capacitance (fF/m2) for the

n-channel and p-channel MOSFET drain-bulk junction, respectively.

additional contribution:

Where: CJSWn and CJSWp are the zero-bias sidewall capacitance (F/m) for

the n-channel and p-channel MOSFET drain-bulk junction, respectively.

The sum of CJBOT and CJSW is the total depletion capacitance, CDB

Power Dissipation

Energy from power supply needed to charge up the capacitor:

Energy stored in capacitor:

Estore = 1/ 2C LVDD 2

Energy lost in p-channel MOSFET during charging:

identical amount of energy.

If the charge/discharge cycle is repeated f times/second,

where f is the clock frequency, the dynamic power

dissipation is:

P = 2E diss * f = C L VDD 2 f

cycle which lowers the power dissipation.

CMOS Static Logic Gates

VDD

M4

A

B M3

A M1 B M2 VOUT

_

(a)

VDD

A M3 M4

A

+

B

B M2 VOUT

_

M1

(b)

CMOS NAND Gate

I-V Characteristics of n-channel devices

VDD

VM M3 M4 ID

VM

VM M2 VGS1 = VM

+

VGS2 = VM VDS1

M1 VDS1 ID1 = ID2

;;;

;;;

VDS

(a) (b)

VM

VM

;; ;;

gate gate

;;

;;

;; ;;

M1 M2

source drain

n+

L1 L2

(a)

VM

VM

;; ;;

gate gate

M1 M2

source drain

L1 L2

(b)

Kneff = kn1/2 = kn2/2 Recall kn = W/LnCox

Effective width of two p-channel devices is 2Wp BUT

worst case only one device is on

Kpeff = kp3 = kp4

6.012 Spring 2007 Lecture 13 15

Calculation of static and transient

performance for NAND Gate

kpeff

= kneff is desirable for equal

propagation delays and symmetrical transfer

characteristics

Recall n = 2p

Therefore (W/L)n = (W/L)p

for 2-input NAND gate

W M W

=

L n 2 L p

What did we learn today?

Summary of Key Concepts

No current between power supply and ground while

inverter is idle in any logic state

rail-to-rail logic

Logic levels are 0 and VDD.

High |Av| around the logic threshold

Good noise margins.

engineered through Wn/Ln and Wp/Lp.

VDD tp

L tp

Sizing static gates

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