Errata

SLAZ661G October 2015 Revised May 2017

MSP430FR2533 Device Erratasheet

1 Revision History
The check mark indicates that the issue is present in the specified revision.
The revision of the device can be identified by the revision letter on the Package Markings or by the
HW_ID located inside the TLV structure of the device
Rev A

Errata Number
ADC50
ADC63
BSL18
CPU21
CPU22
CPU40
CPU46
EEM23
PORT28
USCI42
USCI45
USCI47

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Package Markings www.ti.com

2 Package Markings

RHB32 QFN (RHB), 32 Pin

DA32 TSSOP (DA), 32 Pin

3 Memory-Mapped Hardware Revision (TLV Structure)

Die Revision TLV Hardware Revision

Rev A 10h

Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device
User's Guide.

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www.ti.com Detailed Bug Description

4 Detailed Bug Description

ADC50 ADC Module

Function Erroneous ADC conversion result for internal temperature sensor in LPM3 mode

Description When ACLK is used as ADC clock source and device is in LPM3 mode while sampling
the on-chip temperature sensor, the ADC may generate erroneous conversion results.

Workaround 1) Use SMCLK or MODCLK as the ADC clock source. A 100us sampling time is required
if triggering ADC conversion from LPM3.
OR
2) Use LPM0 or Active Mode.

ADC63 ADC Module

Function ADCHI/ADCLO may be reset unexpectedly when ADCCTL2 high byte is written byte-
wise

Description ADCHI/ADCLO may be reset unexpectedly when ADCCTL2 high byte is written byte-
wise.

Workaround Write to ADCCTL2 high byte in word-wise method.

BSL18 BSL Module

Function Empty reset vector does not invoke BSL

Description An empty reset vector (for example, as on an un-programmed device) should invoke the
BSL, but it does not on affected devices.

Workaround Use the dedicated TEST and RST pins to perform hardware BSL invocation, or perform
software BSL invocation from the main application. See the MSP430FR4xx and
MSP430FR2xx Bootloader (BSL) Users Guide SLAU610 for more information on BSL
entry.

CPU21 CPUXv2 Module

Function Using POPM instruction on Status register may result in device hang up

Description When an active interrupt service request is pending and the POPM instruction is used to
set the Status Register (SR) and initiate entry into a low power mode , the device may
hang up.

Workaround None. It is recommended not to use POPM instruction on the Status Register.
Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

User is required to add the compiler or

TI MSP430 Compiler Tools (Code
Composer Studio)
MSP430 GNU Compiler (MSP430-GCC)
v4.0.x or later assembler flag option below.
--silicon_errata=CPU21
MSP430-GCC 4.9 build 167 or later

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CPU22 CPUXv2 Module

Function Indirect addressing mode with the Program Counter as the source register may produce
unexpected results

Description When using the indirect addressing mode in an instruction with the Program Counter
(PC) as the source operand, the instruction that follows immediately does not get
executed.
For example in the code below, the ADD instruction does not get executed.

mov @PC, R7
add #1h, R4

Workaround Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

User is required to add the compiler or

TI MSP430 Compiler Tools (Code
Composer Studio)
MSP430 GNU Compiler (MSP430-GCC)
v4.0.x or later assembler flag option below.
--silicon_errata=CPU22
MSP430-GCC 4.9 build 167 or later

CPU40 CPUXv2 Module

Function PC is corrupted when executing jump/conditional jump instruction that is followed by

instruction with PC as destination register or a data section

Description If the value at the memory location immediately following a jump/conditional jump
instruction is 0X40h or 0X50h (where X = don't care), which could either be an
instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as
destination register or a data section (const data in flash memory or data variable in
RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed;
therefore, branching to a wrong address location in code and leading to wrong program
execution.
For example, a conditional jump instruction followed by data section (0140h).
@0x8012 Loop DEC.W R6
@0x8014 DEC.W R7
@0x8016 JNZ Loop
@0x8018 Value1 DW 0140h

Workaround In assembly, insert a NOP between the jump/conditional jump instruction and program
code with instruction that contains PC as destination register or the data section.
Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

For the command line version add the

following information
IAR Embedded Workbench IAR EW430 v5.51 or later
Compiler: --hw_workaround=CPU40
Assembler:-v1

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IDE/Compiler Version Number Notes
TI MSP430 Compiler Tools (Code
v4.0.x or later
Composer Studio)
MSP430 GNU Compiler (MSP430-GCC) Not affected

CPU46 CPUXv2 Module

Function POPM peforms unexpected memory access and can cause VMAIFG to be set

Description When the POPM assembly instruction is executed, the last Stack Pointer increment is
followed by an unintended read access to the memory. If this read access is performed
on vacant memory, the VMAIFG will be set and can trigger the corresponding interrupt
(SFRIE1.VMAIE) if it is enabled. This issue occurs if the POPM assembly instruction is
performed up to the top of the STACK.

Workaround If the user is utilizing C, they will not be impacted by this issue. All TI/IAR/GCC pre-built
libraries are not impacted by this bug. To ensure that POPM is never executed up to the
memory border of the STACK when using assembly it is recommended to either
1. Initialize the SP to
a. TOP of STACK - 4 bytes if POPM.A is used
b. TOP of STACK - 2 bytes if POPM.W is used
OR
2. Use the POPM instruction for all but the last restore operation. For the the last restore
operation use the POP assembly instruction instead.
For instance, instead of using:

POPM.W #5,R13

Use:

POPM.W #4,R12
POP.W R13

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

C code is not impacted by this bug. User

IAR Embedded Workbench Not affected using POPM instruction in assembler is
required to implement the above
workaround manually.

C code is not impacted by this bug. User

TI MSP430 Compiler Tools (Code using POPM instruction in assembler is
Not affected
Composer Studio) required to implement the above
workaround manually.

C code is not impacted by this bug. User

MSP430 GNU Compiler (MSP430-GCC) Not affected using POPM instruction in assembler is
required to implement the above
workaround manually.

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EEM23 EEM Module

Function EEM triggers incorrectly when modules using wait states are enabled

Description When modules using wait states (USB, MPY, CRC and FRAM controller in manual
mode) are enabled, the EEM may trigger incorrectly. This can lead to an incorrect profile
counter value or cause issues with the EEMs data watch point, state storage, and
breakpoint functionality.

Workaround None.

NOTE: This erratum affects debug mode only.

PORT28 PORT Module

Function Pull-down resistor of TEST/SBWTCK pin

Description The device's internal pull-down resistor on the TEST/SBWTCK pin gets disabled if the
SYS control bit SFRRPCR.SYSRSTRE is cleared. This can lead to increased current
consumption and unintentionally-enabled JTAG access to the device.

Workaround 1) Do not clear the SFRRPCR.SYSRSTRE bit, use the SFRRPCR.SYSRSTRUP bit to
define direction of the internal resistor on RST/NMI/SBWTDIO pin instead.
OR
2) Ensure a zero voltage level of TEST/SBWTCK pin by connecting the pin to an
external component (e.g. external pull-down resistor) on the PCB.

USCI42 eUSCI Module

Function UART asserts UCTXCPTIFG after each byte in multi-byte transmission

Description UCTXCPTIFG flag is triggered at the last stop bit of every UART byte transmission,
independently of an empty buffer, when transmitting multiple byte sequences via UART.
The erroneous UART behavior occurs with and without DMA transfer.

Workaround None.

USCI45 eUSCI Module

Function Unexpected SPI clock stretching possible

Description In rare cases, during SPI communication, the clock high phase of the first data bit may
be stretched significantly. The SPI operation completes as expected with no data loss.
This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to
the system clock (MCLK).

Workaround Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are
synchronous to each other.

USCI47 eUSCI Module

Function eUSCI_A SPI slave receive with clock phase UCCKPH = 1

Description When the eUSCI_A module is configured as a SPI slave with clock phase mode
UCCKPH = 1 in the UCAxCTLW0 register, if the UCAxCLK pin is not at the appropriate

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idle level (low for UCCKPL = 0, high for UCCKPL = 1) when the UCSWRST bit in the
UCAxCTLW0 register is cleared, the SPI module will not be able to receive a byte. In
this case the UCAxRXBUF will not be filled and UCRXIFG in the UCAxIFG register will
not be set.
eUSCI_B modules are not affected.

Workaround Use an eUSCI_B module for SPI slave if UCCKPH = 1 clock phase mode is required.
OR
Check the UCAxCLK pin level in software and wait until the correct level is available (low
for UCCKPL = 0, high for UCCKPL = 1) before clearing the UCSWRST bit in the
UCAxCTLW0 register. This is only possible if the master provides the correct level since
the SPI CLK is controlled by the master.

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5 Document Revision History

Changes from device specific erratasheet to document Revision A.
1. Device name changed from "XMS" to "MSP430"
Changes from document Revision A to Revision B.
1. Errata ADC63 was added to the errata documentation.
Changes from document Revision B to Revision C.
1. Errata USCI42 was added to the errata documentation.
Changes from document Revision C to Revision D.
1. Errata CPU46 was added to the errata documentation.
Changes from document Revision D to Revision E.
1. CPU21 was added to the errata documentation.
2. USCI45 was added to the errata documentation.
3. CPU22 was added to the errata documentation.
4. Workaround for CPU40 was updated.
5. Workaround for CPU46 was updated.
Changes from document Revision E to Revision F.
1. BSL18 was added to the errata documentation.
2. TLV Hardware Revision section was added to the documentation.
3. Workaround for CPU46 was updated.
Changes from document Revision F to Revision G.
1. USCI47 was added to the errata documentation.

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