Pr r

Programming
i I/O – 1
ARM ‡ Embedded systems usually include some
I/O, Exceptions, Interrupts non-digital components
‡ Digital interface to CPU: status & data
registers
status
Tulika
T lik Mit
Mitra

meechanism
m
reg
National University of Singapore CPU
data
tulika@comp.nus.edu.sg reg

10/3/2007 CS5272 © 2007 Tulika Mitra 1 10/3/2007 CS5272 © 2007 Tulika Mitra 2

Pr r
Programming
i I/O - 2 I/O R
Register
i t rBBasics
i
Address
‡ Memory-mapped ‡ I/O Registers are NOT like normal memory
Data
„ Device events can change their values (e.g., status reg)
„ Devices are mapped CPU
Read „ Reading a register can change its value (e.g., error
to specific memory Write condition
co d o reset)
ese )
locations just like „ read-only (e.g., receive registers) , write-only (e.g.,
RAM Memory I/O Device transmit registers)
„ Uses load/store „ Multiple registers mapped to same address
Address
instructions just like Data
‡ Clear from context
accesses to memory CPU Memory I/O
‡ The bits in a control register often each specify something
different and important -- and have significant side effects
I/O mapped
R d
Read
‡
Write ‡ Cache must be disabled for memory-mapped addresses
„ Special bus line and I/O Port ‡ When polling I/O registers, should tell compiler that value
instructions M
Memory can change on its own
I/O Device
10/3/2007 CS5272 © 2007 Tulika Mitra 3 „
10/3/2007 volatile int *ptr; CS5272 © 2007 Tulika Mitra 4

ARM memory-mapped
r pp d I/O M
Memory-mapped
r pp d I/O
I/O: E
Example
pl
‡ Define location for device ‡ A device containing eight 8-bit registers at addresses
0x00001000 – 0x00001007
DEV1 EQU 0x1000 ‡ The decoder activates chip enable for this address range
‡ Address
dd ess bits
b s A0—A2
0 are
a e used for
o register
eg s e select
se ec
‡ Example: storing the lowest byte of processor register r3 in
‡ Read/write code device register R2
ADR r1,DEV1
r1 DEV1 ; set up device address LDR r1
r1, =0x1002
0x1002
STR r3, [r1]
LDR r0,[r1] ; read DEV1
MOV r0r0,#8
#8 ; sett up
p value
l tot write
rit
STR r0,[r1] ; write value to device

10/3/2007 CS5272 © 2007 Tulika Mitra 5 10/3/2007 CS5272 © 2007 Tulika Mitra 6
M
Memory-mapped
r pp d I/O iin C V l til variable
Volatile ri bl
int p
peek(char
( *location)) volatile int *p
p_status;
status;
{ return *location; } p_status = (int *) 0x4001;
while ((
((*p
p_status
status & 0x01) == 0);
void poke(char *location,char value)
‡ Compiler allocates (*p_status) to register
{ *location = value; } „ Infinite loop as ((*p
p_status)
status) will not be updated
‡ Volatile keyword ensures that compiler will
#define DEV1 0x1000 not allocate it in register and will not allow
dev_status = peek((char *)DEV1); it to be put in data cache
poke((char *)DEV1, 8);

10/3/2007 CS5272 © 2007 Tulika Mitra 7 10/3/2007 CS5272 © 2007 Tulika Mitra 8

E
Example:
pl SSerial
ri l I/O - 1 Example: Serial I/O - 2
‡ Processor has parallel buses for data -- need to convert ‡ High level I/O call
High-level
serial data to parallel (and vice versa)
„ printf(“the number is %d\n”, someNumber);
‡ UART - Universal asynchronous receiver and transmitter
‡ Low-level details
Chip Reg
Select
Tx Clock „ printf()is a library call which formats the
R/W output (e.g., converts %d formats) and then
Control
makes system call to output the formatted
IRQ
Tx Data Reg Tx Shift Reg Tx Data string
St t Reg
Status R ‡ Formatted string is nothing more than an array of
CTS characters
D0-D7 Data Control Reg
Bus RTS ‡ Low-level routines then output the string one character
Buffers Rx Data Reg Rx Shift Reg Rx Data at a time using UART
Rx Clock
10/3/2007 CS5272 © 2007 Tulika Mitra 9 10/3/2007 CS5272 © 2007 Tulika Mitra 10

C
Conceptual
pt l Vi
View off D
Device
i Dri
Driverr Ch k UART fforr space
Check p
while (*string != '\0') while (*string != '\0'){
string printChar(*string++); string
g if (UART is empty())
Problem
• while loop can execute a lot faster
printChar(*string++);
than the UART can transmit }
Chip Reg
Chip Reg Tx Clock
Select
Tx Clock Select
R/W
R/W
Control
Control 2
Tx Data Reg Tx Shift Reg Tx Data
Tx Data Reg Tx Shift Reg Tx Data IRQ 1
IRQ
Status Reg
St t Reg
Status R CTS
CTS D0-D7
D0-D7 Data Control Reg
Data Control Reg RTS
RTS Bus
Bus Rx Data Reg Rx Shift Reg Rx Data
Rx Data Reg Rx Shift Reg Rx Data
Rx Clock
Rx Clock
10/3/2007 CS5272 © 2007 Tulika Mitra 11 10/3/2007 CS5272 © 2007 Tulika Mitra 12
B
Busy-wait
it I/O I t rr pt
Interrupt
‡ When device is ready, it sends an interrupt
‡ Continuously test if device is ready ‡ O an interrupt,
On i t t CPU jumps
j to
t interrupt
i t t handler
h dl
current_char = mystring; ‡ Read/write of the device is done inside interrupt handler
time
while ((*current
current_char
char !=
! ‘\0’)
\0 ) {
user program user program
poke(OUT_CHAR,*current_char); Task
/* busy wait for the transmission to complete */ IRQ IRQ
Q Interrupt
p handler

while (peek(OUT_STATUS) != 0);

current_char++;
rr t h r++
}
‡ B tt option:
Better ti Interrupt
I t t Interrupt
10/3/2007 CS5272 © 2007 Tulika Mitra 13 10/3/2007 CS5272 © 2007 Tulika Mitra 14

Normal Program Flow vs.

E pti /I t rr pt
Exceptions/Interrupts E pti vs. Interrupt
Exception I t rr pt
‡ Normally,
Normally programs execute sequentially ‡ Exception refers to an internal CPU event
(with a few branches to make life interesting) „ floating point overflow
‡ Normally,
Normally programs execute in user mode „ MMU fault ((e.g.,
g , page
p g fault))
„ trap (SWI)
‡ Exceptions and interrupts break the
sequential flow of a program, jumping to ‡ Interrupt refers to an external I/O event
architecturally-defined memory locations „ I/O device request
„ reset
‡ ARM manual usually does not make
distinction between exception & interrupt

10/3/2007 CS5272 © 2007 Tulika Mitra 15 10/3/2007 CS5272 © 2007 Tulika Mitra 16

ARM E
Exceptions
pti Pr
Processor
rMModes
d
‡ User: Normal program execution
„ unable to access protected system resources
or change mode
‡ Exception modes: Additional registers to
avoid corrupting user mode
„ FIQ: fast interrupt for high-speed data transfer
„ IRQ: general-purpose interrupt handling
„ S
Supervisor
i (SVC)
(SVC): protected
t t d mode
d for
f OS
‡ System: Supervisor mode but access to
only user mode registers
10/3/2007 CS5272 © 2007 Tulika Mitra 17 10/3/2007 CS5272 © 2007 Tulika Mitra 18
Pr
Processor
r mode
d rregisters
i t r -1 Pr
Processor
r mode
d rregisters
i t r -2
‡ Exception
p handlers have access to a certain
subset of the banked registers
„ its own r13 or sp register (sp_mode)
„ its own r14 or lr register (lr_mode)
(lr mode)
„ its own saved program status registers (spsr_mode)
‡ In case of FIQ, each exception handler has access
to 5 more general-purpose registers (r8_FIQ to
r12_FIQ)
‡ Other registers must be restored to their original
contents upon exit from handler
„ Save and restore from stack

10/3/2007 CS5272 © 2007 Tulika Mitra 19 10/3/2007 CS5272 © 2007 Tulika Mitra 20

V t r ttable
Vector bl Pr
Processor
r actions
ti on exception
pti
‡ Controls exception Addr Type
yp Mode Priority
y ‡ Copy CPSR into SPSR_mode
SPSR mode
handling
‡ 32 bytes at the bottom of ‡ Change CPSR to reflect
memory map 0x0 Reset SVC 1 „ Appropriate mode
‡ One word for each
exception type
„ Map banked registers according to the mode
„ Not enough
g space
p to
0x8 SWI SVC 6 „ Disable interrupts
include full handler code ‡ IRQs on any exception
„ Contains a branch or load FIQs when a FIQ occurs and on reset
pc instruction to continue 0x18 IRQ IRQ 4 ‡

execution
ti with
ith th
the ‡ Sets lr_mode
lr mode to return address
interrupt handler
0x1C FIQ FIQ 3 ‡ Sets pc to the vector address for the
exception
10/3/2007 CS5272 © 2007 Tulika Mitra 21 10/3/2007 CS5272 © 2007 Tulika Mitra 22

R t r i fr
Returning from exception
pti M r concretely
More r t l …
‡ If entry code used stack to store registers ‡ Reset
that must be preserved while it handles „ No need to return
the exception, use LDM instruction to ‡ SWI
restore those registers „ MOVS pc, lr
‡ Restore CPSR from SPSR_mode ‡ IRQ,
Q, FIQ
Q
‡ Restore program counter using return „ SUBS pc, lr, #4
address stored in lr_mode „ Processor checks for interrupt after executing
each instruction

10/3/2007 CS5272 © 2007 Tulika Mitra 23 10/3/2007 CS5272 © 2007 Tulika Mitra 24
I t rr pt H
Interrupt Handlers
dl r N t d/R
Nested/Re-entrant
tr t Interrupts
I t rr pt
‡ Interrupts can occur within interrupt handlers time
‡ When an interrupt occurs,
occurs the hardware will jump to an
“interrupt handler” user program
time user program
Task
user program user pprogram
g
Task IRQ Interrupt handler
IRQ
IRQ Interrupt handler
IRQ FIQ FIQ Interrupt handler

FIQ
• On interrupt, the processor will set the
corresponding
p g interrupt
p bit in the CPSR
to disable subsequent interrupts of the
Interrupt same type from occurring.
Interrupt • However, interrupts of a higher priority
can still
till occur.
Second
10/3/2007 CS5272 © 2007 Tulika Mitra 25 10/3/2007
Interrupt
CS5272 © 2007 Tulika Mitra 26

Ti i off IInterrupts
Timing t rr pt I t lli iinterrupt
Installing t rr pt h
handler
dl r -11
‡ Before an interrupt handler can do anything, it must save unsigned Install_Handler (unsigned location, unsigned *vector)
away the current program's registers (if it touches those { unsigned vec, oldvec;
registers) vec = ( (unsigned location) – (unsigned) vector – 0x8) | 0xE59FF000;
‡ That's why the FIQ has lots of extra registers - to minimize oldvec = *vector;
vector;
CPU context saving overhead time
*vector = vec;
user program cpu context saved
user program return (oldvec);
Task }
IRQ
“servicing” interrupt
unsigned *irqvec = (unsigned *)0x18;
FIQ cpu context restored
static unsigned pIRQ_Handler = (unsigned)IRQ_handler;
Install_Handler (&pIRQHandler, irqvec);
Interrupt latency

10/3/2007 Interrupt CS5272 © 2007 Tulika Mitra 27 10/3/2007 CS5272 © 2007 Tulika Mitra 28

Interrupt response

I t lli iinterrupt
Installing t rr pt handler
h dl r - 2 Si pl iinterrupt
Simple t rr pt h
handler
dl r iin C
__irq void IRQHandler (void)
‡ Take the address of the exception handler
{
‡ Subtract the address of the vector volatile unsigned int *base = (unsigned int *) 0x80000000;
if (*base == 1) // which interrupt was it ?
‡ Subtract 0x8 as PC points to current
C_int_handler(); // process the interrupt
address + 0x8 *(base+1) = 0; //clear the interrupt
‡ Logically OR this with 0xE59FF000 }
‡ __irq keyword preserves all ATPCS corruptible registers,
(opcode for LDR PC, [pc, #offset]) to preserves all other registers used by the function, and exits
produce the value to be placed in the by setting PC to (lr-4) and restoring CPSR
‡ If handler calls a subroutine, __irq also preserves and
vector restores the link register from stack
‡ 0x80000000 is the memory-mapped interrupt controller
base address
10/3/2007 CS5272 © 2007 Tulika Mitra 29 10/3/2007 CS5272 © 2007 Tulika Mitra 30
R tr t interrupt
Reentrant i t rr pt handler
h dl r - 1 R tr t interrupt
Reentrant i t rr pt handler
h dl r - 2
IRQ
‡ Interrupt
p handler re-enables interrupts
p SUB lrlr, lr
lr, #4 ; return address
‡ Interrupt handler calls a subroutine (with BL STMFD sp!, {lr}
MRS r14, SPSR
; push adjusted lr_IRQ
; copy spsr_IRQ to r14
instr) and return address is copied into lr_IRQ STMFD sp!, {r12, r14} ; save work registers and spsr_IRQ
; clear interrupts
‡ Another interrupt occurs and the return address ; re-enable interrupts
of the subroutine (in lr_IRQ) is corrupted MSR CPSR_c, #0x1F ; switch to SYS mode, USR mode registers are now current
; CPSR_c are just the control bits
„ __irq
irq keyword does not help STMFD sp! sp!, {r0-r3,lr}
{r0 r3 lr} ; save lr_USR
lr USR and non
non-callee
callee saved registers
BL C_irq_handler
‡ Use system mode that uses user-mode register LDMFD sp!, {r0-r3,lr}
‡ Write top level interrupt handler in assembly MSR CPSR_c, #0x92 ; switch to IRQ mode and disable IRQs
LDMFD sp! sp!, {r12
{r12, r14}
MSR SPSR_cf, r14 ; SPSR_cf are control and conditional bits
LDMFD sp!, {pc}^ ; return from IRQ, ^ specifies CPSR is restored from SPSR
END

10/3/2007 CS5272 © 2007 Tulika Mitra 31 10/3/2007 CS5272 © 2007 Tulika Mitra 32

R tr t interrupt
Reentrant i t rr pt handler
h dl r -33 MSR andd MRS instructions
i tr ti
Save return address on IRQ stack
‡
‡ MRS and MSR are used to read and write
‡ Save work registers and spsr_IRQ
‡ Clear the source of the interrupt the Current Program Status Register
‡ Switch to system mode (CPSR) and Saved Program Status
‡ Re-enable interrupts Registers (SPSRs) of the ARM core. These
Save user mode link register and non callee-saved register
‡
‡ Call C interrupt
p handler function (user-mode
( lr register)
g )
are commonly used to change processor
‡ When the C interrupt handler returns, restore user mode mode
d andd to
t enable/disable
bl /di bl interrupts,
i t t
register and disable interrupts when the core is in a privileged mode (i.e.
Switch to IRQ node disabling interrupts
‡
‡ Restore work registers and spsr_IRQ
not User mode)
‡ Return from IRQ

10/3/2007 CS5272 © 2007 Tulika Mitra 33 10/3/2007 CS5272 © 2007 Tulika Mitra 34

P tti it allll together:

Putting t th r Interrupt
I t rr pt I/O P tti it allll together:
Putting t th r Interrupt
I t rr pt I/O
Foreground program
‡ Replaces the following busy busy-wait
wait I/O ‡
current_char
h = mystring;
i
while (*current_char != ‘\0’) {
current_char = mystring; add_char_to_buffer(*current_char);
current_char++;
while ((*current
current_char
char !=
! ‘\0’)
\0 ) { }
poke (OUT_DATA, remove_char_from_buffer()); /* put character in device */
poke(OUT_CHAR,*current_char); poke(OUT_STATUS, 1); /* initiate transmission */

/* busy wait for the transmission to complete */ ‡ I t

Interrupt
t handler
h dl (called
( ll d when
h transmission
t i i is
i complete)
l t )
void output_handler(){
while (peek(OUT_STATUS) != 0); if (!empty_buffer()){
poke(OUT_DATA, remove_char_from_buffer()); /* put character in device */
current_char++;
rr t h r++ poke(OUT_STATUS, 1); /* initiate transmission */
}
} }

10/3/2007 CS5272 © 2007 Tulika Mitra 35 10/3/2007 CS5272 © 2007 Tulika Mitra 36
 How Do We Determine the SWI
S ft r Interrupts
Software I t rr pt (SWI) number?
b r?
‡ SWIs (often called software traps) allow a ‡ All SWIs go to 0x08
user program to “call” the OS -- that is,
Vector Table
SWIs are how system calls are USER Program
starting at 0x00 in memory
SWI Handler
implemented.
0x00 to R_Handler (Reset
ADD r0,r0,r1 0x04 to U_Handler (Undef instr.) (S_Handler)
SWI 0x10 0x08 to S_Handler (SWI) SWI Handler must
‡ When SWIs execute, the processor SUB r2,r2,r0 0x0c to P_Handler (Prefetch abort)
0x10
0 0 to D D_Handler
Handler (Data abort)
serve as clearing

changes modes (from User to Supervisor

h
house f different
for diffe e t
0x14 ... (Reserved)
0x18 to I_Handler (IRQ) SWIs
mode on the ARM) and disables interrupts 0x1c to F_Handler (FIQ)

MOVS pc, lr

10/3/2007 CS5272 © 2007 Tulika Mitra 37 10/3/2007 CS5272 © 2007 Tulika Mitra 38

SWI Instruction
Instr ction Format SWI Handler Uses “Comment”
Comment Field
Example: SWI 0x18
cond 1 1 1 1 24-bit “comment” field (ignored by processor)

Vector Table starting at 0x00 in memory

USER Program SWI Handler
31 28 27 24 23 0 0x00 to R
R_Handler
Handler (Reset
ADD r0,r0,r1 0x04 to U_Handler (Undef instr.)
(S_Handler)
cond 1 1 1 1 24-bit “comment” field (ignored by processor) SWI 0x10 0x08 to S_Handler (SWI)
SUB r2,r2,r0 0x0c to P_Handler (Prefetch abort) LDR r0,[lr,#-4]
0x10 to D_Handler (Data abort) BIC r0,r0,#0xff000000
0x14 ... (Reserved)
0x18 to I_Handler (IRQ)
0x1c to F_Handler (FIQ)
R0 holds SWI number
SWI number
MOVS pc, l
lr

10/3/2007 CS5272 © 2007 Tulika Mitra 39 10/3/2007 CS5272 © 2007 Tulika Mitra 40

Use SWI # to Jump to “Service

Service Routine
Routine” Problem
P ob e with
w t The
T e Current
C e t Handler
Ha d e
cond 1 1 1 1 24-bit “comment” field (ignored by processor)
What was in R0? User program
may have been using this
Vector Table
starting at 0x00 in memory
register. Therefore, cannot just
USER Program SWI Handler use it - must first save it
0x00 to R_Handler (Reset
ADD r0,r0,r1 0x04 to U_Handler (Undef instr.)
(S_Handler) Vector Table (spring board)
SWI 0x10 0x08 to S_Handler (SWI) starting
i at 0x00
0 00 in
i memory
LDR r0,[lr,#-4] SWI Handler
SUB r2,r2,r0 0x0c to P_Handler (Prefetch abort) BIC r0,r0,#0xff000000 USER Program 0x00 to R_Handler (Reset
ADD r0,r0,r1 0x04 to U_Handler (Undef instr.)
(S_Handler)
0x10 to D_Handler (Data abort)
switch (r0){ SWI 0x10 0x08 to S_Handler (SWI)
0x14 ... (Reserved) case 0x00: service_SWI1();
LDR r0,[lr,#-4]
0x18 to I I_Handler
Handler (IRQ) case 0x01:
0 01 service_SWI2();
i SWI2() SUB r2,r2,r0 0x0c to P P_Handler
Handler (Prefetch abort) BIC r0r0,r0,#0xff000000
r0 #0xff000000
0x1c to F_Handler (FIQ) case 0x02: service_SWI3(); 0x10 to D_Handler (Data abort)
… switch (r0){
0x14 ... (Reserved) case 0x00: service_SWI1();
}
0x18 to I_Handler (IRQ) case 0x01: service_SWI2();
MOVS pc, lr case 0x02: service_SWI3();
0x1c to F_Handler (FIQ)
…
}
MOVS pc, lr

10/3/2007 CS5272 © 2007 Tulika Mitra 41 10/3/2007 CS5272 © 2007 Tulika Mitra 42
F ll SWI Handler
Full C SWI H dl r
C_SWI_Handler
Previous sp_svc
S_Handler spsr_svc
void C_SWI_handler(unsigned
( g number,
,
SUB sp,sp, #4
# ; leave room on stack for SPSR lr_svc
unsigned *regs)
STMFD sp!, {r0­r12, lr} ; store user's gp registers regs[12] r12
{ r11
MRS r2, spsr[_csxf] ; get SPSR into gp registers
switch (number){ r10
STR r2, [sp, #14*4] ; store SPSR above gp registers r9
MOV r1, sp ; pointer to parameters on stack case 0: /* SWI number 0 code */ break; r8
LDR r0, [lr, #­4] ; extract the SWI number case 1: /* SWI number 1 code */ break; r7
r6
BIC r0,r0,#0xff000000 ; get SWI # by bit-masking ... r5
BL C_SWI_handler ; go to handler (see next slide) case XXX: /* SWI number XXX code */ r4
LDR r2, [sp, #14*4] ; restore SPSR (NOT “sp!”) break; r3
MSR spsr_csxf, r2 r2
2
default:
r1
LDMFD sp!, {r0­r12, lr} ; unstack user's registers } /* end switch */ sp_svc r0
ADD sp, sp, #4 ; remove space used to store SPSR
} /* end C_SWI_handler()
() */
MOVS pc, lr ; return from handler
10/3/2007 CS5272 © 2007 Tulika Mitra 43 10/3/2007 CS5272 © 2007 Tulika Mitra 44

C SWI H dl – Contd.
C_SWI_Handler C td Calling SWIs from C Code
Previous sp_svc
Assembly code produced by compiler
void C_SWI_handler(unsigned
g number,
, spsr_svc User-Level C Source Code
unsigned *regs) lr_svc readline
regs[12] r12 char __swi(4) SWI_ReadC(void); STMDF sp!,{lr}
{ r11 MOV lr, a1
switch (number){ r10
void readline (char *buffer) readagain
case 0: r9 { SWI 0x4
r8 char ch; STRB a1,[lr],#1
/* SWI number 0 code */ CMP a1,0xd
r7 do {
value_in_reg
g_0 = reg[0];
g r6 BNE readagain
*buffer++ = ch= SWI_ReadC();} MOV a1,#0
reg[0] = updated_value_0; r5
STRB a1, [lr, #0]
break; r4 while (ch != 13);
LDMIA sp!, {pc}
r3 *buffer = 0;
…… r2
2
} /* end switch */ r1 } /* end readline() */
sp_svc r0
} /* end C_SWI_handler() */

10/3/2007 CS5272 © 2007 Tulika Mitra 45 10/3/2007 CS5272 © 2007 Tulika Mitra 46

S
Summary
r
‡ Memory mapped I/O
Memory-mapped
‡ Interrupt and Exceptions
‡ Interrupt
Interrupt-driven
driven I/O
‡ Software Interrupt (SWI)

10/3/2007 CS5272 © 2007 Tulika Mitra 47