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Fuji Electric Journal Vol.75 No.

8, 2002

Multi-series Connection of
High-Voltage IGBTs
Yasushi Abe
Koji Maruyama

1. Introduction Fig.1. Charge/discharge snubber circuit

Since power conversion equipment used by power systems,
industrial plants, and electric railways have large capacities Charge/discharge
snubber circuit
and operate at high voltages, devices such as the thyristor
and GTO (Gate Turn-Off) thyristor have traditionally been
used. On the other hand, for medium- to small-capacity
conversion equipment such as the general-purpose inverters, IGBT
the IGBT (Insulated Gate Bipolar Transistor) is widely used
to obtain a higher performance. The next step, which is
gaining importance, is to use the IGBT to the applications
where voltage is higher and capacity larger. Although Fuji
Electric has already marketed a press pack IGBT (2.5 kV/
1.8 kA) featuring a high withstand voltage and a large current,
a series-parallel connection technique for IGBTs that enables Fig.2. Device voltage waveforms at turn-off (for two devices
operation at higher voltages is required to expand the uses of connected in series)
IGBT conversion equipment.

Spike Voltage slew rate reduction

In these circumstances, Fuji Electric is working to develop voltage
technique that connects multiple IGBTs in series. Device voltage with earlier off timing

This paper focuses on the principle of operation of voltage

balance control technique in series connected devices,
simulation analysis, and test results.
Device voltage
Switching timing difference imbalance reduction
2. Series Connection
Without charge/discharge With charge/discharge
2.1 Problems with Series Connection and Conventional snubber circuit snubber circuit
A major problem occurring when devices are connected in
series is that if a difference in switching timing occurs among
the devices, the voltage of each device will not be balanced, 2.2 Device Voltage Balance Circuit System
placing too much of a burden for voltage on specific devices. This section explains Fuji Electric's unique method for
Because the switching speed of IGBTs is faster than that of solving the problem described above. The solution is a
other power devices, there is a tendency for the imbalanced simple circuit. In Fuji Electric's method, the gate wires of
device voltage to increase. In particular, during turn-off, the IGBTs connected in series are coupled magnetically by a
transient voltage generated by interrupting the current is core (referred to hereafter as the gate balance core) to
superimposed on the main circuit voltage, increasing the synchronize the timing of the gate current that flows during
possibility of device damage. Controlling the balance of switching. The result is that the device voltage can be
device voltage is therefore a very important task when IGBTs balanced.
are connected in series.

Generally, a charge/discharge snubber circuit is connected

to each device, as shown in Figure 1, as an effective way to
solve this problem. The snubber circuit consists of
capacitors, diodes, and resistors. Because the voltage slew
rate at turn-off can be lowered, as shown in Figure 2, the
device voltage imbalance can be reduced. However, if the
snubber circuit is used in a high-voltage equipment, it needs
to be more complex and larger, which also increases losses.

Fuji Electric Journal Vol.75 No.8, 2002

Figure 3 shows the circuit configuration of two series Fig.4. Timing chart
connected IGBTs. The gate balance core is made up of a
secondary winding with a turn ratio of 1:1.
Off On Off
V i1 0
As shown in Figure 3, the gate balance core is inserted by
Off On Off
connecting each winding to the gate wire of the devices in V i2 0
series. As a result, the gate wire of each series connected V g1 V g1 V g2 V g1 V g2
device is magnetically coupled. V g2 0

Fig.3. Device voltage balance circuit system I g2

I g1 T (off)
I g1
IGBT I g2 0 T (on)
I g1 I g2
Gate balance core T g V CE1
GDU1 I g1 V CE1
Rd1 V CE2
Input signal V i1 V CE1
V g1
V T1 V CE2 0
Gate drive circuit With gate balance core Without gate balance core
GDU2 I g2 Rd2
G V T2
Input signal V i2
V g2
2.3 Operation Analysis by Simulation
IC To verify the principle of operation described above, we
conducted a simulation analysis of the circuit in Figure 3.
We used a two-dimensional simulator, ISE-TCAD (ISE AG),
which can perform a coupled simulation of devices and
The following explains the principle of operation of this circuit. circuits.
Figure 4 shows a timing chart. We assume that there is a
timing difference between the input signals Vi1 and Vi2 of Q1 Figure 5 shows the results of simulating the turn-off operation.
and Q2, and that Vi1 is T(on) faster at turn-on and T(off) faster As the device model, we used a Fuji Electric 2.5kV press
at turn-off than Vi2. If there is no gate balance core Tg under pack IGBT. We also assumed that Q1 was 200ns faster
these conditions, the gate current and gate output voltage than Q2. From the simulation results, we can confirm that
(Ig1 and Vg1) of Q1 are T(on) at turn-on or T(off) at turn-off the imbalance of device voltage can be controlled by
faster than Ig2 and Vg2 of Q2, as shown in Figure 4 (it is connecting a gate balance core.
assumed that the signal transfer time of the gate drive circuit
GDU1 and that of GDU2 are the same). Because Q2 is in Fig.5. Simulation results
the off state during T(on) at turn-on, the device voltage VCE2
increases (indicated by the broken line). This voltage 4,000
increase is equal to the drop of VCE1. When T(on) passes,
Q2 is turned on at Ta and the voltage drops, settled to a
steady state. In the same manner, because Q2 is in the on Device voltage (V) 2,000 IC
Device current (A)
state during T(off) at turn-off, the device voltage VCE1 of Q1
1,000 V CE2
that is cut off earlier increases, creating an imbalance 500 ns
between VCE1 and VCE2 (indicated by the broken line). 0
When T(off) passes, Q2 is turned off at Tb and the (a) Without gate balance core
unbalanced voltage converges to the normal voltage. 4,000

Next is explained the operation when a gate balance core Tg 3,000

exists. If Q1 first enters the on state during T(on) at turn-on, Device voltage (V) 2,000 IC
Device current (A) V CE1, V CE2
the gate current Ig1 starts to flow before all other currents.
However, this action causes a voltage difference between 1,000
500 ns
gate drive circuits, generating a positive voltage at VT1 of the 0
gate balance core and a negative voltage at VT2. That is, a (b) With gate balance core
voltage is generated to decrease Ig1 and to increase Ig2 so
that Ig1 = Ig2 can be expected, as indicated by the solid line in
Figure 4. This action synchronizes the gate timing. Using
a similar principle, if Q1 is first turned off, a negative voltage 2.4 Prototype of the IGBT Multiseries Connected Stack
is generated at VT1 and a positive voltage at VT2. A voltage To apply the principle of operation of the gate balance core
that increases Ig1 and decreases Ig2 is generated, and Ig1 = Ig2 explained above to conversion equipment, we built a
is also achieved after turn-off. prototype stack by connecting four IGBTs in series . We
used Fuji Electric 2.5kV/1.8kA press pack IGBTs. Like a
thyristor, this IGBT has a pressure contact structure, which is
appropriate for a series connection.

Fuji Electric Journal Vol.75 No.8, 2002

Figure 6 shows the gate balance core and the gate drive Fig.7. Stack and circuit configuration
circuit peripheral. The gate balance core is contained in the
Gate drive circuit IGBT Cooling fin
gate drive circuit.

Figure 7 shows the complete stack and the circuit

configuration. This circuit configures one phase of the
2-level inverter and has a structure in which voltage is
applied by sandwiching eight IGBTs of the upper and lower
arms between the cooling fins, which are water-cooled.

Q11 - Q14 and Q21 - Q24 in the figure are IGBTs, GDU11 -
GDU14 and GDU21 - GDU24 are gate drive circuits, R11 - R14
and R21 - R24 are voltage dividing resistors, and Tg11 - Tg14 (a) Complete stack
and Tg21 - Tg24 are gate balance cores. When the gate Gate balance core
balance cores are connected as shown in the figure, all gate GDU11 I g1 Tg11 Q11
R11 V CE(Q11)
wires of the IGBTs that are connected in series are coupled
magnetically. GDU12 I g2 Tg12 Q12
R12 V CE(Q12)
Fig.6. Gate balance core and gate drive circuit peripheral
GDU13 Tg13 I g3
R13 V CE(Q13)

GDU14 I g4 Q14
29.5 R14 V CE(Q14)

29.4 Q21
26.5 GDU21 Tg21
R21 V CE(Q21)
(Unit: mm)
(a) Gate balance core Q22
GDU22 Tg22
R22 V CE(Q22)
Gate drive circuit IGBT Cooling fin
GDU23 Tg23
R23 V CE(Q23)

R24 V CE(Q24)

DC voltage Ed = 4,000 (V), collector current Ic = 1,000 (A)

Q11 - Q24: 2.5kV/1.8kA press pack IGBT (manufactured by Fuji Electric)
(b) Circuit configuration

(b) Gate drive circuit peripheral Fig.8. Gate current measurement results

2.5 Prototype Test Results

We performed a turn-off test using a stack that was created
by connecting four IGBTs in series (see Figure 7). The test
conditions were a DC voltage of 4,000V, a breaking current 0
of 1,000A, and the upper arm (Q11 - Q14) was used to
interrupt the current. We also put forward the switching I g2, I g3, I g4
timing of Q11 by 200ns with respect to the three other I g1
devices. 1 s

We first measured the gate current timing with and without (a) Without gate balance core
gate balance cores to verify the gate current balance effect of
the gate balance core. Figure 8 shows the measurement
results. When there was no gate balance core, the gate
current Ig1 of Q11 started to flow 200ns earlier than the other
gate currents. However, as the figure makes clear, when I g1, I g2, I g3, I g4
gate balance cores were connected, the gate currents of the
four devices started to flow at the same time.

1 s

(b) With gate balance core

Fuji Electric Journal Vol.75 No.8, 2002

We then measured the device voltage to verify that balancing Fig.9. Element voltage balance measurement results
the gate current timing can have an effect on the element
voltage sharing balance. Figure 9 shows the element
voltage waveforms of Q11 and Q12.
It is clear from the figure that if no gate balance core exists,
the device voltage VCE (Q11) of Q11 that is turned off earlier
increases more than the device voltages of the other devices.
V CE(Q11)
However, when connecting gate balance cores are
connected, the device voltage can be equalized.
V CE(Q12)

3. Conclusion 0
1 s
This paper presents a technique that enables the series
connection of multiple high-voltage IGBTs. To promote the (a) Without gate balance core
miniaturization and improved performance of high-voltage
power conversion equipment such as those used in power
systems and industrial plants, we intend to continue working
on the development of high-voltage technology, which
includes series connection technology.

IC V CE(Q11), V CE(Q12)
(1) Eguchi, N. et al. Constituent Technologies Supporting Power
Electronics for Power and Industries. Fuji Review vol. 74,
no. 5, 2001. pp. 265-272
1 s
(2) Abe, Y. et al. Improving Element Voltage Balance for IGBTs
Connected in Series. National Symposium of the Institute of (b) With gate balance core
Electrical Engineers in 2001, 4-002, 2001

Commentary Noise terminal voltage

The noise terminal voltage is also called conduction noise.
It is a kind of wave causing electromagnetic interference
that propagate to the power wire of electronic equipment
in frequency bands at 30MHz and below, and can cause a 90
failure. The noise (that is, the magnitude of the A
interference) can be assessed by measuring the voltage 80
generated in the power wire. Noise 70
terminal B
The limit value of the noise terminal voltage is prescribed (dB V) 60
by CISPR Pub.22, which is an international standard. As 50
shown in the figure, CISPR Pub.22 is prescribed for each
frequency band in the bands from 150kHz to 30MHz. 40 A : CISPR Pub.22 Class A
B : CISPR Pub.22 Class B
Switching power units mounted in information technology 30
equipment such as PC monitors and adapters used at 100 1,000 10,000 100,000
Frequency (kHz)
home must meet CISPR Pub. 22 Class B requirements.
Class A requirements apply to equipment used in
commercial and industrial areas.