FIRST ASIA INSTITUTE OF TECHNOLOGY AND HUMANITIES

#2 Pres. Laurel Highway, Darasa, Tanauan City, Batangas, Philippines

Laboratory 09: Logical Effort d) Edit the block similar to the symbol for NAND gate. Right click the block, select
Edit symbol/title block and the Symbol Editor window appear. After editing,
Objectives: save the edit symbol (Ctrl + s) then close the Symbol Editor windows.
In this laboratory, you will be able to:
Create symbols for logic gates in NI Multisim.
Optimize the delay of a path by sizing the gates.
Apply different techniques to minimize the delay.

Activity 1: Symbols for logic gates

a) Create a 5-input CMOS NAND gate without sizing. Place a hierarchical connector
located at Place>Connectors> hierarchical connector (Shortcut Ctrl + I). Set e) Test the NAND5 using transient analysis from 0 to 20ns. The output should be
Input as direction for input signals and Output direction for output signal. Save inverted.
your work and name it NAND5.ms12

f) Also, create a circuits for inverter (INV.ms12) and 3-input NOR (NOR3.ms12).

b) Test the functionality of 5-input CMOS NAND gate. Open new file. Save and name Activity 2: Sizing the Gates to Optimize the Path
it TEST_NAND5.ms12.
a) Shown in the table below are the sizes of the NMOS and PMOS transistors of the
c) Now, place the NAND5 circuit on this sheet. Click Place>Hierarchical block from unit gates. Complete the table by filling out the logical effort values in the last
file and open NAND5.ms12. A block is created automatically that represent the column.
circuit from NAND5.ms12.

1
 FIRST ASIA INSTITUTE OF TECHNOLOGY AND HUMANITIES
#2 Pres. Laurel Highway, Darasa, Tanauan City, Batangas, Philippines

Table 1 a) Open new file, save and name it LAB09. Create the circuit of Figure 3.
Gate NMOS PMOS Logical Effort
INV 120 170 1 b) Hierarchically place the gates or Copy and Paste the symbol you have created
NAND5 600 170 7 from activity 1.
3
NOR3 120 510 7
3 c) Size the transistor using the size given in table 1. Run a transient analysis of 40ns
b) Shown below a schematic of path driving a capacitive load. Assume that the
and measure the delay of the path.
capacitive load is 256 times larger than the input capacitance of the first inverter
Rise time = 6.3889 ns
on the chain. You are also not allowed to have additional stages aside from the
one given below. Solve for the sizes of the gates and write them in the blanks Fall Time = 5.7208 ns
provided below. In your solutions, use the logical effort youve solved in the 2.8518+6.9820
previous step. Propagation Delay = = .
2

d) Simulate again but this time size the transistor equal from the table 2.
Rise time = 682.120 ps
Fall Time = 567.9902 ps
346.9176+372.5945
Propagation Delay = = .
2
INV = 1 NAND = 11.1702 NOR = 53.4752

Figure 3
Question:
1. What are your observations from the result of rise/fall time and delay?
c) Given the sizes of the gates that youve solved from the previous question, solve Explain
for the transistor sizes of the stages. Complete the table below.
From the results gathered in the simulation, it can be observed that
the delay was decreased by increasing the width of the transistors. By
GATE NMOS PMOS computing the gate sizes of the unsized transistors, an improved
INVERTER 120nm 170nm version of sizes was made. Since the width is increased, power will also
NAND5 1.04um 296.48nm increase. Thus, Logical Effort does not emphasize power relationships
NOR3 1.22um 5.20um of the system but focuses on delay improvement. Also, the load
capacitance has effect on the speed of the circuit. When load is
increased, the delay observed is larger. For this experiment, Cin used is
3.07fF.

Members:
Activity 3: Simulation Punzalan, Justine Roy A.
Quiatchon, Bien Paolo C.