2292 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO.

10, OCTOBER 2012

A Simple Circuit Approach to Reduce Delay

Variations in Domino Logic Gates
Gaetano Palumbo, Fellow, IEEE, Melita Pennisi, Member, IEEE, and Massimo Alioto, Senior Member, IEEE

AbstractIn this paper, a simple approach to reduce delay

variations in domino logic gates is proposed. Previous analysis
by the same authors showed that delay variations in domino
logic are mainly due to the feedback loop implemented by the
keeper transistor and the output inverter gate. Accordingly, the
proposed strategy aims at reducing the loop gain associated with
this feedback loop, and hence its impact on delay variations. In
particular, a simple modified keeper is proposed to reduce the
loop gain while keeping the same silicon area, noise margin, and
nominal performance. The resulting delay variations associated
with keeper insertion are shown to be lowered by approximately
50%. The proposed approach is assessed by means of simulations
in 65-nm and 90-nm commercial CMOS technologies.
Index TermsIntradie variations, process variations, timing
Fig. 1. Schematic of a Domino logic gate.
modeling, variability, VLSI.

the power supply and the dynamic node , when the latter has
to be kept high [10], [11].
I. INTRODUCTION
In nanometer technologies, intradie process variations deter-
mine large delay variations that are a timing overhead that limits
the performance improvements potentially offered by Domino

V ARIABILITY issues pose a major challenge in

nanometer integrated circuits (ICs) [1][3]. Indeed, espe-
cially in high-performance applications, the large delay/power
deviations due to process and environmental variations make it
difficult to meet the tight bounds imposed by performance and
consumption requirements, thereby degrading the yield [4][9].
In performance-critical applications, Domino logic is widely
employed since it has a lower delay at the cost of a reduced noise
immunity, compared with static CMOS logic [10], [11]. The
speed advantage of Domino logic is obtained thanks to the more
compact circuit topology (the pull-up network is much simpler
than CMOS logic). This speed advantage becomes more pro-
nounced when considering wide fan-in gates. As an example,
fast OR gates and MUXes with wide fan-in are typically used
to realize high-performance register files [12][14].
To counteract the noise immunity and signal integrity degra-
dation observed in Domino logic, the dynamic node is typi-
cally connected to a keeper PMOS transistor ( in Fig. 1).
During the evaluation phase, provides a static path between
Manuscript received February 18, 2011; revised September 05, 2011; ac-
cepted January 15, 2012. Date of publication May 04, 2012; date of current
version September 25, 2012. This paper was recommended by Associate Editor
S. Cotofana.
G. Palumbo and M. Pennisi are with the DIEES (Dipartimento di Ingegneria
Elettrica, Elettronica e dei Sistemi), Universit di Catania, I-95125, Catania,
Italy (e-mail: gpalumbo@diees.unict.it; mpennisi@diees.unict.it).
M. Alioto is with the DII (Dipartimento di Ingegneria dellInformazione),
Universit di Siena, I-53100, Siena, Italy, and also with the EECS Department,
the University of Michigan, Ann Arbor, MI 48109 USA (e-mail: malioto@dii.
unisi.it; alioto@umich.edu).
Digital Object Identifier 10.1109/TCSI.2012.2189046
logic [15][23]. Since intradie process variations are expected
to rapidly increase in the next technology generations, and con-
sidering that they are very difficult to compensate with adaptive
schemes, they are regarded as the most critical source of vari-
ability and a major limit to performance in nanometer technolo-
gies [21].
Recently, the effect of process variations on the delay of dy-
namic logic was investigated at the circuit level of abstraction
by the same authors [24]. The analysis showed that the delay
variability of Domino logic gates is typically doubled compared
to that of the static logic counterparts. In the same paper it was
shown that [24]:
the variability of the delay at the dynamic node (i.e., from
the input to node in Fig. 1) is almost the same as the
overall delay variability (i.e., from the input to node OUT
in Fig. 1);
variations in the keeper transistor and the precharge tran-
sistor do not significantly contribute to the delay variability
at the dynamic node .
Thus, the only remaining cause of variability increase compared
to static CMOS logic is the positive feedback loop that is imple-
mented by the keeper transistor and the output inverter in Fig. 1
[24]. Furthermore, the delay variability degradation associated
with the feedback loop tends to get worse in more advanced
technologies (see Section II for the details). Hence, it must be
necessarily mitigated to avoid unmanageable delay variations in
current and next technology generations.
In regard to the trade-off between noise margin and perfor-
mance, a strong keeper improves the former but degrades the
latter, due to the stronger current contention with pull-down

1549-8328/$31.00 2012 IEEE

PALUMBO et al.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES
network. Clearly, this trade-off becomes hard to manage in the
presence of variations, hence various circuit solutions have been
proposed to limit their impact [14], [25][28]. More specifi-
cally, approaches in [14], [25] and [26] temporarily reduce the
noise margin for a portion of the clock cycle. The approach in
[27] proposes a replica bias technique that can counteract varia-
tions that are fully correlated in both NMOS and PMOS transis-
tors (i.e., layout-dependent variations), whereas it is ineffective
against random variability components (e.g., random dopant
fluctuations) or variations that affect NMOS and PMOS tran-
sistors in different ways. The scheme proposed in [28] compen-
sates only fully correlated variations through a keeper with digi-
tally programmable strength, which suffers from heavy loading
of the dynamic node and its large overhead is justified only if
this approach is adopted in large structures like register files.
All the above approaches are based on the simple principle
that delay variations can be reduced by appropriately tuning the
keeper strength. On the other hand, in this paper a completely
different principle is exploited to reduce delay variations in
Domino circuits. Rather, this work aims to reduce the delay
sensitivity to process variations by reducing the loop gain, as
justified by the above considerations on the positive feedback
loop implemented by the keeper [24]. In particular, a simple
keeper topology that replaces the standard PMOS keeper is
adopted to reduce delay variations while keeping the same
silicon area, delay and noise margin. Also, in the proposed
technique, the noise margin is constantly kept to the targeted
value without any temporary degradation, in contrast to [14],
[25], [26]. Interestingly, thanks to the different principle and
goal, the proposed technique can be mixed with any of the
alternative techniques in [14], [25][28] by simply replacing
the PMOS keeper with the proposed structure. Hence, the
proposed technique can actually be complementary to such
techniques, rather than being purely a competitor.
The paper is organized as follows. In Section II, a detailed
analysis of delay variation in a Domino logic gate is carried
out. The proposed keeper topology to reduce delay variations
is discussed in Section III along with design guidelines. Monte
Carlo simulations in 65-nm and 90-nm CMOS technology are
reported in Section IV to validate the proposed approach. Con-
clusions of the work are summarized in Section V. Two appen-
dices are added to improve the readability of the paper.
II. ANALYSIS OF DELAY VARIATIONS IN DOMINO LOGIC
A. Assumptions and Constraints on the Transistor Sizes
The generic Domino logic gate in Fig. 1 consists of an NMOS
pull-down network (PDN) inserted between the precharge tran-
sistor and the evaluation transistor . The dynamic
node at the output of the PDN drives the static output inverter.
At the beginning of the evaluation phase (i.e., when goes
high), node is kept at the voltage by the keeper tran-
sistor . When a transient noise is observed at node , the
keeper rejects it by bringing the voltage of back to [3].
With regard to the size of the keeper, the adoption of a
stronger keeper obviously permits a better noise immunity. On
the other hand, a stronger keeper also opposes to transitions
2293
Fig. 2. Test circuit to evaluate delay variability for the traditional Domino.
of determined by the PDN in Fig. 1, thereby increasing
the gate delay [3]. This is the well-known trade-off between
noise immunity and speed in Domino logic, which basically
depends on the ratio between the saturation current of
the keeper and that of the PDN. To avoid an excessive delay
increase, must be kept lower than unity, and typically
ranges from 0.1 to 0.5 [29] (i.e., the keeper saturation current is
from 10% to 50% of the on current of the PDN).
The output inverter must be high skewed to minimize the
delay, typically with the PMOS transistor sized four times wider
than the NMOS [30]. On the other hand, the size of the eval-
uation transistor is chosen according to the trade-off between
the clock load specification (i.e., a size smaller than PDN tran-
sistors) and the speed requirement, and is reasonably sized 1.5
times larger than the equivalent width of the PDN [30].
B. Analysis of the Impact of Intradie Variations and Discussion
on the Role of the Positive Feedback Loop
Let us analyze the impact of the intradie variations on the
speed of Domino gates with different fan-in (i.e., an inverter, a
NAND, and a NOR with fan-in equal to [2], [3], [4] and [2],
[3], [4], [8], [16], [32], respectively) designed by using a 65-nm
CMOS technology. Moreover, some results by using a 90-nm
technology are reported in Appendix I to enable comparison
between different technologies.
To correctly evaluate the delay variations, an appropriate sim-
ulation setup is adopted. In particular, the circuit shown in Fig. 2
is used, where the circuit under test is driven by a realistic input
waveform generated by an equal gate, although the latter is not
subject to any process variation (so that the input rise time of
the circuit under test is not subject to significant variations).
The circuit under test is loaded by a capacitance that is set
to some multiple of the input capacitance of a min-
imum-sized inverter ( quantifies the load indepen-
dently of technology). In particular, results equal to
410 aF in 65-nm technology.
The results, obtained with 2000 runs1 of Monte Carlo simu-
lations in 65-nm CMOS are summarized in Tables IIII, which
respectively report the mean value , standard deviation
and the resulting variability of the delay. In these tables,
the load capacitance is set to and , the
equivalent aspect ratio of the PDN is set to the realistic value
/60 nm, and is minimum sized. Also,
the keeper is sized to achieve a of 0.1 (a wider
range for will be considered in Section IV), and the
1This number of runs ensures a lower than 4% inaccuracy in the standard
deviation estimate.
2294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012
TABLE I
DELAY MEAN VALUE IN DOMINO LOGIC WITH/WITHOUT STANDARD KEEPER
AND KEEPER IN FIG. 4 (65-nm TECHNOLOGY, IN
BRACKETS: PERCENTAGE INCREASE W.R.T. THE CASE WITHOUT KEEPER)
TABLE II
DELAY STANDARD DEVIATION IN DOMINO LOGIC WITH/WITHOUT STANDARD
KEEPER AND KEEPER IN FIG. 4 (65-nm TECHNOLOGY, IN
BRACKETS: PERCENTAGE INCREASE W.R.T. THE CASE WITHOUT KEEPER)
high-skewed static inverter is sized by using the logical effort
approach for each load condition.
From inspection of Tables I, II, the mean value tends to in-
crease faster than the standard deviation when increasing the
fan-in at a given load. Thus, the delay variability tends to
TABLE III
DELAY MEAN VALUE, STANDARD DEVIATION AND VARIABILITY IN
DOMINO GATES WITH STANDARD KEEPER IN FIG. 1 (65-nm TECHNOLOGY,
)
decrease when increasing the fan-in, as shown in Table III. Fur-
thermore, the delay variability decreases when increasing ,
due to the increase in the mean value (the standard deviation
increases only slightly). As expected, the delay variability also
increases when considering a more advanced technology, as is
confirmed by the comparison with results in 90-nm technology
summarized in Appendix I.
As clarified by the authors in [24], the above delay varia-
tions are due to two main factors: one is the process variability
within the PDN in Fig. 1, the other is related to the presence
of the positive feedback loop implemented by the keeper and
the inverter gate. In particular, the feedback loop in Fig. 1 is
responsible for an increase in the delay variations even when
transistors in the loop (i.e., keeper and inverter transistors) are
not subject to variations. To quantitatively evaluate the impact
of the feedback loop on the delay variations, let us analyze the
results in Tables I, II, where the mean value and the standard
deviation of the delay are reported for the above considered
logic gates with and without the keeper (i.e., with/without the
feedback loop). In these tables, data in bold font and brackets
refer to the percentage increase with respect to the case without
keeper. From Table I, the keeper insertion determines a mod-
erate increase in the mean value of the gate delay, compared
to the case without keeper, due to the current contention with
the pull-down network. On the other hand, from Table II, the
keeper insertion determines a strong increase in the delay stan-
dard deviation , compared to the case without keeper.2
From the above considerations, it is clear that the impact
of the feedback loop on the delay variability is significant
in sub-100 nm technologies, and also tends to increase in
down-scaled technologies. In turn, this means that the speed
degradation of Domino due to delay variations tends to grow
faster than static CMOS logic (whose delay variations are basi-
cally the same as Domino logic variations due to the only PDN,
without the effect of keeper [24]). Hence, the feedback loop in
Domino gates tends to reduce their speed improvement over
static logic, thereby making Domino logic less advantageous in
down-scaled technologies.
2In Table III, the reduced variability in logic gates with higher fan-in is easily
understood by considering that a larger number of stacked transistors permits to
average out the transistor variations [18], [21].
PALUMBO et al.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES 2295

above. Equivalently, becomes rather sensitive to varia-

tions when , for a given change in the input voltage. In
turn, the current determines the voltage drop at the dy-
namic node and hence the delay at the same node. Hence, when
the delay becomes rather sensitive to process variations.
On the other hand, when as in the case of Domino logic
without keeper, the delay variability is reduced and becomes
equal to that of static CMOS gates.
Summarizing, the Domino delay variability increase due to
the presence of the keeper (i.e., feedback loop) can be lowered
by reducing the loop gain. In the following section, a circuit ap-
proach to reduce the loop gain without impacting other param-
eters of interest is discussed.

III. A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY

Fig. 3. Simplified schematic of a Domino logic gate. VARIATIONS IN DOMINO LOGIC GATES
From (1), the magnitude of the loop gain can be reduced
C. Circuit Analysis of the Positive Feedback Loop by reducing either the voltage gain of the inverter , or the
impedance or the keeper transconductance .
Let us analyze the small-signal loop gain of the circuit in In the following, we discuss an approach that aims at reducing
Fig. 1, whose simplified scheme is reported in Fig. 3. The PDN the latter.
in Fig. 3 (including the evaluation transistor) is represented with
an independent current source , whereas the keeper is A. Keeper Topology to Reduce the Impact of Process
represented as a dependent current source , which is Variations
controlled by the output small-signal voltage . In turn, the
small-signal component of current can be written A simple approach to modify the keeper and reduce its small-
as , being signal transconductance while keeping the same
the keeper transconductance. The resulting small-signal voltage strength is shown in Fig. 4. As no change is made in the strength,
at the dynamic node can be written as , being the circuit in Fig. 4 does not have any penalty in terms of noise
the impedance at the dynamic node (which is determined margin and speed, compared to the standard keeper in Fig. 1. In
by transistor parasitics), and the current detail, the improved keeper is realized by splitting the original
flowing through . For the case of interest, the transistor keeper transistor into two transistors and
voltage at node decreases from the precharged value , , where only is driven by the inverter output. In-
hence . stead, transistor works as an equivalent resistance
From inspection of Fig. 1, the feedback associated with the
keeper transistor has a noninverting loop gain given by
(2)
(1)
that represents a source degeneration for the transistor .
where is the voltage gain of the inverter, which is obvi- Hence, naming the transconductance of , the
ously lower than one3 at the beginning of the evaluation phase effective transconductance of the keeper is immediately found
(i.e., when the voltage at node is ). At the same time, to be
the keeper transconductance at the beginning of the evaluation
phase is small as well, as the keeper operates in the linear region. (3)
Due to the low value of and of the gain
, the loop gain is positive but certainly lower than one at the
beginning of the evaluation phase. From basic circuit theory, a Apparently, compared to the standard keeper topology in Fig. 1
feedback circuit with a loop gain has a closed-loop gain sen- without , and hence the loop gain is reduced by a
sitivity to variations equal to [31], [32]. Hence, the factor of , as desired.
lower-than-one and positive feedback loop gain in Domino
gates increases the gain sensitivity to variations when , B. Transistor Sizing Strategy
compared to the case without keeper (i.e., in open loop con- From a design perspective, the above technique makes sense
figuration). In particular, let us consider the closed-loop gain only if the loop gain reduction is obtained by keeping the same
between the input voltage and the current , which be- noise margin as the gate with the original keeper, since it is a crit-
comes very sensitive to variations when , as discussed ical specification in Domino logic gates. To this aim, we have to
3 becomes rather high only around bias points where the voltage of size and so that they provide the same DC current
node are close to the inverter logic threshold. as the original keeper (i.e., they have to set an equal
2296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012
Fig. 4. Keeper topology to reduce delay variations.
ratio). Since these transistors are in series, this condition is met
by setting the aspect ratio of and according to
Since the keeper usually has a rather small driving capability, its
transistor width is customarily set to the minimum value
allowed by the technology, whereas its length is
greater than minimum. Thus, in the gate with modified keeper,
transistors and are sized with
and . same for both types of keeper with a difference of just a few
Now, we still have another degree of freedom in the
and sizes that can be used to keep the loop gain in
(1) as low as possible, or equivalently to keep
as high as possible from (3). Since is propor-
tional to , we have to set4 and
. This sizing criterion combined with (4)
permits to reduce the loop gain while maintaining the same
ratio, thereby avoiding any penalty in terms of noise
margin and performance.
It is worth noting that the considered keeper is very similar
to the keeper based on a single transistor, and its layout is very
simple, since it is the series of two transistors with minimum
width. As the overall length is the same as the
channel length of the original keeper, the increment in the
silicon area is negligible.
IV. DESIGN CONSIDERATIONS, SIMULATIONS, AND VALIDATION
To assess the reduction in the delay variations offered by the
above discussed keeper topology, Domino logic gates were sim-
ulated according to the test circuit in Fig. 2 and under the same
conditions as in Section II for the 65-nm technology (results on
the most critical gates for the 90-nm CMOS technologies are re-
ported in Table VII of Appendix I). The same sizes were kept for
all transistors except for the keeper, which was sized according
to the design strategy in Section III.
4This clearly holds in practical cases where . In the
uncommon case where , it is easily found that we
must set , and
in order to satisfy (4) and maximize
TABLE IV
DELAY VARIABILITY IN DOMINO GATES WITH KEEPER IN FIG. 4
(65-nm TECHNOLOGY, )
First, we considered Domino logic gates with
assigned to 0.1, which is in the low side of the typical
range and leads to a noise margin ranging from 300 to 350
mV for all logic gates and the standard keeper in Fig. 1.
As an example, a noise margin of 340 mV for the inverter
(4) and 300 mV for the NAND3 gate were obtained with
the appropriate sizes of the keeper in Fig. 4 that leads to
(i.e., ,
for the keeper in Fig. 4,
and for the standard keeper
in Fig. 1). As expected from the considerations in Section III,
the nominal noise margin was confirmed to be consistently the
percentage points (the small difference is due to the approxi-
mations that are customarily introduced in the transistor sizes).
Interestingly, the keeper in Fig. 4 was also found to keep the
same noise margin variability as the traditional keeper, for the
reasons discussed in Appendix II. This means that the proposed
keeper does not introduce any penalty in terms of noise margin,
even when variations are accounted for. Also, this ensures that
all comparisons presented in the following are fairly performed
at same noise margin, even in the presence of variations.
Monte Carlo simulations with 2000 samples were carried
out to evaluate the mean value and the standard deviation of
the delay for the proposed keeper, whose numerical values are
reported in Tables III. The variability resulting from these
simulations is reported in Table IV. Monte Carlo simulations
accounted for the variation in the threshold voltage, mobility,
gate oxide thickness, source/drain resistance and channel di-
mensions.
From the simulation results in Table II, the mean value of the
delay is basically the same for both the standard keeper in
Fig. 1 and the proposed keeper in Fig. 4 (again, the small dif-
ference is due to the usual approximations in transistor sizes).
This means that the proposed keeper does not introduce any sig-
nificant speed penalty at nominal conditions, as expected. The
same observation was confirmed to hold for the noise margin
variability, which was found to be the same for both keepers, as
expected from the considerations in Appendix II.
In regard to the delay variability, the delay standard devi-
ation and variability with the proposed keeper (see Table IV)
are consistently lower than those with the standard keeper (see
. Table III) for all logic gates, as expected. This is especially true
PALUMBO et al.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES
Fig. 5. Percentage increase of delay standard deviation of standard/proposed
keeper w.r.t. case with no keeper vs. ( , 65-nm tech-
nology): (a) inverter and NAND; (b) NOR.
in low fan-in gates and in the case of low capacitive load. This is
clear from the data in brackets in Table II, which shows that the
delay variability increase due to the insertion of the proposed
keeper is almost half that obtained with the standard keeper
in Fig. 1, compared to the case without keeper. This means
that the keeper topology in Fig. 4 under the sizing strategy in
Section III-B is effective in reducing the delay variability in-
crease associated with the feedback loop. Similar results are re-
ported in Appendix I under a 90-nm technology.
Although the above results were obtained assuming
, they hold also for different values of . proposed keeper was found again to be typically 50% lower than
To show the influence of a different (i.e., keeper
strenght), the same Domino logic gates were also designed
and simulated with widely ranging from 0.1 to 0.5. In
regard to the mean value of the delay, a higher value of
leads to a higher delay because of the increased current con-
tention with the pull-down network. For example, all the gates
loaded with were found to be slowed
down by 1 ps (4 ps) and 2 ps (8 ps) for and
, compared to the case with . As
already observed for , simulations confirmed
that the proposed keeper does not introduce any speed and
noise margin penalty at nominal conditions, regardless of the
adopted . on average) the standard deviation increase due to the keeper
In regard to the delay standard deviation, its percentage in-
crease due to the insertion of the keeper with respect to the
case without keeper is plotted in Fig. 5 (Fig. 6) versus
for . As a first comment
on Figs. 56, the delay variation always increases for all logic
2297
Fig. 6. Percentage increase of delay standard deviation of standard/proposed
keeper w.r.t. case with no keeper vs. ( , 65-nm
technology): (a) inverter and NAND; (b) NOR.
gates when a stronger keeper (i.e., higher ) is adopted,
regardless of the adopted keeper. This is because a stronger
keeper has a greater small-signal transconductance, hence the
loop gain increases and hence delay variations are more pro-
nounced (as clarified in Section III). Again, the proposed keeper
offers a considerable delay variability reduction over the stan-
dard keeper, regardless of the value of . More quantita-
tively, the delay variability increase due to the insertion of the
that obtained with the standard keeper in Fig. 1. This confirms
that the considerable advantages of the proposed keeper are kept
regardless of the adopted value of .
The improvement in delay standard deviation that is enabled
by the proposed keeper is clearly maintained in practical circuits
built with cascaded gates. Indeed, the delay standard deviation
of an -stage path approximately scales proportionally to
[4], [21]. As an example, Fig. 7 shows the percentage standard
deviation increase with respect to the case with no keeper in
a sample 6-stage path. The results for both the standard and
the proposed keeper are shown for the output of each stage. As
expected, the proposed keeper significantly reduces (by 35%
insertion.
V. CONCLUSIONS
As was recently shown by the same authors, Domino logic
gates suffer from significant increase higher delay variability,
2298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

TABLE V
DELAY MEAN VALUE, STANDARD DEVIATION, AND VARIABILITY IN
DOMINO GATES WITH STANDARD KEEPER IN FIG. 1 (90-nm TECHNOLOGY,
)

TABLE VI
DELAY MEAN VALUE, STANDARD DEVIATION, AND VARIABILITY IN DOMINO
GATES WITH KEEPER IN FIG. 4 (90-nm TECHNOLOGY, )

Fig. 7. Percentage increase of delay standard deviation of standard/proposed

keeper w.r.t. case with no keeper at the output of the various stages in the de-
picted circuit.

compared to static CMOS logic [24]. This is due to the pres-

ence of the keeper transistor and the associated positive feed-
back loop. This delay variability increase becomes more critical
moving toward more advanced technology generations.
In this paper, the loop gain was found to be the critical pa- TABLE VII
rameter that is responsible for this delay variability degrada- DELAY STANDARD DEVIATION IN DOMINO LOGIC WITH/WITHOUT
STANDARD KEEPER IN FIG. 1 AND KEEPER IN FIG. 4 (90-nm TECHNOLOGY,
tion. A keeper topology to reduce the loop gain was introduced )
along with a detailed transistor sizing strategy. The latter per-
mits to minimize the loop gain (and hence delay variations)
while keeping the same keeper strength, and hence the same
noise margin and delay. The resulting area overhead is also in-
significant.
Extensive Monte Carlo simulations in commercial 65-nm and
90-nm CMOS showed that the proposed keeper topology halves
the delay variability increase associated with the keeper inser-
tion. Since Domino logic without keeper essentially experiences
the same delay variability as static CMOS logic, this also means
that the proposed keeper reduces by 50% the delay variability
degradation of Domino logic with respect to static CMOS logic
(i.e., it partially fills the variability gap between the two logic
styles). At the same time, the proposed keeper guarantees the the same simulation setup previously described for the 65-nm
same nominal noise margin and its variability as well, hence the technology.
reduced delay variability is not obtained by penalizing the noise The equivalent aspect ratio of the PDN for all gates is set to
margin. Also, the proposed keeper keeps the same dynamic be- the realistic value , and again the abso-
havior (delay mean value) and silicon area as the Domino logic lute sizes for the NAND2 and NAND3 are multiplied by 2 and 3,
with standard keeper. Due to the increasing importance of vari- compared to the inverter, is minimum sized and the keeper
ability at each new technology generation, the proposed keeper is sized to achieve a of 0.1. Moreover, the high-
is a useful tool to keep variations under control at no penalty in skew static inverter is sized with the NMOS equal to 0.5 /0.1
terms of nominal performance, area, and noise margin. and 2.8 /0.1 for the and load,
respectively. The noise margin for Domino logic with 90-nm
APPENDIX I technology is around 350 mV for the inverter and linearly re-
RESULTS ON A 90-nm TECHNOLOGY duces to 310 mV for the NAND3 gate, which is very close to
In this appendix, some results are reported for the most crit- the design examples that we presented above in 65-nm CMOS.
ical gates realized with a 90-nm technology, for which the input The transistor sizes of the proposed keeper to achieve an equiv-
capacitance of a minimum-sized inverter was found alent aspect ratio of were found
to be 520 aF. Table V and Table VI summarize the mean , to be and
standard deviation and the variability of the delay . Comparison on standard deviation delay be-
obtained with 2000 runs of Monte Carlo simulations for a load tween traditional Domino gates and the proposed topology are
capacitance equal to and , and by using summarized in Table VII.
PALUMBO et al.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES
TABLE VIII
STRENGTH VARIABILITY IN PROPOSED AND TRADITIONAL KEEPER IN A NOR3
GATE (65-nm TECHNOLOGY)
APPENDIX II
NOISE MARGIN VARIABILITY FOR THE PROPOSED KEEPER
Monte Carlo simulations revealed that the noise margin under
the proposed keeper also has the same variability as the tra-
ditional one, as well as the same nominal value. As the noise
margin is set by the keeper strength in a given logic gate, this
means that the proposed and the traditional keeper have the
same strength variability (other than the same nominal value,
by design). This was confirmed by extensive Monte Carlo sim-
ulations. As an example, Table VIII reports the variability of the
keeper strength in a NOR3 gate with nominal equal to
0.1 and 0.5. In this table, the keeper strength has been evaluated
as the on-current of the keeper when with source-gate voltage
equal to (i.e., in Figs. 1 and 4) and source-drain
voltage equal to 50 mV (i.e., ). Appar-
ently, the strength variability of the proposed keeper matches
very well that of the traditional keeper. The same results were
found to hold for all logic gates in all conditions and for dif-
ferent nominal values of . [18] A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and
The fact that the proposed keeper has the same strength (and
hence noise margin) variability as the traditional one can be
intuitively grasped through the following circuit considerations.
On one hand, the presence of the minimum-sized transistor
in Fig. 4 tends to increase the keeper strength variability
because of its small size. On the other hand, this larger vari-
ability of is compensated by the lower variability of the
stacked transistor , since the latter is larger and also tends
to dominate the overall resistance (since it has ).
Apparently, the two effects tend to compensate each other,
thereby justifying why the noise margin variability under the
proposed keeper was found to be consistently the same as the
traditional one in all conditions.
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Gaetano Palumbo (M91SM98F07) was born in
Catania, Italy, in 1964. He received the Laurea de-
gree in electrical engineering and a Ph.D. degree from
the University of Catania, Italy, in 1988 and 1993, re-
spectively.
Since 1993 he has conducted courses on electronic
devices, electronics for digital systems, and basic
electronics. In 1994 he joined the DEES (Dipar-
timento Elettrico Elettronico e Sistemistico), now
DIEES (Dipartimento di Ingegneria Elettrica Elet-
tronica e dei Sistemi), at the University of Catania
as a Researcher, subsequently becoming Associate Professor in 1998. Since
2000 he has been a full Professor in the same department. His primary research
interest has been analog circuits with particular emphasis on feedback circuits,
compensation techniques, current-mode approach, low-voltage circuits. Then,
his research has also embraced digital circuits with emphasis on bipolar and
MOS current-mode digital circuits, adiabatic circuits, and high-performance
building blocks focused on achieving optimum speed within the constraint of
low power operation. In all these fields he is developing some the research
activities in collaboration with STMicroelectronics of Catania. He is the coau-
thor of three books, CMOS Current Amplifiers, Feedback Amplifiers: Theory
and Design, and Model and Design of Bipolar and MOS Current-Mode Logic
(CML, ECL and SCL Digital Circuits), all by Kluwer Academic Publishers,
in 1999, 2001, and 2005, respectively, and a textbook on electronic devices in
2005. He is the author of about 380 scientific papers on referred international
journals (more than 150) and in conferences. Moreover, he is coauthor of
several patents.
Dr. Palumbo he served as an Associate Editor of the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS PART I from June 1999 to the end of 2001 and
from 2004 to 2005 for the topic Analog Circuits and Filters and Digital Cir-
cuits and Systems, respectively. From 2006 to 2007 he served as an Associate
Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. From
2008 to 2011 he served as an Associate Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS PART I. In 2005 he was one of the 12 panelists in the
scientific-disciplinare area 09industrial and information engineering of the
CIVR (Committee for Evaluation of Italian Research), which has the aim to
evaluate the Italian research in the above area for the period 20012003. In 2003
he received the Darlington Award. Since 2011 he is a member of the Board of
Governors of the IEEE CAS Society.
Melita Pennisi (M07) was born in Catania, Italy, in
1980. She received the Laurea degree in electronics
engineering and the Ph.D. degree in electronics
and automatic engineering from the University of
Catania, in 2004 and 2008, respectively.
Since 2008, she has worked with the DIEES
(Dipartimento di Ingegneria Elettrica Elettronica
e dei Sistemi) of the University of Catania as a
Researcher. She is coauthor of more than 15 pub-
lications on international journals and conference
proceedings. Her primary research interests include
the modeling and the optimized design of CMOS high-performance, analysis
of analog nonlinear circuits, behavioral modeling of complex mixed-signal
circuits, and design/modeling for variability-tolerant and low-leakage VLSI
circuits.
Massimo Alioto (M01SM07) was born in
Brescia, Italy, in 1972. He received the Laurea
degree in electronics engineering and the Ph.D.
degree in electrical engineering from the University
of Catania, Italy, in 1997 and 2001, respectively.
In 2002, he joined the Department of Information
Engineering of the University of Siena as a Research
Associate and in the same year as an Assistant
Professor. In 2005 he was appointed Associate Pro-
fessor of Electronics. In the summer of 2007, he was
a Visiting Professor at EPFL-Lausanne, Switzerland.
In 20092011, he held a Visiting Professor position at BWRC-UCBerkeley,
investigating on next-generation ultra-low power circuits and wireless nodes.
In 20112012, he is also Visiting Professor at University of Michigan, in-
vestigating on active techniques for resiliency in near-threshold processors,
error-aware VLSI design for wide energy scalability, ultra-low power circuits,
and energy scavenging. He has authored or coauthored 170 publications on
journals (60, mostly IEEE Transactions) and conference proceedings. Two of
them are among the most downloaded TVLSI papers in 2007 (respectively
10th and 13th). He is coauthor of the book Model and Design of Bipolar and
MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer,
2005). His primary research interests include ultra-low power VLSI circuits
and wireless nodes, near-threshold circuits for green computing, error-aware
and widely energy-scalable VLSI circuits, circuit techniques for emerging
technologies. He is the director of the Electronics Lab at University of Siena
(site of Arezzo).
Prof. Alioto is a member of the HiPEAC Network of Excellence. He is
the Chair of the VLSI Systems and Applications Technical Committee of
the IEEE Circuits and Systems Society, for which he was also Distinguished
Lecturer in 20092010 and member of the DLP Coordinating Committee in
20112012. He serves or has served as a Track Chair in a number of confer-
ences (ISCAS, ICCD, ICECS, APCCAD, ICM). He was Technical Program
Chair of the ICM 2010 and NEWCAS 2012 conferences. He serves as Associate
Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION
(VLSI) SYSTEMS, the ACM Transactions on Design Automation of Electronic
Systems, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I, the
Microelectronics Journal, IntegrationThe VLSI Journal, the Journal of
Circuits, Systems, and Computers, the Journal of Low Power Electronics, as
well as the Journal of Low Power Electronics and Applications. He is or was
also Guest Editor of the Special Issue Ultra-low voltage circuits and systems
of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART II, as well as
of the Special Issue Advances in oscillator analysis and design of the Journal
of Circuits, Systems, and Computers.