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Preferred Device
Power MOSFET
33 Amps, 100 Volts
NChannel TO220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
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offers a draintosource diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly 33 AMPERES
well suited for bridge circuits where diode speed and commutating 100 VOLTS
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
RDS(on) = 60 m
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a NChannel
Discrete Fast Recovery Diode D
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
G
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Symbol Value Unit
S
DrainSource Voltage VDSS 100 Vdc
DrainGate Voltage (RGS = 1.0 M) VDGR 100 Vdc MARKING DIAGRAM
GateSource Voltage & PIN ASSIGNMENT
Continuous VGS 20 Vdc 4
NonRepetitive (tp 10 ms) VGSM 40 Vpk 4 Drain
Drain Current Continuous ID 33 Adc
Drain Current Continuous @ 100C ID 20
Drain Current Single Pulse (tp 10 s) IDM 99 Apk TO220AB
Total Power Dissipation PD 125 Watts CASE 221A
Derate above 25C 1.0 W/C STYLE 5 MTP33N10E
LLYWW
Operating and Storage Temperature Range TJ, Tstg 55 to C
150 1
2 1 3
3
Single Pulse DraintoSource Avalanche EAS 545 mJ Gate Source
Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, 2
IL = 33 Apk, L = 1.000 mH, RG = 25 ) Drain
Thermal Resistance C/W MTP33N10E = Device Code
Junction to Case RJC 1.0 LL = Location Code
Junction to Ambient RJA 62.5 Y = Year
Maximum Lead Temperature for Soldering TL 260 C WW = Work Week
Purposes, 1/8 from case for 10 sec.
ORDERING INFORMATION
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MTP33N10E
90 90
TJ = 25C VGS = 10 V VDS 10 V
80 80 TJ = 55C
I D , DRAIN CURRENT (AMPS)
20 6V 20
10 5V 10
0 0
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)
0.02 0.037
0 6 12 18 24 30 36 42 48 54 60 66 5 11 17 23 29 35 41 47 53 59 65
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current Figure 4. OnResistance versus Drain Current
and Temperature and Gate Voltage
2.0 10000
RDS(on) , DRAINTOSOURCE RESISTANCE
VGS = 10 V VGS = 0 V
1.8 ID = 16.5 A
1.6
I DSS , LEAKAGE (nA)
1000 TJ = 125C
(NORMALIZED)
1.4
1.2 100C
100
1.0
25C
0.8
0.6 10
50 25 0 25 50 75 100 125 150 20 30 40 50 60 70 80 90 100
TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
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MTP33N10E
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the offstate condition when
controlled. The lengths of various switching intervals (t) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can onstate when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because draingate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
t = Q/IG(AV) complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG VGSP) resistance (Figure 9) shows how typical switching
tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If
where the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG
The circuit used to obtain the data is constructed to minimize
RG = the gate drive resistance
common inductance in the drain and gate circuit loops and
and Q2 and VGSP are read from the gate charge curve.
is believed readily achievable with board mounted
During the turnon and turnoff delay times, gate current is components. Most power electronic loads are inductive; the
not constant. The simplest calculation uses appropriate data in the figure is taken with a resistive load, which
values from the capacitance curves in a standard equation for approximates an optimally snubbed inductive load. Power
voltage change in an RC network. The equations are: MOSFETs may be safely operated into an inductive load;
td(on) = RG Ciss In [VGG/(VGG VGSP)] however, snubbing reduces switching losses.
td(off) = RG Ciss In (VGG/VGSP)
5000
VDS = 0 V VGS = 0 V TJ = 25C
4500 Ciss
4000
C, CAPACITANCE (pF)
3500
Crss
3000
2500
Ciss
2000
1500
1000 Coss
500
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
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MTP33N10E
14 140 1000
VGS, GATETOSOURCE VOLTAGE (VOLTS)
t, TIME (ns)
tr
8 Q1 80
100
6 60 tf
ID = 33 A
4 TJ = 25C 40 td(off)
2 Q3 20
VDS td(on)
0 0 10
0 10 20 30 40 50 60 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
24
21
18
15
12
9
6
3
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous draintosource voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases nonlinearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, Transient Thermal temperature.
ResistanceGeneral Data and Its Use. Although many EFETs can withstand the stress of
Switching between the offstate and the onstate may draintosource avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 s. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum
exceed (TJ(MAX) TC)/(RJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated EFET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For
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MTP33N10E
1000 550
VGS = 20 V
100 TC = 25C
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature
1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
0.2
0.1
0.1 P(pk)
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
0.05
PULSE TRAIN SHOWN
0.02 t1 READ TIME AT t1
0.01 t2 TJ(pk) TC = P(pk) RJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 1.0E+00 1.0E+01
t, TIME (ms)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
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MTP33N10E
PACKAGE DIMENSIONS
TO220 THREELEAD
TO220AB
CASE 221A09
ISSUE AA
NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
T PLANE
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U C 0.160 0.190 4.07 4.82
H D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 1.15
Z 0.080 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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MTP33N10E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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