Академический Документы
Профессиональный Документы
Культура Документы
UNIT I
Contents:
The main objective of this lesson is to learn the block diagram of a digital computer
and various processing units in it. The concept of Binary numbers and its
representation is discussed.
1.1 Introduction
Digital System
Control Unit
The control unit (often called a control system or central controller) directs the
various components of a computer.
It reads and interprets (decodes) instructions in the program one by one.
The control system decodes each instruction and turns it into a series of
control signals that operate the other parts of the computer.
Control systems in advanced computers may change the order of some
instructions so as to improve performance.
The memory unit stores programs as well as input, output, and intermediate
data.
The processor unit performs arithmetic and other data-processing tasks as
specified by a program.
The input and output devices are special digital systems driven by
electromechanical parts and controlled by electronic digital circuits.
An electronic calculator is a digital system similar to a digital computer, with
the input device being a keyboard and the output device a numerical display.
A digital computer, however, is a more powerful device than a calculator.
4
A digital computer can accommodate many other input and output devices; it
can perform not only arithmetic computations, but logical operations as well
and can be programmed to make decisions based on internal and external
conditions.
A digital computer is an interconnection of digital modules.
15 - Decimal
1111 Binary
F Hexadecimal
17 - Octal
Base or Radix of a number is the number of different digits which can occur at each
position in the number system
Decimal 0,1,2,3.9
Octal 0,1,2,3,..7
Binary 0,1
Hexadecimal 0-9,A-F
Example : 3456.789
The block diagram of digital computer and its various units has been explained. The
concept of binary term has been discussed as on or off state. The numbers with
different bases has been depicted in the form of table.
6
1.6 References
http://poppy.snu.ac.kr/~kchoi/class/lc_intro/number_sys.pdf.
http://www.ncb.ernet.in/education/modules/mfcs/resources/BinaryNumberSys
tems.pdf.
http://www.danbbs.dk/~erikoest/binary.htm
7
Contents:
The aim of this lesson is to perform conversion between one base to another base and
to gain knowledge about number system.
2.1 Introduction
1 * 100 + 2 * 10 + 3 * 1 =
100 + 20 + 3 = 123
Each digit appearing to the left of the decimal point represents a value between zero
and nine times power of ten represented by its position in the number.
Digits appearing to the right of the decimal point represent a value between zero and
nine times an increasing negative power of ten.
For example, the value 725.194 is represented as follows:
uses base 8
includes only the digits 0 through 7 (any other digit would make the
number an invalid octal number)
When dealing with large values, binary numbers quickly become too unwieldy. The
hexadecimal (base 16) numbering system solves these problems. Hexadecimal
numbers offer the two features:
In the Hexadecimal number system, the hex values greater than 9 carry the following
decimal value:
9
Decimal Binary(base 2)
e.g. convert (41.375)10 to binary representation
1. Integer part
(41)10 = (101001)2
41/2 =20 rem 1
20/2 =10 rem 0
10/2 =5 rem 0
5/2 =2 rem 1
2/2 =1 rem 0
11
1/2 =0 rem 1
Hence result: (101001)2
2. Fractional part
(.375)10 = (.011)2
.375 x 2 = 0.75 0 MSB
.75 x 2 = 1.5 1
.5 x 2 = 1.0 1 LSB
Hence result: (.011)2
It is very easy to convert from a binary number to a decimal number. Just like the
decimal system, we multiply each digit by its weighted position, and add each of the
weighted values together. For example, the binary value 1100 1010 represents:
1 * 128 + 1 * 64 + 0 * 32 + 0 * 16 + 1 * 8 + 0 * 4 + 1 * 2 + 0 * 1 =
128 + 64 + 0 + 0 + 8 + 0 + 2 + 0 =
202
It is easy to convert from an integer binary number to octal. This is accomplished by:
1. Break the binary number into 3-bit sections from the LSB to the MSB.
2. Convert the 3-bit binary number to its octal equivalent.
For example, the binary value 1010111110110010 will be written:
001 010 111 110 110 010
1 2 7 6 6 2
It is also easy to convert from an integer octal number to binary. This is accomplished
by:
1. Convert the decimal number to its 3-bit binary equivalent.
2. Combine the 3-bit sections by removing the spaces.
12
To convert from Octal to Decimal, multiply the value in each position by its Octal
weight and add each value. Using the value from the previous example, 127662, we
would expect to obtain the decimal value 44978.
1*8^5 2*8^4 7*8^3 6*8^2 6*8^1 2*8^0
To convert decimal to octal is slightly more difficult. The typical method to convert
from decimal to octal is repeated division by 8.
Repeated Division By 8
For this method, divide the decimal number by 8, and write the remainder on the side
as the least significant digit. This process is continued by dividing he quotient by 8
and writing the remainder until the quotient is 0. When performing the division, the
remainders which will represent the octal equivalent of the decimal number are
written beginning at the least significant digit (right) and each new digit is written to
the next more significant digit (the left) of the previous digit. Consider the number
44978.
Division Quotient Remainder Octal Number
44978 / 8 5622 2 2
5622 / 8 702 6 62
702 / 8 87 6 662
87 / 8 10 7 7662
10 / 8 1 2 27662
1/8 0 1 127662
13
To convert a hexadecimal number into a binary number, simply break the binary
number into 4-bit groups beginning with the LSB and substitute the corresponding
four bits in binary for each hexadecimal digit in the number.
For example, to convert 0ABCDh into a binary value, simply convert each
hexadecimal digit according to the table above. The binary equivalent is:
A F B 2
The first step is to pad the binary number with leading zeros to make sure that the the
binary number contains multiples of four bits.
For example, given the binary number 10 1100 1010, the first step would be to add
two bits in the MSB position so that it contains 12 bits. The revised binary value is
0010 1100 1010.
The next step is to separate the binary value into groups of four bits, e.g., 0010 1100
1010. Finally, look up these binary values in the table above and substitute the
appropriate hexadecimal digits, e.g., 2CA.
The weighted values for each position is as follows:
4096 256 16 1
It is easy to convert from an integer binary number to hex. This is accomplished by:
1. Break the binary number into 4-bit sections from the LSB to the MSB.
2. Convert the 4-bit binary number to its Hex equivalent.
A F B 2
To convert from Hex to Decimal, multiply the value in each position by its hex weight
and add each value. Using the value from the previous example, 0AFB2H, we would
expect to obtain the decimal value 44978.
The typical method to convert from decimal to hex is repeated division by 16.
Repeated Division By 16
For this method, divide the decimal number by 16, and write the remainder on the
side as the least significant digit. This process is continued by dividing the quotient by
16 and writing the remainder until the quotient is 0. When performing the division,
the remainders which will represent the hex equivalent of the decimal number are
written beginning at the least significant digit (right) and each new digit is written to
the next more significant digit (the left) of the previous digit. Consider the number
44978.
44978 / 16 2811 2 2
2811 / 16 175 11 B2
175 / 16 10 15 FB2
10 / 16 0 10 0AFB2
Examples
25 => 2 x 10 1+ 5 x 10 0 (decimal)
11001 => 1 x 2 4+ 1 x 23+ 0 x 22+ 0 x 2 1+ 1 x 20 (binary)
19 => 1 x 16 1+ 9 x 16 0 (hexadecimal)
31 => 3 x 81+ 1 x 8 0(octal)
15
This lesson has discussed various number systems with different base and the
conversion from one base to another base has been discussed in detail with examples.
1. Convert i. 58.46 10 ii. 125.09 10 to binary, octal and hexadecimal number base
systems.
2. Convert i. 1011.0112 ii. 11111.11012 to decimal, octal and hexadecimal number
base systems.
3. Convert i. 7438 ii. 452.0168 to binary, decimal and hexadecimal number base
systems.
4. Convert i. FF.AD16 ii. BC.EF16 to binary, octal and decimal number base systems.
5. Convert the Following
5.1 Binary to Decimal
a. 101110
b. 1110101
c. 110110100
d. 1101101.1111
e. 10.100001
5.2 Decimal to Binary
a. 1231
b. 673.23
c. 175
d. 1998
e. 12.45
5.3 Decimal to Octal
a. 7562
b. 225.225
5.4 Octal to Decimal
a. 623.77
2.6 References
http://poppy.snu.ac.kr/~kchoi/class/lc_intro/number_sys.pdf.
http://www.ncb.ernet.in/education/modules/mfcs/resources/BinaryNumberSys
tems.pdf.
http://www.danbbs.dk/~erikoest/binary.htm
17
Contents:
3.1 Introduction
Complements are used in digital computers for simplifying the subtraction operation
and for logical manipulation. Various complementary methods are diminished radix
and radix complement. The concept of 9s, 10s 1s and 2s complementary
subtraction have been discussed in this lesson.
3.2 Complements
Complements are used in digital computers for simplifying the subtraction operation
and for logical manipulation.
There are two types of complements
Diminished Radix (or r-1s) complement
Radix (or rs) complement
e.g.
(33)10 (22)10 = 33 +(99-22)9s
= (33 + 77)9s
= (110)9s (discard end carry, add 1)
= (10 +1)10
= (11)10
3.2.5 2s Complement
To calculate the 2's complement of an integer, invert the binary equivalent of the
number by changing all of the ones to zeroes and all of the zeroes to ones (also called
1's complement), and then add one.
For example,
0000 0010 = +2
Two's complement subtraction is the binary addition of the minuend to the 2's
complement of the subtrahend (adding a negative number is the same as subtracting a
positive one).
20
For example,
1111 1011 = -5
3.2.7 1s Complement
2s Complement
Rs Complement
R-1s Complement
1s Complement
2s Complement
10s and 9s Complement
22
3.6 References
http://academic.evergreen.edu/projects/biophysics/technotes/program/2s_com
p.htm#calculate#calculate
23
Contents:
The aim of this lesson is to explain about various Binary codes, Binary coded
decimal, Error detecting codes, reflected / gray code, Excess-3-Code and ASCII
alphanumeric code.
4.1 Introduction
Electronic systems use signals that have 2 distinct values and circuit elements
that have 2 stable states. A binary digit is represented as 0 or 1. A group of 4 bit
elements requires a 4 bit code. A group of 8 bit elements requires a three bit code. The
BCD is a straight assignment of the binary equivalent.
Electronic circuits have 2 distinct values and circuit elements have 2 stable states. A
BIT by definition, is a Binary Digit. To represent a group of 2n distinct elements in a
binary code requires a minimum of n bits.
Sign 2's
Offset 4221 Gray
... magni- Compli- BCD Excess-3
Binary Code Code
tude ment
-4 1100 0100 1100 ... ... ... ...
-3 1011 0101 1101 ... ... ... ...
-2 1010 0110 1110 ... ... ... ...
-1 1001 0111 1111 ... ... ... ...
0000 0011
0 0000 1000 0000 0000 0000
0000 0011
0000 0011
1 0001 1001 0001 0001 0001
0001 0100
0000 0011
2 0010 1010 0010 0010 0011
0010 0101
0000 0011
3 0011 1011 0011 0011 0010
0011 0110
0000 0011
4 0100 1100 0100 1000 0110
0100 0111
0000 0011
5 0101 1101 0101 0111 0111
0101 1000
0000 0011
6 0110 1110 0110 1100 0101
0110 1001
0000 0011
7 0111 1111 0111 1101 0100
0111 1010
0000 0011
8 ... ... ... 1110 1100
1000 1011
0000 0011
9 ... ... ... 1111 1101
1001 1100
0001 0100
10 ... ... ... ... 1111
0000 0011
0001 0100
11 ... ... ... ... 1110
0001 0100
0001 0100
12 ... ... ... ... 1010
0010 0101
0001 0100
13 ... ... ... ... 1011
0011 0110
0001 0100
14 ... ... ... ... 1001
0100 0111
0001 0100
15 ... ... ... ... 1000
0101 1000
One of the most widely used representations of numerical data is the binary coded
decimal (BCD) form in which each integer of a decimal number is represented by a 4-
bit binary number (see conversion table). It is particularly useful for the driving of
display devices where a decimal output is desired. BCD usually refers to such coding
in which the binary digits have their normal values, i.e., 8421. Sometimes it is written
"8421 BCD" to clearly distinguish it from other binary codes such as the 4221 Code,
but when BCD is used without qualification, the 8421 version is assumed.
The field for Binary Coded Decimal (BCD) numbers is calculated from any of the
other bases, but no calculation routine is included here for conversion from BCD to
the other forms.
For Example:
Finally we stick all of it together in the order it appears in the original number,
i.e. 0100 0000 1001 0110
so 4096 = 0100000010010110 (BCD).
It is interesting to note that this is not the same as the binary equivilent, because:
4096 = 0001000000000000
How does the recipient know that the frame it received is correct?
What kinds of errors can we get?
o Bits can flip
o Can bits be lost?
o Is it usally single bits or sequences of bits?
The sender could send two copies. If they didn't match, the recipient could
assume they were incorrect.
26
A Gray code is an encoding of numbers so that adjacent numbers have a single digit
differing by 1. The term Gray code is often used to refer to a "reflected" code, or more
specifically still, the binary reflected Gray code.
2 3 4
0 0 1 1
1 0 0 1 0
0 1 1 1
1
0 2 0 3 1 4 0
27
Gray codes corresponding to the first few nonnegative integers are given in the
following table.
0 0 20 11110 40 111100
1 1 21 11111 41 111101
2 11 22 11101 42 111111
3 10 23 11100 43 111110
4 110 24 10100 44 111010
5 111 25 10101 45 111011
6 101 26 10111 46 111001
7 100 27 10110 47 111000
8 1100 28 10010 48 101000
9 1101 29 10011 49 101001
10 1111 30 10001 50 101011
11 1110 31 10000 51 101010
12 1010 32 110000 52 101110
13 1011 33 110001 53 101111
14 1001 34 110011 54 101101
15 1000 35 110010 55 101100
16 11000 36 110110 56 100100
17 11001 37 110111 57 100101
18 11011 38 110101 58 100111
19 11010 39 110100 59 100110
4.2.5 Excess-3-Code
It is a 4 bit code.
In this code, a digit is represented by adding 3 to the number and then converting it to
a 4-bit binary number. It can be used for the representation of multi-digit decimal
numbers as can BCD.
1 2
3 3
3 5
2 9
3 3
5 12
0101 1100
The American Standard Code for Information Interchange (ASCII) is the standard
alphanumeric code for keyboards and a host of other data interchange tasks. Letters,
numbers, and single keystroke commands are represented by a seven-bit word.
Typically a strobe bit or start bit is sent first, followed by the code with LSB first.
Being a 7-bit code, it has 2^7 or 128 possible code groups.
Problem-1
PRINT X
P 101 0000
R 101 0010
I 100 1001
N 100 1110
T 101 0100
010 0000
X 101 1000
Various codes has been explained in detail with examples and a parity bit helps in
detecting transmission errors, the reflected changes by only one bit as it proceeds
from one number to the next. ASCII refers to American Standard Code for
Information Interchange.
4.4 Lesson-end Activities
Binary Codes
Binary Coded Decimal
Gray Code
Excess-3-Code
ASCII Code
4.6 References
Unit II
Contents:
The main objective of this lesson is to learn the basics of Boolean algebra its
postulates and laws. The basic building blocks that is the digital circuits has been
discussed.
5.1 Introduction
Boolean algebra is a deductive mathematical system closed over the values zero and
one (false and true). This was invented by george Boolie and named after him. various
laws and postulates has been proved. Logic circuits refers to one or more input
voltages but only one output voltage, and gates are often called logic circuits. The
axiomatic definition of Boolean algebra has been discussed.
Boolean algebra is a deductive mathematical system closed over the values zero and
one (false and true).
A binary operator defined on a set of values accepts a pair of boolean inputs and
produces a single boolean value. For example, the boolean AND operator accepts two
boolean inputs and produces a single boolean output (the logical AND of the two
inputs).
In a algebra system, there are some initial assumptions, or postulates, that the system
follows. Boolean algebra systems often employ the following postulates:
Closure. The boolean system is closed with respect to a binary operator if for
every pair of boolean values, it produces a boolean result. For example, logical
AND is closed in the boolean system because it accepts only boolean operands
and produces only boolean results.
32
P1 Boolean algebra is closed under the AND, OR, and NOT operations.
P2 The identity element with respect to is one and + is zero. There is no identity
element with respect to logical NOT.
P6 and + are both associative. That is, (AB)C = A(BC) and (A+B)+C = A+(B+C).
T1 : Commutative Law
(a) A + B = B + A
(b) A B = B A
T2 : Associate Law
(a) (A + B) + C = A + (B + C)
(b) (A B) C = A (B C)
T3 : Distributive Law
(a) A (B + C) = A B + A C
(b) A + (B C) = (A + B) (A + C)
T4 : Identity Law
(a) A + A = A
(b) A A = A
T5 :
(a)
(b)
T6 : Redundance Law
(a) A + A B = A
(b) A (A + B) = A
T7 :
(a) 0 + A = A
(b) 0 A = 0
T8 :
(a) 1 + A = 1
(b) 1 A = A
T9 :
(a)
(b)
T10 :
(a)
(b)
(a)
(b)
Question : 1
34
(1) Algebraically
Question : 2
35
Complement of a Function
Example
F1 = X'YZ' + Z'Y'Z
= (X + Y' + Z) (X + Y + Z')
F2 = X(Y'Z' + YZ)
= (X' + ( Y + Z) (Y' + Z')
The logical functions are represented with some special symbols to denote these
functions in a logical diagram. There are three fundamental logical operations,
from which all other functions, no matter how complex, can be derived. These
functions are named and, or, and not.
The OR Gate
While the three basic functions AND, OR, and NOT are sufficient to accomplish
all possible logical functions and operations, some combinations are used so
commonly that they have been given names and logic symbols of their own.
The first is called NAND, and consists of an AND function followed by a NOT
function. The second, as you might expect, is called NOR. This is an OR function
followed by NOT. The third is a variation of the OR function, called the Exclusive-
OR, or XOR function.
The NAND and NOR gates are called universal functions since with either one the
AND and OR functions and NOT can be generated.
Note:
The concepts of logic circuits with neat graphic symbol representation has been
presented and various laws of Boolean algebra has been explained. The complement
of a function with a example has been explained.
1. Give the basic laws of Boolean algebra and their duals. Prove the Boolean laws.
2. Neatly, draw the basic logic gates and give their truth table.
3. What are universal gates? Why are they called so?
5.6 References
Contents:
The main aim of this lesson is to learn the sum of products, product of sums,
minterms and maxterms and digital logic families.
6.1 Introduction
The lesson covers the conversion part from sum of products to product of sums using
terms and using truth tables. The digital logical families includes RAM, PROM and
EPROM.
A binary variable may appear either in its normal form (x) or in its complement form
X'. Consider 2 binary variables X & Y combined with an AND operation There are 4
possible outcomes
1. X'Y'
2. XY'
3. X'Y
4. XY
Each of these four AND terms represent a minterm or standard product. N variables
can be combined to form 2n Minterms.
Consider the two functions F2 and F1 and as shown in the following table.
41
Each term is expected to see if it contains all the variables. If it misses one or more
variables, it is ANDed with an expression such as x+x' where x is one of the missing
variable
The function has 3 variables A,B,C. The first term A has 2 Missing variables B & C
and is written as
F(A,B,C) = (1,4,5,6,7)
M0 M2 M4 M5
F(X,Y,Z) = (0,2,4,5)
X Y Z F = XY + X'Z
0 0 0 00
0 0 1 1
0 1 0 02
0 1 1 1
1 0 0 04
1 0 1 05
1 1 0 1
1 1 1 1
F(X,Y,Z) = (1,3,6,7)
Product of Maxterms
F(X,Y,Z) = (0,2,4,5)
43
Standard Forms
2 types
1. Sum of Products
2. Products of sums
Sum of Products
Product of Sums
F2 = X (Y'+Z) (X'+Y+Z'+W)
Large-scale integration (LSI) devices contain between 100 and a few thousand
gates in a single package. They include digital systems such as processors, memory
chips, and programmable logic devices.
44
Digital integrated circuits are classified not only by their complexity or logical
operations, but also by the specific circuit technology to which they belong. The
circuit technology is referred to as a digital logic family. Each logic family has its
own electronic circuit technology circuit upon which more complex digital circuits
and components are developed. The basic circuit in each technology is a NAND,
NOR, or an inverter gate.
Many different logic families of digital integrated circuits have been introduced
commercially. The following are the most popular:
TTL is a widespread logic family that has been in operation for some time and is
considered as standard. ECL has an advantage in systems requiring high speed
operation. MOS is suitable for circuits that need high component density, and CMOS
is preferable in systems requiring low power consumption.
Emitter-coupled logic (ECL) circuits provides the highest speed among the
integrated digital logic families .ECL is used in systems such as super computers and
signal processors, where high speed is essential.
The characteristics of digital logic families are usually compared by analyzing circuit
of the basic gate in each family.
6.2.4.1 RAM
a word in memory is the same and requires an equal amount of time no matter where
the cells are located physically in memory: thus the name: "random access.
The n data input lines provide the information to be stored in memory, and the n
data output lines supply the information coming out of memory. The k address lines
provide a binary number of k bits that specify a particular word chosen among the 2k
available inside the memory.
k address lines
address lines
k
RAM
Read
unit
Write
n
data output lines
6.2.4.2 PROM
For small quantities it is more economical to use a second type of ROM called a
programmable read only memory or PROM. When ordered, PROM units contain all
the fuses intact, giving all the fuses intact, giving all the 1s in the bits of stored
words.
A blown fuse defines binary 0 states, and an intact fuse gives binary 1 state. All
procedures for programming ROMs are hardware procedures even though the word
programming is used.
6.2.4.3 EPROM
A third type of ROM available is called as erasable PROM. The EPROM can be
reconstructed to the initial value even though it fuses have been blown previously.
When the EPROM is placed under a ultraviolet light for a given period of time, the
shortwave radiation discharges the internal gates that serves as fuses. Certain PROMs
can be erased electrically and these are called electrically erasable PROMs.
The canonical forms, the concept of minterms, maxterms, converting from one form
to another and digital logical families has been dicussed.
Minterms
Maxterms
Digital Logic Families RAM,PROM, EPROM
6.6 References
Contents:
The aim of this lesson is to learn the concept of minimizing the Boolean functions
using KMap method and evaluating dont cares cases in KMap.
7.1 Introduction
A karnaugh map is a visual display of the fundamental products needed for a sum of
products solution. The map method provides a simple straight forward procedure for
minimizing Boolean functions. It is very easy and simple to implement. The concept
of rolling the map, eliminating redundant groups has been discussed along with dont
care conditions.
7.2 Simplification of Boolean Functions
The diagram below illustrates the correspondence between the Karnaugh map and the
truth table for the general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table,
therefore there is one square in the map for every row in the truth table. Around the
edge of the Karnaugh map are the values of the two input variable. A is along the top
and B is down the left hand side. The diagram below explains this:
The values around the edge of the map can be thought of as coordinates. So as an
example, the square on the top right hand corner of the map in the above diagram has
coordinates A=1 and B=0. This square corresponds to the row in the truth table where
A=1 and B=0 and F=1. Note that the value in the F column represents a particular
function to which the Karnaugh map corresponds.
Example 1:
49
Note that values of the input variables form the rows and columns. That is the logic
values of the variables A and B (with one denoting true form and zero denoting false
form) form the head of the rows and columns respectively.
Bear in mind that the above map is a one dimensional type which can be used to
simplify an expression in two variables.
There is a two-dimensional map that can be used for up to four variables, and a three-
dimensional map for up to six variables.
Z = A + AB
Z = A( + B)
Z=A
Referring to the map above, the two adjacent 1's are grouped together. Through
inspection it can be seen that variable B has its true and false form within the group.
This eliminates variable B leaving only variable A which only has its true form. The
minimised answer therefore is Z = A.
Example 2:
Pairs of 1's are grouped as shown above, and the simplified answer is obtained by
using the following steps:
Note that two groups can be formed for the example given above, bearing in mind that
50
the largest rectangular clusters that can be made consist of two 1s. Notice that a 1 can
belong to more than one group.
The first group labelled I, consists of two 1s which correspond to A = 0, B = 0 and A
= 1, B = 0. Put in another way, all squares in this example that correspond to the area
of the map where B = 0 contains 1s, independent of the value of A. So when B = 0 the
output is 1. The expression of the output will contain the term
For group labelled II corresponds to the area of the map where A = 0. The group can
therefore be defined as . This implies that when A = 0 the output is 1. The output is
therefore 1 whenever B = 0 and A = 0
Hence the simplified answer is Z = +
(a)
(b)
(c)
51
(e)
(f)
(g)
(1) Z = f(A,B,C) = + B + AB + AC
(2) Z = f(A,B,C) = B + B + BC + A
Solutions
(i) Z = f(A,B,C) = + B + AB + AC
52
By using the rules of simplification and ringing of adjacent cells in order to make as
many variables redundant, the minimised result obtained is B + AC+
Solutions
(ii) Z = f(A,B,C) = B + B + BC + A
By using the rules of simplification and ringing of adjacent cells in order to make as
many variables redundant, the minimised result obtained is B + A
The map is considered to lie on a surface with the top and bottom edges, as well as the
right and left edges, touching each other to form adjacent squares.
F = W + XY'Z
W'X' 1
W'X 1 1 1 1
WX 1 1 1 1
54
BC'D' + BCD'
BD' (C +C')
BD'
A'B'
A'B 1 1
AB 1 1
AB'
After the groups have been encircled, eliminate the redundant groups if occurred. This
is the group whose 1's are already used by other group.
W'X' 1
W'X 1 1 1
WX 1 1 1 1
WX' 1
55
W'X' 1
W'X 1 1 1
WX 1 1 1
WX' 1
W'X' 1
W'X 1 1 1
WX 1 1 1
WX' 1
1. Enter a 1 on the Karnaugh Map for each fundamental product that produces a
1 output in the truth table, enter 0 otherwise
2. Encircle the octete, quads and pairs, remember to roll and overlap to get the
possible group.
3. If any isolated 1's remain, encircle each.
4. eliminate any redundant groups
5. Write the Boolean equation by ORing the products corresponding to the
encircled groups.
56
A'B' 1 1
1
A'B 1
AB
AB' 1 1
1
The minimized Boolean function derived from the map in all previous expressed in
the sum of product form.
The product of sum form can be obtained as the 1's placed in the squared of the map
represent the minterms of the function. The minterm not included in the function
denotes the complement of the function. If the squares not placed by 1 is marked with
0 and combines the 0's to valid adjacent squares.
Simplify the Boolean Function
1. Sum Of Products
2. Product of Sums
F(A,B,C,D) = (0,1,2,5,8,9,10)
A'B' 1 1 0 1
A'B 0 1 0 0
AB 0 0 0 0
AB' 1 1 0 1
In some digital system certain input conditions never occur during normal operations,
so its corresponding output also never occurs. Since the output never appears it is
indicated by 'X' in the truth table.
The 'X' is called as Don't Care Condition.
When choosing adjacent squares simplify the function in a map, the don't care
minterms may be assumed to be either 0 or 1 whichever produces the simple
expression.
F(W,X,Y,Z) = (1,3,7,11,15)
d(W,X,Y,Z) = d(0,2,5)
W X Y Z F
0 0 0 0 0 X
1 0 0 0 1 1
2 0 0 1 0 X
58
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 X
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
59
A'B' X 1 1 X
A'B X 1
AB 1
AB' 1
A'B' 1 1 1 1
A'B X 1
AB 1
AB' 1
60
A'B' X 1 1 X
A'B 1 1
AB 1
AB' 1
The Kmap method for minimizing the boolean has been explained with 2 variable, 3
variable and 4 variable map. The sum of products and product of sum has been
illustrated in Kmap and dont care conditions in Kmap has been discussed with
examples
K-Map Concept
2,3,4 Variable Map
Dont Care Conditions
7.6 References
The main of this lesson is to learn the concept of universal gates and implementation
of NAND and NOR gates using simple gates. One more method called as Tabulation
method has been discussed to reduce Boolean expressions.
8.1 Introduction
This lesson explains the building of NAND and NOR gates using simple logic gates
and the tabulation method is an another simplification process of minimizing Boolean
expressions.
To prove that we can construct any boolean function using only NAND gates, we
need only show how to build an inverter (NOT), an AND gate, and an OR gate from a
NAND (since we can create any boolean function using only AND, NOT, and OR).
Building an inverter is easy, just connect the two inputs together
Once we can build an inverter, building an AND gate is easy - just invert the output of
a NAND gate. After all, NOT (NOT (A AND B)) is equivalent to A AND B .Of
course, this takes two NAND gates to construct a single AND gate, but no one said
that circuits constructed only with NAND gates would be optimal, only that it is
possible.
62
The remaining gate we need to synthesize is the logical-OR gate. We can easily
construct an OR gate from NAND gates by applying DeMorgan's theorems.
The tabular method makes repeated use of the law A + = 1. Note that Binary
notation is used for the function, although decimal notation is also used for the
functions. As usual a variable in true form is denoted by 1, in inverted form by 0, and
the abscence of a variable by a dash ( - ).
63
This is because the FIRST RULE of the Tabular method for two terms to combine,
and thus eliminate one variable, is that they must differ in only one digit position.
when two terms are combined, one of the combined terms has one digit more at logic
1 than the other combined term. This indicates that the number of 1's in a term is
significant and is referred to as its index.
0000...................Index 0
0010, 1000.............Index 1
1010,0011,1001.......Index 2
1110, 1011.............Index 3
1111...................Index 4
The necessary condition for combining two terms is that the indices of the two terms
must differ by one logic variable which must also be the same.
Example 1:
To make things easier, change the function into binary notation with index value and
decimal value.
Tabulate the index groups in a column and insert the decimal value alongside.
From the first list, combine terms that differ by 1 digit only from one index group to
the next. These terms from the first list are then seperated into groups in the second
list. Note that the ticks are just there to show that one term has been combined with
another term. From the second list we can see that the expression is now reduced to: Z
= + + C+A
From the second list note that the term having an index of 0 can be combined with the
terms of index 1. Bear in mind that the dash indicates a missing variable and must line
up in order to get a third list. The final simplified expression is: Z =
Bear in mind that any unticked terms in any list must be included in the final
expression (none occurred here except from the last list). Note that the only prime
implicant here is Z = .
Note that the above solution can be derived algebraically. Attempt this in your notes.
Example 2:
The chart is used to remove redundant prime implicants. A grid is prepared having all
the prime implicants listed at the left and all the minterms of the function along the
top. Each minterm covered by a given prime implicant is marked in the appropriate
position.
From the above chart, BD is an essential prime implicant. It is the only prime
implicant that covers the minterm decimal 15 and it also includes 5, 7 and 13. is
also an essential prime implicant. It is the only prime implicant that covers the
minterm denoted by decimal 10 and it also includes the terms 0, 2 and 8. The other
minterms of the function are 1, 3 and 12. Minterm 1 is present in and D.
Similarly for minterm 3. We can therefore use either of these prime implicants for
these minterms. Minterm 12 is present in A and AB , so again either can be used.
The disadvantages of Map method has been overcome and Tabulation method has
been discussed and many Computer programs have been developed employing this
algorithm. The method reduces a function in standard sum of products form to a set of
prime implicants from which as many variables are eliminated as possible.
Tabulation Method
NAND and NOR Gates
8.6 References
UNIT III
The main objective of this lesson is to know the basics of combinational circuit and
formulate various systematic design and analysis procedures of combinational
circuits.
9.1 Introduction
Logic circuits for digital systems may be combinational circuits or sequential circuits.
A combinational circuit consists of input variables, logic gates and output variables.
The logic gates accepts signals from the inputs and generate signals to the outputs.
Digital computers performs a variety of information processing tasks.
A combinational circuit that performs the addition of 2 bits is called as Half adder and
a combinational circuit that performs the addition of 3 bits (2 significant bit and a
previous carry) is called as Full Adder. Taking the complement of the subtrahend and
adding it to the minuend accomplish the subtraction of 2 binary numbers.
Adders are the basic building blocks of all arithmetic circuits; adders add two
binary numbers and give out sum and carry as output.
A quarter adder is a circuit that can add two binary digits but will not produce a carry.
This circuit will produce the following results:
0 plus 0 = 0
0 plus 1 = 1
1 plus 0 = 1
1 plus 1 = 0 (no carry)
Half Adder.
Full Adder.
Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out
bit. This operation is called half addition and the circuit to realize it is called a half
adder.
69
X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Booelan Expressions
S (X,Y) = (1,2)
S = X'Y + XY'
S=X Y
CARRY(X,Y) = (3)
CARRY = XY
Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a
carry input bit C-in produces a sum bit S and a carry out C-out bit.
X Y Z SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
70
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Booelan Expressions
CARRY = XY + XZ + YZ
The below implementation shows implementing the full adder with AND-OR gates,
instead of using XOR gates. The basis of the circuit below is from the above Kmap.
71
9.2.2.2 Subtracter
Subtracter circuits take two binary numbers as input and subtract one binary number
input from the other binary number input. Similar to adders, it gives out two outputs,
difference and borrow (carry-in the case of Adder).
Half Subtracter.
72
Full Subtracter.
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
From the above table we can draw the Kmap as shown below for "difference" and
"borrow". The boolean expression for the difference and Borrow can be written.
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
The availability of large variety of codes for the same discrete elements of the
information results in different variety of codes by different digital systems.
Sometimes the output of one system will be an input of another system.
A conversion circuit must be inserted between 2 systems if uses each different codes
for the same information. Thus a code converter is a circuit that makes the 2 systems
compatible even though each uses a different binary code
75
Transforms BCD code for the decimal digits to Excess-3 code for the decimal
digits
BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001,
respectively
Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3
(binary 0011) added to each BCD code word
Formulation
Conversion of 4-bit codes can be most easily formulated by a truth table
In p u t B C D O u tp u t E x c e ss-3
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 0 1 1
76
The combinational circuit for performing arithmetic operations has been discussed
and it includes half adder, full adder, half subtracter and full subtracter. The Boolean
expressions of each circuit has been discussed with circuit diagram.
1. With neat circuit and truth table, discuss half adder and half Subtracter.
2. Construct a full adder with half adders.
3. Give the truth table and logic circuit of full Subtracter.
4. Discuss code converter in detail.
Half Adder
o A combinational circuit that performs the addition of 2 bits is called as
Half adder
Full Adder
o A combinational circuit that performs the addition of 3 bits (2 significant
bit and a previous carry) is called as Full Adder
Half Subtracter
o A half subtracter that subtracts 2 bits and produces their difference.
Full Subtracter
o A full subtracter is a combinational circuit that performs a subtraction
between 2 bits taking into account that a 1 may be borrowed by a lower
significant stage
9.6 References
www.asic-world.com/digital/arithmetic3.html
www.cs.princeton.edu/courses/archive/spr05/cos126/lectures/10.pdf
www.cs.bu.edu/faculty/snyder/cs450/Chapter02.pdf
77
The main of this lesson is to learn the concepts of binary parallel adder and how full
adder is fashioned in a parallel manner and the concept of converting decimal
numbers to binary coded decimal representation.
10.1 Introduction
A binary parallel adder is a digital function that produces the arithmetic sum of 2
binary numbers in parallel. It consists of full adders connected in cascade with the
output carry from one full adder connected to the input carry of the next full adder. A
decimal adder converts a given decimal number into a binary coded decimal form
A Binary Parallel adder is a digital function that produces the arithmetic sum of 2
binary numbers in parallel. It consists of full adders connected in cascade with the
output carry of one full adder connected to the input of the next full adder.
The adders discussed in the previous section have been limited to adding single-digit
binary numbers and carries. The largest sum that can be obtained using a full adder is
112. Parallel adders let us add multiple-digit numbers. If we place full adders in
parallel, we can add two- or four-digit numbers or any other size desired.
To add 10 2 (addend) and 01 2 (augend), assume there are numbers at the appropriate
inputs. The addend inputs will be 1 on A2 and 0 on A1. The augend inputs will be 0
on B2 and 1 on B1. Working from right to left, as we do in normal addition, lets
calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output of adder
1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a
sum (S2) of 1 with no carry (C2) from adder 1. To determine the sum, read the
outputs (C2, S 2, and S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1.
The sum, then, of 10 2 and 01 2 is 011 2 or 11 2. To add 112 and 012, assume one number
is applied to A1 and A2, and the other to B1 and B2, as shown in figure 3-10. Adder 1
produces a sum (S1) of 0 and a carry (C1) of 1. Adder 2 gives us a sum (S2)
78
Addition of two BCD digits requires two 4-bit Parallel Adder Circuits. One 4-bit
Parallel Adder adds the two BCD digits. A BCD Adder uses a circuit which checks
the result at the output of the first adder circuit to determine if the result has exceeded
9 or a Carry has been generated. If the circuit determines any of the two error
conditions the circuit adds a 6 to the original result using the second Adder circuit.
The output of the second Adder gives the correct BCD output. If the circuit finds the
result of the first Adder circuit to be a valid BCD number (between 0 and 9 and no
Carry has been generated), the circuit adds a zero to the valid BCD result using the
second Adder. The output of the second Adder gives the same result.
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
79
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
If sum is up to 9
Use the regular Adder.
The main topics discussed in the binary parallel adder and algorithm for BCD adder
Decimal Adder
10.6 References
www.asic-world.com/digital/arithmetic3.html
81
11.2 Decoders
A binary decoder has n inputs and 2n outputs. Only one output is active at any one
time, corresponding to the input value.
A 2 to 4 decoder consists of two inputs and four outputs, truth table and symbols of
which is shown below.
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of
which is shown below.
X Y Z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
From the truth table we can draw the circuit diagram as shown in figure below.
84
11.2.2 Encoders
The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs =
1 and the output is the n-bit binary number corresponding to the active input.
85
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what
the 3-to-8 decoder does. At any one time, only one input line has a value of 1.
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs
Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7
Based on the above equations, we can draw the circuit as shown below
Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of
what the 4-to-10 decoder does. At any one time, only one input line has a value of 1.
The figure below shows the truth table of a Decimal-to-binary encoder
86
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
From the above truth table , we can derive the functions Y3, Y2, Y1 and Y0 as given
below.
Y3 = I8 + I9
Y2 = I4 + I5 + I6 + I7
Y1 = I2 + I3 + I6 + I7
Y0 = I1 + I3 + I5 + I7 + I9
The concepts discussed in the above lesson is how binary information are converted
from n input lines to a maximum of 2n output lines and from 2n input lines to n output
lines and various examples of encoders and decoders has been discussed.
1. Explain the various types of decoders with logic circuit and truth table.
2. Explain the various types of encoders with logic circuit and truth table.
11.6 References
www.asic-world.com/digital/combo3.html
87
12.1 Introduction
12.2 Multiplexer
A B f
0 0 C0
0 1 C1
1 0 C2
1 1 C3
Assume that we have four lines, C0, C1, C2 and C3, which are to be multiplexed on a
single line, Output (f). The four input lines are also known as the Data Inputs. Since
there are four inputs, we will need two additional inputs to the multiplexer, known as
the Select Inputs, to select which of the C inputs is to appear at the output. Call these
select lines A and B.
12.2.2 Demultiplexer
The demultiplexer is the inverse of the multiplexer, in that it takes a single data input
and n address outputs. It has 2n outputs. A demultiplexer is a logic circuit with one
input and many outputs. A demultiplexer is a circuit that receives information on a
single line and transmits this information on one of the 2n possible output lines.
90
The selection of the specific output line is controller by the bit values of n selection
lines.
D0
D1
E 1x4 D2
Input Demultiplexer
D3
A B
Selection Lines
E is taken as data input line and A & B are taken as selection lines.
The single input variable has a path to all 4 outputs but he input information is
directed to only of the output lines based on the binary values of the 2 selection lines.
If the selection line AB = 00 the output will be the same as the input value E while all
other outputs are maintained at 0
A B D0 D1 D2 D3
0 0 E 0 0 0
0 1 0 E 0 0
1 0 0 0 E 0
1 1 0 0 0 E
The memory elements are devices capable of storing binary info. The binary info
stored in the memory elements at any given time defines the state of the sequential
circuit. The input and the present state of the memory element determines the output.
Memory elements next state is also a function of external inputs and present state. A
sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
There are two types of sequential circuits. Their classification depends on the timing
of their signals:
92
This is a system whose outputs depend upon the order in which its input variables
change and can be affected at any instant of time.
This type of system uses storage elements called flip-flops that are employed to
change their binary value only at discrete instants of time. Synchronous sequential
circuits use logic gates and flip-flop storage devices. Sequential circuits have a clock
signal as one of their inputs. All state transitions in such circuits occur only when the
clock value is either 0 or 1 or happen at the rising or falling edges of the clock
depending on the type of memory elements used in the circuit. Synchronization is
achieved by a timing device called a clock pulse generator. Clock pulses are
distributed throughout the system in such a way that the flip-flops are affected only
with the arrival of the synchronization pulse. Synchronous sequential circuits that use
clock pulses in the inputs are called clocked-sequential circuits. They are stable and
their timing can easily be broken down into independent discrete steps, each of which
is considered separately.
A flip flop circuit can maintain a binary state indefinitely (as long as the power is
delivered to the circuit) until directed by an input signal to switch states. The major
difference among various types of flip flops are in the number of inputs they possess
and in the manner in which the inputs affect the binary state.
S R Q Q+
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X 0
The operation has to be analyzed with the 4 inputs combinations together with the 2
possible previous states.
The waveform below shows the operation of NOR gates based RS Latch
94
The basic flip flop is an asynchronous sequential circuit. By adding gates to the inputs
of the basic circuit, the flip flop can be made to respond to input levels during the
occurrence of a clock pulse.
The clocked RS flip flop consists of a basic NOR Flip flop and 2 AND gates. The
outputs of the 2 AND gates remain 0 as long as the clock pulse is 0 regardless of S
and R Input values. When the clock pulse goes to 1, information from S and R inputs
is allowed to reach the basic flip flop.
To change to clear state the inputs must be S =0 and R = 1 and CP = 1. With both S
=1 and R = 1 the occurrence of a clock pulse causes both outputs to momentarily go
to 0
S R Q(next)
0 0 Q Q(next) = S + R'Q
SR 0 1 0
SR = 0
1 0 1
1 1 ?
95
The RS latch seen earlier contains ambiguous state; to eliminate this condition we can
ensure that S and R are never equal. This is done by connecting S and R together with
an inverter. Thus we have D Latch: the same as the RS latch, with the only difference
that there is only one input, instead of two (R and S). This input is called D or Data
input. D latch is called D transparent latch for the reasons explained earlier. Delay
flip-flop or delay latch is another name used. Below is the truth table and circuit of D
latch.
D Q Q+
1 X 1
0 X 0
Below is the D latch waveform, which is similar to the RS latch one, but with R
removed.
D Q(next)
D 0 0 Q(next) = D
1 1
96
When the two inputs of JK latch are shorted, a T Latch is formed. It is called T latch
as, when input is held HIGH, output toggles.
T Q Q+
1 0 1
1 1 0
0 1 1
0 0 0
T Q(next)
T 0 Q Q(next) = TQ' + T'Q
1 Q'
The ambiguous state output in the RS latch was eliminated in the D latch by joining
the inputs with an inverter. But the D latch has a single input. JK latch is similar to RS
latch in that it has 2 inputs J and K as shown figure below. The ambiguous state has
been eliminated here: when both inputs are high, output toggles. The only difference
here is output feedback to inputs, which is not there in the RS latch.
97
J K Q
1 1 0
1 1 1
1 0 1
0 1 0
J K Q(next)
0 0 Q
Q(next) = JQ' +
JK 0 1 0
K'Q
1 0 1
1 1 Q'
All sequential circuits that we have seen in the last few pages have a problem (All
level sensitive sequential circuits have this problem). Before the enable input changes
state from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs
changes, then another state transition occurs for the same enable pulse. This sort of
multiple transition problem is called racing.
In the figure above there are two latches, the first latch on the left is called master
latch and the one on the right is called slave latch. Master latch is positively clocked
and slave latch is negatively clocked.
A Master Slave Flip Flop has been constructed by 2 separate flip flops. One circuit
serves as a master and the other serve as a slave and the overall circuit is referred as
master Slave Flip Flop.
When A Clock Pulse CP is 0, the output of the inverter is 1. Since the clock input of
the slave flip flop is 1, the flip flop is enabled and the output is Q and Q. The master
flip flop is disabled because cp = 0.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in
the number of inputs and in the response invoked by different value of input signals.
99
Flip-flop Types
FLIP-
FLIP-FLOP CHARACTERISTIC CHARACTERISTIC
FLOP EXCITATION TABLE
SYMBOL TABLE EQUATION
NAME
S R Q(next) Q Q(next) S R
0 0 Q Q(next) = S + R'Q 0 0 0 X
SR 0 1 0 0 1 1 0
SR = 0 1 0 0 1
1 0 1
1 1 ? 1 1 X 0
J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q(next) = JQ' + K'Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0
Q Q(next) D
D Q(next) 0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1
Q Q(next) T
T Q(next) 0 0 0
T 0 Q Q(next) = TQ' + T'Q 0 1 1
1 Q' 1 0 1
1 1 0
Each of these flip-flops can be uniquely described by its graphical symbol, its
characteristic table, its characteristic equation or excitation table. All flip-flops have
output signals Q and Q'.
The characteristic table in the third column of Table 1 defines the state of each flip-
flop as a function of its inputs and previous state. Q refers to the present state and
Q(next) refers to the next state after the occurrence of the clock pulse. The
characteristic table for the RS flip-flop shows that the next state is equal to the present
state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears
the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation mark (?) for
the next state when S and R are both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K
are replaced by S and R respectively, except for the indeterminate case. When both J
100
and K are equal to 1, the next state is equal to the complement of the present state,
that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and
independent of the present state.
The next state for the T flip-flop is the same as the present state Q if T=0 and
complemented if T=1.
The characteristic table is useful during the analysis of sequential circuits when the
value of flip-flop inputs are known and we want to find the value of the flip-flop
output Q after the rising edge of the clock signal. As with any other truth table, we
can use the map method to derive the characteristic equation for each flip-flop, which
are shown in the third column of Table 1.
During the design process we usually know the transition from present state to the
next state and wish to find the flip-flop input conditions that will cause the required
transition. For this reason we will need a table that lists the required inputs for a given
change of state. Such a list is called the excitation table, which is shown in the fourth
column of Table 1. There are four possible transitions from present state to the next
state. The required input conditions are derived from the information available in the
characteristic table. The symbol X in the table represents a "don't care" condition, that
is, it does not matter whether the input is 1 or 0.
The concepts of Multiplexer, demultiplexer and the various types of flip flops with
excitation tables has been discussed in detail
Multiplexer
Demultiplexer
Types of Flip Flops
12.6 References
UNIT 4
Contents:
The main aim of this lesson is to learn the basics of computer, concepts of machine
language, various categories of languages, and rules of the language.
13.1 Introduction
A computer system includes both hardware and software. Software refers to the
program and hardware refers to the computer on which the instructions are executed.
A program written in a computer may be either dependent or independent of the
computer. The computer understands only machine language and user writes coding
in high level language and so there exist a translator who converts high level language
to machine level language and vice versa. The translator used to convert is referred as
compiler. The basic elementary programming concepts are discussed in this lesson.
13.2.1 Characteristics
A total computer system includes both hardware and software.
Software: Software refers to the set of programs written for the computer
There are various programming languages present but only the computer can
understand programs written in binary form. Programs written in any other languages
have to be converted to binary representation before they are executed in the
computer.
Hexa Decimal
Symbol Description
Code
AND 0 or 8 AND M to AC
ADD 1 or 9 Add M to AC, carry to E
LDA 2 or A Load AC from M
STA 3 or B Store AC in M
BUN 4 or C Branch unconditionally to m
BSA 5 or D Save return address in m and branch to m+1
ISZ 6 or E Increment M and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7170 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right E and AC
CIL 7040 Circulate left E and AC
INC 7017 Increment AC, carry to E
SPA 7010 Skip if AC is positive
SNA 7008 Skip if AC is negative
SZA 7004 Skip if AC is zero
SZE 7002 Skip if E is zero
HLT 7001 Halt computer
INP F800 Input information and clear flag
OUT F400 Output information and clear flag
SKI F170 Skip if input flag is on
SKO F100 Skip if output flag is on
ION F080 Turn interrupt on
IOF F040 Turn interrupt off
MIN 106
SUB 107
DIF 108
Table 13.1 Computer Instructions
103
m: effective address
Machine-Language
Binary code
Exact representations of instructions in memory in form of 0s and 1s
Octal or hexadecimal code
Equivalent Translation of Binary code to octal or hexa decimal code
Assembly-Language
It uses Symbolic code or mnemonic codes such as ADD, SUB. LOAD. Each
symbolic instruction code can be translated into binary coded instruction. The
Translation is done by a special program called an ASSEMBLER
High-Level Language
It uses simple English representation and the programs are written as sequence of
instructions and each statement must be converted into machine level language before
execution. The conversion part is carried by the translator called as COMPILER.
ORG N
Hexadecimal number N is the memory loc.
for the instruction or operand listed in the following line
END
Denotes the end of symbolic program
DEC N
Signed decimal number N to be converted to the binary
HEX N
Hexadecimal number N to be converted to the binary
The first line has a pseudo instruction ORG define the origin of the program at
memory location 100.
The next six lines define machine instructions, and the last 4 lines have pseudo
instructions
The concepts of machine language its various instruction set, a sample program to
perform the summation of 2 numbers has been explained in various language
instructions sets. A programming language is defined as a set of rules. Various rules
of a programming language have been clearly explained in this lesson.
Assembly level language uses pneumonic codes and assembler is a translator which
converts assembly level language into machine level language and vice versa.
13.6 References
Contents:
The main aim of this lesson is to learn the concept of micro operations and its
execution in registers. Various micro operations such as Arithmetic and Logical micro
operations are discussed in this lesson in detail.
14.1 Introduction
The equivalent machine code for pneumonic codes are given in the table below
107
Hexadecimal Code
Location Content Symbolic Program
100 2107 ORG 100
101 7170 LDA SUB
102 7017 CMA
103 1106 INC
104 3108 ADD MIN
105 7001 STA DIF
106 0053 MIN, HLT
107 FFE9 SUB, DEC 83
108 0000 DIF, DEC -23
HEX 0
END
A symbolic language
A convenient tool for describing the internal organization of digital computers
Can also be used to facilitate the design process of digital systems.
Designation Of Registers
Registers may also be represented showing the bits of data they contain
Designation of a register
a register
portion of a register
a bit of a register
108
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
In this case the contents of register R2 are copied (loaded) into register R1
A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
Note that this is a non-destructive; i.e. the contents of R1 are not altered by
copying (loading) them to R2
the data lines from the source register (R5) to the destination register (R3)
Parallel load in the destination register (R3)
Control lines to perform the action
Control Functions
P: R2 R1
Which means if P = 1, then load the contents of register R1 into register R2, i.e., if
(P = 1) then (R2 R1)
109
P: R2 R1
t t+1
Clock
Load
The same clock controls the circuits that generate the control function and the
destination register
Registers are assumed to use positive-edge-triggered flip-flops
If two or more operations are to occur simultaneously, they are separated with
commas
P: R3 R5, MAR IR
Here, if the control function P = 1, load the contents of R5 into R3, and at the same
time (clock), load the contents of register IR into register MAR
14.2.3 ALU
Addition
Subtraction
Increment
Decrement
B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder C3 C2 C1 C0
FA FA FA FA
C4 S3 S2 S1 S0
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
FA FA FA FA
C4 S3 S2 S1 S0
Binary Incrementer A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1
2 MUX
3
A1 X1 C1
S1 D1
S0 FA
B1 0 4x1 Y1 C2
1
2 MUX
3
A2 X2 C2
S1 D2
S0 FA
B2 0 4x1 Y2 C3
1
2 MUX
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1
2 MUX
3 Cout
0 1
0 0 0 0 F0 = 0 F0 Clear
0 0 0 1 F1 = xy FAB AND
0 0 1 0 F2 = xy' F A B
0 0 1 1 F3 = x FA Transfer A
0 1 0 0 F4 = x'y F A B
0 1 0 1 F5 = y FB Transfer B
0 1 1 0 F6 = x y FAB Exclusive-OR
0 1 1 1 F7 = x + y F AB OR
1 0 0 0 F8 = (x + y)' F A B) NOR
1 0 0 1 F9 = (x y)' F (A B) Exclusive-NOR
1 0 1 0 F10 = y' F B Complement B
1 0 1 1 F11 = x + y' FAB
1 1 0 0 F12 = x' F A Complement A
1 1 0 1 F13 = x' + y F A B
1 1 1 0 F14 = (xy)' F (A B) NAND
1 1 1 1 F15 = 1 F all 1's Set to all 1's
Ai
0
Bi
1
4X1 Fi
MUX
2
3 Select
S1
S0
Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A Complement
Selective-set AA+B
Selective-complement AAB
Selective-clear A A B
Mask (Delete) AAB
113
Clear AAB
Insert A (A B) + C
Compare AAB
14.6 References
Contents:
The main objective of this lesson is to learn the concepts of general register
organization, the interconnectivity among registers, control word and the storage
device called as stack based on last in first out mechanism.
15.1 Introduction
The part of the computer that performs data processing operations is called the central
processing unit. It is made up of 3 major parts called as Arithmetic and logic unit
performs required microoperations for executing the instructions, the control unit
supervises the transfer of information among registers and instructs the ALU to
perform the desired operation. The stack in digital computer is a memory unit with an
address register that can count only. The register that holds the address for the stack is
called as stack pointer because its values always points at the top item in the stack.
The 2 operations performed in the stack are PUSH and POP.
When a large number of registers are included in the CPU, it is most efficient
to connect them through a common bus system.
A bus organization for seven CPU registers is shown above. The output of
each register is connected to 2 multipliers (MUX) to form the two buses A and B. The
selection lines in each multiplier select one register or the input data for the particular
bus. The A and B buses form the inputs to a common arithmetic and logical unit. The
operations selected in the ALU determine the arithmetic and logical microoperation to
be performed. The result of the microoperation is available for output data and also
goes into the inputs of all the registers.
Control Word
There are 14 binary selection inputs in the unit and their combined value specifies a
control word.
The 3 bit binary code in the first column of the table specifies the binary code for each
of the three fields. The register selected by fields SELA, SELB and SELD is the one
whose decimal number is equivalent to the binary number in the code. When SELA or
SELB is 000, the corresponding multiplexer selects the external input data. When
SELD = 000, no destination register is selected but the contents of the output bus are
available in the external output.
The ALU provides arithmetic and logical operations. In addition, the CPU must either
provide post shift operations or pre shift operations. The encoding of the ALU
operations for the CPU is given below
Stack Organization
Stack works under the principle of Last-in first-out (LIFO) in such a way that the item
stored last in the list is retrieved is first
Stack in digital computer is essentially a memory unit with an address register that
can count only(after an initial value is loaded into it).
119
Register Stack
Registers:
Stack Initialization
SP cleared to 0
EMTY set to 1
FULL cleared to 0
Push
SP SP + 1
M[SP] DR
If (SP = 0) then (FULL 1)
EMTY 0
Pop
DR M[SP]
SP SP 1
If (SP = 0) then (EMTY 1)
FULL 0
Memory Stack
Figure 15.5 Computer memory with program, data and stack segments
The stack limits can be checked by using 2 processor registers: one to hold the upper
limit (3000 an example) and the other to hold the lower limit.
As a user interface for calculation the notation was first used in Hewlett-Packard's
desktop calculators from the late 1660s and then in the HP-35 handheld scientific
calculator launched in 1672. In RPN the operands precede the operator, thus
dispensing with the need for parentheses.
Implementations of RPN are stack-based; that is, operands are popped from a stack,
and calculation results are pushed back onto it
The final result, 15, lies on the top of the stack at the end of the calculation.
A bus organization for seven CPU registers has been discussed. The concept of
control word and examples of microoperations has been discussed. Stack is a storage
device and it performs two operations in it called as Push and Pop. The sequence of
push operations and pop operations has been discussed in a series of microoperations.
The concept of stack limits and usage of stack for evaluating arithmetic expressions
has been discussed with examples.
123
15.6 References
Contents:
The main objective of this lesson is to learn the concepts of instruction formats such
as three address instructions, two address instructions etc and the various addressing
modes.
16.1 Introduction
A computer will have variety of instruction code formats. the most common fields
found in instruction formats are, an operation code fields, an address field and a mode
field. The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually referenced. The addressing
modes techniques are used for giving versatility and to reduce the number of bits in
the addressing field of instructions.
Single accumulator
General register
Stack
Single Accumulator
ADD X
AC AC + M[X]
General Register
125
PUSH X
ADD
Zero address
Pop two numbers off stack
Add them
Push result back on stack
One address instructions use an implied accumulator (AC) register for all data
manipulation
X = (A + B) * (C + D)
LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X
126
A stack-organized computer does not use an address field for the instructions ADD
and MUL
X = (A + B) * (C + D)
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
RISC Instructions
Only load and store instructions can reference memory, all other instructions can only
reference registers
RISC Instructions
X = (A + B) * (C + D)
LOAD R1, A
LOAD R2, B
LOAD R3, C
LOAD R4, D
ADD R1, R1, R2
ADD R3, R3, R4
MUL R1, R1, R3
STORE X, R1
Register indirect Mode - the register in the CPU contains the address of the location
in memory that contains the operand
Example: LD R1,@R2 R1 M[R2]
Relative Address - the address in the instruction is added to the program counter to
obtain the effective address
Example: JMP -17 ADR 17
PC M[PC+ADR]
Indexed Addressing value of index register added to address part of the instruction
to yield effective address
Example: LD R1,X(R3) ADR addr(X), R1 M[ADR+R3]
The various instruction formats such as three address, two address, one address and
zero address has been discussed with examples and various addressing modes such as
implied mode, immediate mode, Register mode, Register indirect mode, relative
addressing mode has been discussed.
16.6 References
Contents:
The main objective of the lesson is to learn the data transfer instructions, Arithmetic
Instructions and Logical instructions and the program control instructions and types of
interrupts.
17.1 Introduction
Computers give an extensive set of instructions to give the user the flexibility to carry
out various computational tasks.
The computer instructions are classified into three categories
Computers give an extensive set of instructions to give the user the flexibility to carry
out various computational tasks.
Data Transfer instructions move data from one place in the computer to another
without changing the data content. The most common transfers are between memory
and processor registers, between processor registers and input or output, and between
the processor register themselves.
The load instruction has been used to transfer from memory to a processor register.
The store instruction has been used to transfer from a processor register to memory.
The Move register has been used among multiple CPU registers to transfer from one
register to another register
It performs operations on data and provides the computational capabilities for the
computer. It is divided into 3 basic types.
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
Name Mnemonic
131
Clear CLR
Complement COM
AND AND
OR OR
Exclusive OR XOR
Clear Carry CLRC
Set carry SETC
Complement Carry COMC
Enable Interrupt E1
Disable Interrupt D1
Name Mnemonic
Logical Shift Right SHR
Logical Shift Left SHL
Arithmetic Shift Right SHRA
Arithmetic Shift Left SHLA
Rotate Right ROR
Rotate Left ROL
Rotate Right Through carry RORC
Rotate Left through Carry ROLC
Use a special status or flag register, called a Program Status Word (PSW), to store the
results of an instruction (such as compare).
Subsequent instructions can test the bits in the status work and branch depending on
the value.
Bit C is set to 1 if the end carry is 1; cleared to 0 if the carry is 0.
Bit S (sign) is set to 1 if the highest bit in the AC is 1; 0 otherwise
Bit Z set to 1 after previous load of a register has a value of zero
Bit V(overflow) is set to 1 if XOR of the last 2 carriess is equal to 1 and
cleared to 0
Subroutine Call and Return
Assume that there exists a stack and that a register (SP) points to the top of the stack.
Call
JSR X
SP SP -1
M[SP] PC
PC effective address
Return
RTN PC M[SP]
SP SP + 1
132
Interrupts
The concept of program interrupt is used to handle a variety of problems that arise out
of normal program, sequence
Program Status Word Collection of all status bit conditions in the CPU.
Bit I is 1 if Interrupts are enabled
Bit S is 1 if in supervisory mode
Supervisory mode
1. special instructions can be executed
2. set when running in O/S
3. results from an interrupt C S Z V I S
Interrupt Vector
Types of Interrupts
1. External Interrupt come from an input output devices, from a timing device
Example of External Interrupts are
I/O device requesting transfer of data
Elapse time of an event
Power failure
I/O device finished transfer of data
2. Internal interrupt arise from illegal or erroneous use of an instruction or data. They
are also called as Traps.
Examples of Internal Interrupts are
Register Overflow
Attempt to divide by zero
Invalid Operation Code
Stack Overflow
This lesson covered the three categories of computer instructions and its mnemonic
codes. The concept of status bit register has been explained by a diagrammatic
representation. The concepts of subroutine calls and return and types of interrupts has
been discussed.
The collection of all status bit conditions in the CPU is called as a Program Status
Word.
17.6 References
UNIT V
Lesson 18: Input Output Organization and Memories: Peripheral Devices,
Input-Output Interface, and Asynchronous Data Transfer
Contents:
The aim of this lesson is learn about peripheral devices such as monitor, keyboard,
printer, magnetic tape, disk etc and the method of transferring information between
internal storage and external I/O devices and the various synchronous data transfer
methods has been discussed.
18.1 Introduction
Data Bus
Source Destination
Strobe
Initiated by destination
Destination activates strobe
Source places data on the bus
Keeps data until accept them by destination
Reads data to a register (Generally at falling edge of the strobe)
Destination disable strobe
Source removes data after predetermined time
Data Bus
Source Destination
Strobe
Strobe disadvantage
In source initiation - Source doesnt know whether destination got the data
In destination initiation Destination doesnt know whether source has
placed the data on the bus
Handshaking introduce a reply method to solve this problem
141
Two-Wired Handshaking
Parallel transmission
Each bit of message has its own path
Total message transmitted at the same time
N bit message requires N conduction paths
Faster/expensive
Short distance transmission
Serial transmission
Each bit in message sent in sequence one at a time
Uses only one pair of conductors (or one conductor with a common
ground
Slower/cheaper
Uses for long distance transmission
Synchronous
Uses common clock frequency
Transmits bits continuously
For long distance transmission
Use separate clocks with same frequency
Keep clocks in step via synchronization signals send
periodically
Periodic synchronization signals should transfer even no data to
transmit
Asynchronous
Transmits only when data available to transmit
Otherwise keeps in idle
Uses start and stop bits at the both ends of the character code
Transmission line rests at state 1 while idle
Start bit is always 0
Stop bit can be 1 or more 1s
Transmission Rules
Working Principle
Using transmission rules receiver detects start bit when line goes 1 to 0
Receiver knows
o Bit transmission rate
o Number of bits in character
After a character transmission line keeps at state 1 for at least one or two bits
for resynchronization at both transmitter and receiver
Ex: Transmission rate 10 characters/sec (at 1 start bit, 8 info bits and 2 stop
bits) (1+8+2)*10 bit/s 110 bit/s i.e. baud rate 110 baud
Definitions
Mode of operation
Baud rate to use
Bits in each character
No of stops bits should append
Whether to use parity check
Status Register
2 bit Flags
o Transmit register is empty
o Receiver register is full
18.6 References
Contents:
The main aim of this lesson is to learn various modes of transfer between central
computer and I/O devices and various priority interrupts and servicing methods.
19.1 Introduction
Various modes of transfer are Programmed I/O, Interrupt Initiated I/O and DMA.
Programmed I/O operations are result of the I/O instructions written in the computer
program. Interrupt is initiated when the data for the device is ready and in the DMA
process the interface transfers data into and out of the memory unit through the
memory bus.
Binary information received from an external device is usually stored in memory for
later processing. CPU merely executes instruction and accepts data temporally from
I/O devices but the ultimate source and destination is memory unit.
Receiving data from input devices stores in memory
Sending data to output devices from memory
I/O handling modes
Programmed I/O
Interrupt-initiated I/O
Direct Memory Access (DMA)
19.2.3.1 Polling
Inputs Outputs
Boolean function
I0 I1 I2 I3 x y IST
1 x x x 0 0 1
0 1 x x 0 1 1 x = I0 I1
0 0 1 x 1 0 1 x = I0 I1 + I0 I2
0 0 0 1 1 1 1 (IST) = I0 + I1 + I2 + I3
0 0 0 0 1 1 0
Software Routines
Various modes of transfer have been discussed in detail with flowchart and examples.
Concept of priority interrupt and its various methods of servicing th einterrupt has
been discussed.
19.6 References
The main aim of this lesson is to learn the principles of DMA and IO processor.
20.1 Introduction
DMA is a technique that lets the peripheral device manage the memory buses directly
to improve the speed of transfer. The DMA controller is an Interface with CPU and
I/O devices. DMA can have even more than one channel and is commonly used in
devices like magnetic disks and screen display. IOP is similar to CPU except its
handles only I/O processing. Unlike DMA controller totally setup by the CPU, IOP
can fetch and executes its own instructions
The transfer of data between a fast storage device such as magnetic disk and
memory is often limited by the speed of the CPU. Removing CPU from the path and
letting the peripheral device manage the memory buses directly would improve the
speed of transfer. This transfer technique is called direct memory access.
The two control signals in the CPU that facilitate the DMA transfer are
a. Bus request
b. Bus grant
Bus Request (BR) input is used by the DMA controller to request the CPU to
relinquish control of the buses.
When this input is active, the CPU terminates the execution of the current instruction
and place the address bus, the data bus, and the read and write lines into a high
impedance state.
Bus grant (BG), the CPU activates the bus grant output to inform the external DMA
tat the buses are in high impedance state.
Burst transfer: when the DMA takes control of the bus system, it communiates
directly with the memory. The transfer can be made in several ways. In DMA burst
transfer, a block sequence consisting of a number of memory words is transferred in a
153
continuous burst while the DMA controller is master of the memory buses. This mode
of transfer is need for fast devices such as magnetic devices.
Cycle stealing: this allows the DMA controller to transfer one data word at a time,
after which it must return control of the buses to the CPU. The CPU merely delays its
operation for one memory cycle to allow the direct memory I/O transfer to steal one
memory cycle.
The DMA controller needs the usual circuits of an interface to communicate with the
CPU and I/O device.
DMA can start data transfer between memory and peripheral device as it gets the
control command
The address register and address lines are used for direct communication with the
memory. The registers are selected by the CPU through the address bus by enabling
the DS(DMA select) and RS(register select) inputs.
The RD(read) and WR(write) inputs are bidirectional. When the BG input is 0, the
CPU can communicate with the DMA registers through the data bus to read from or
to write to the DMA registers. When the BG=1, the CPU has relinquished
the buses and the DMA can communicate with the memory by specifying an address
in the address bus and activating the RD and WR control. The CPU initializes the
DMA and then it starts and transfers data between memory and peripheral until an
entire block is transferred.
The CPU initializes the DMA by sending the following information through the data
bus:
1. The starting address of the memory blocks where data are available or where
data are to be stored.
2. the word count, which is the number of words in the memory block
3. control to specify the mode of transfer such as read or write
4. a control to start the DMA transfer
The starting address is stored in the address register. The word count is stored in the
word count register, and the control information in the control register. Once the
DMA initialized, the CPU stops communicating with the DMA
155
Unlike DMA controller totally setup by the CPU, IOP can fetch and executes
its own instructions
Additionally IOP can perform other tasks like arithmetic, logic, branching and
code translation
Responsibilities of IOP
Memory at the centre can communicate with both processors via DMA
CPU responsible for data processing and computational tasks
IOP transfers data between peripheral devices and memory
CPU is usually assigned the task of initiating the I/O program, there after IOP
operates independently
IOP take care of data format difference and structure mapping between
memory and various I/O devices
Communication between CPU and IOP is similar to programmed I/O
Communication between Memory and IOP is done as DMA
IOP can be independent or slave processors depending on the sophistication of
the system
Instructions for IOP generally refers as commands
is often limited by the speed of the CPU. In DMA transfer the peripheral devices
manages the memory buses directly. The DMA transfer and DMA controller
functions have been discussed in detail. The IOP is similar to CPY except that it is
designed to handle the details of I/O processing.
1.Explain how DMA controller is used to speed up the data transfer rate.
2.What is IOP? How is it different from CPU? Explain its functionalities.
Bus Request (BR) input is used by the DMA controller to request the CPU to
relinquish control of the buses.
Bus grant (BG), the CPU activates the bus grant output to inform the external DMA
tat the buses are in high impedance state.
Burst transfer: In DMA burst transfer, a block sequence consisting of a number of
memory words is transferred in a continuous burst while the DMA controller is
master of the memory buses. This mode of transfer is need for fast devices such as
magnetic devices.
Cycle stealing: This allows the DMA controller to transfer one data word at a time,
after which it must return control of the buses to the CPU. The CPU merely delays its
operation for one memory cycle to allow the direct memory I/O transfer to steal one
memory cycle.
20.4 References
Contents:
The main objective of this lesson is to learn the memory hierarchy and the need
for the expandable , fast memory to meet the needs of the user.
21.1 Introduction
The memory unit is an essential component in any digital computer for storing
programs and data. The memory unit that directly communicates directly with the
CPU is called as Main memory and the backup storage devices are called as Auxiliary
devices. Cache memory is used to speed up the processing performance. Virtual
memory helps in accommodating a very large program in memory.
Memory stores input for and output from the CPU as well as the instructions
that are followed by the CPU
the amount stored is measured in bits, bytes, Kbytes (K, Kb, 103 bytes),
Megabytes (Mb, 106 bytes), Gigabytes (Gb, 109), Terabytes (Tb, 1012)
there are two kinds of memory:
main memory (or internal or primary memory) is essential for the operation of
the computer, all data and
Instructions must be in main memory first before it can be processed by the
computer
o most costly memory
o in the form of microchips integrated with the computer's central
processor
159
Magnetic
Tapes
Cache
CPU
Storage Media
Fixed Disks
Dismountable Devices
o floppy diskettes
up to 1.44 Megabytes for PC - random access
o magnetic tapes
tens of Megabytes for standard tape
access is sequential, not random
can take minutes to reach a particular set of data on the tape,
depending on where it is stored
o optical compact disks (CDs)
around 250 Megabytes per CD
random access, but the delay in reaching a given item of data
may be 1 second or more
Volumes
a volume is a single tape, CD, diskette or fixed disk, i.e. a physical unit of
storage
Files
The common auxiliary memory devices used in computer system are Magnetic Disks
and Tapes. The important characteristics of any device are
Access Mode
Access Time
Transfer Rate
Capacity
Cost
The average time required to reach a storage location in memory and obtain its
contents is called the access time.
Bits are recorded as magnetic spots on the surface as it passes a stationary mechanism
called a Write Head.
Stored Bits are detected by a change in magnetic field produced by a recorded spot on
the surface a it passes through a Read Head.
Magnetic Disk
161
A disk arm consists of platters or plates coated with magnetized material. The arm
assembly moved inside or outside. The spindle contains high rotating plates. It can
rotate and the plates and every disk surface contains a R/W head which helps in
reading or writing information into the disk.
1. Head movement from current position to desired cylinder: Seek time (0-10s ms).
The movement of R/W head from one track to another track is called as Seek Time.
2. Disk rotation until the desired sector arrives under the head: Rotational latency (0-
10s ms)
3. Disk rotation until sector has passed under the head: Data transfer time (< 1 ms)
Magnetic Tape
162
The Tape itself is a plastic coated with magnetic recording medium. Bits are recorded
as magnetic spots on the tape along several tracks. R/W heads are mounted one in
each track so the data can be recorded and read as a sequence of characters.
Magnetic tapes can be stopped, started to move forward or in reverse. Information
recorded in blocks called as records. Records may be of Fixed length or variable
length.
Many data processing require the search of items in a table stored in memory. In
general the search procedure involves, choosing the addresses, reading the content of
the address, and comparing the information with the key item. The searching
continues until the search is successful or a failure occurs.
The time required to find a item stored in memory can be reduced considerable if
stored data can be identified by the content of the data rather than by an address. A
memory unit accessed by content is called as associative memory or content
addressable memory.
It is uniquely suited for parallel searches.
Hardware Organization
It consists of a memory array and logic m words with n bits per word.
Argument register A and key register k each have n bits, one for each bit of a word.
The match register M has m bits, one for each memory word. Each word in memory is
compared with the content of the argument registers. After the matching process
reading is accomplished
The key register provides a mask for choosing a particular field or key in the
argument word. The entire argument is compared with each memory word if the key
register contains all 1s. Otherwise, only those bits in the argument that have 1s in
their corresponding position of the key register are compared.
163
Input
Output
Argument 101 111100
A
Key K 111 000000
(mask)
Word 1 100 111100 no
match
Word 2 101 000001 match
The K and A register has the following bits. Only the left most bits of A are compared
with memory words because K has 1s in three positions. Word 2 matches.
164
A1 Ai An
K1 Ki Kn
Word m Cm Cmi Cm Mm
Read Operation
If more than one word in memory matches the unmasked argument field, all the
matched words will have 1s in the corresponding bit position of the match register. It
is then necessary to scan the bits of the match register one at a time. The matched
words are read in sequence by applying a read signal to each word line whose
corresponding Mi bit as 1.
Write Operation
An associative memory must have a write capability for storing the information to be
searched. Writing in an associative memory can take different forms, depending on
the application.
165
Locality of reference
Memory references at any given interval of time tend to be confined within a few
localized areas in memory
Cache memory
Fast, small memory with fastest access speed compared to other memory types
166
Hit ratio
21.2.3.1 Mapping
Associative Mapping
Direct Mapping
Set Associative Mapping
The Above figure shows a conceptual implementation of a cache memory. This system is
called set associative because the cache is partitioned into distinct sets of blocks, ad each
set contains a small fixed number of blocks. The sets are represented by the rows in the
figure. In this case, the cache has N sets, and each set contains four blocks. When an
access occurs to this cache, the cache controller does not search the entire cache looking
for a match. Instead, the controller maps the address to a particular set of the cache and
searches only the set for a match.
If the block is in the cache, it is guaranteed to be in the set that is searched. Hence, if the
block is not in that set, the block is not present in the cache, and the cache controller
searches no further.
167
The most obvious way of relating cached data to the main memory address is to store
both memory address and data together in the cache. This the fully associative mapping
approach. A fully associative cache requires the cache to be composed of associative
memory holding both the memory address and the data for each cached line. The
incoming memory address is simultaneously compared with all stored addresses using the
internal logic of the associative memory, as shown in the diagram of conceptual
implementation. If a match is found, the corresponding data is read out. Single words
form anywhere within the main memory could be held in the cache, if the associative part
of the cache is capable of holding a full address.
The address from the processor is divided into tow fields, a tag and an index. The tag
consists of the higher significant bits of the address, which are stored with the data.
The index is the lower significant bits of the address used to address the cache.
168
When the memory is referenced, the index is first used to access a word in the cache.
Then the tag stored in the accessed word is read and compared with the tag in the address.
If the two tags are the same, indicating that the word is the one required, access is made to
the addressed cache word. However, if the tags are not the same, indicating that the
required word is not in the cache, reference is made to the main memory to find it. For a
memory read operation, the word is then transferred into the cache where it is accessed. It
is possible to pass the information to the cache and the processor simultaneously, i.e., to
read-through the cache, on a miss. The cache location is altered for a write operation. The
main memory may be altered at the same time (write-through) or later.
In the direct scheme, all words stored in the cache must have different indices. The tags
may be the same or different. In the fully associative scheme, blocks can displace any
other block and can be placed anywhere, but the cost of the fully associative memories
operate relatively slowly.
Set-associative mapping allows limited number of blocks, with the same index and
different tags, in the cache and can therefore be considered as a compromise between a
fully associative cache and a direct mapped cache. The cache is divided into "sets" of
blocks. A four-way set associative cache would have four blocks in each set. The number
of blocks in a set is known as the associativity or set size. Each block in each set has a
stored tag which, together with the index, completes the identification of the block. First,
the index of the address from the processor is used to access the set. Then, comparators
are used to compare all tags of the selected set with the incoming tag. If a match is found,
the corresponding location is accessed, other wise, as before, an access to the main
memory is made.
169
The tag address bits are always chosen to be the most significant bits of the full address,
the block address bits are the next significant bits and the word/byte address bits form the
least significant bits as this spreads out consecutive man memory blocks throughout
consecutive sets in the cache. This addressing format is known as bit selection and is used
by all known systems. In a set-associative cache it would be possible to have the set
address bits as the most significant bits of the address and the block address bits as the
next significant, with the word within the block as the least significant bits, or with the
block address bits as the least significant bits and the word within the block as the middle
bits.
The association between the stored tags and the incoming tag is done using comparators
and can be shared for each associative search, and all the information, tags and data, can
be stored in ordinary random access memory. The number of comparators required in the
set-associative cache is given by the number of blocks in a set, not the number of blocks
in all, as in a fully associative memory. The set can be selected quickly and all the blocks
of the set can be read out simultaneously with the tags before waiting for the tag
comparisons to be made. After a tag has been identified, the corresponding block can be
selected.
The replacement algorithm for set-associative mapping need only consider the lines in
one set, as the choice of set is predetermined by the index in the address. Hence, with two
blocks in each set, for example, only one additional bit is necessary in each set to identify
the block to replace.
Replacement policy
When the required word of a block is not held in the cache, we have seen that it is
necessary to transfer the block from the main memory into the cache, displacing an
existing block if the cache is full. Except for direct mapping, which does not allow a
replacement algorithm, the existing block in the cache is chosen by a replacement
algorithm. The replacement mechanism must be implemented totally in hardware,
preferably such that the selection can be made completely during the main memory cycle
170
for fetching the new block. Ideally, the block replaced will not be needed again in the
future.
A true random replacement algorithm would select a block to replace in a totally random
order, with no regard to memory references or previous selections.
The first-in first-out replacement algorithm removes the block that has been in the cache
for the longest time. The first-in first-out algorithm would naturally be implemented with
a first-in first-out queue of block address.
In the least recently used (LRU) algorithm, the block which has not been referenced for
the longest time is removed from the cache.
Virtual memory is a concept used in some large computer systems that permit the user to
construct programs as though large memory space were available equal to the totality of
the auxiliary memory. At any time only a part of the program will reside in main memory,
and other parts will otherwise remain on hard disk and may be switched into memory
later if needed.
Address Space
Memory Space
Address space refers to the address generated by programs and the memory space refers
to the actual physical locations.
171
Figure 21.11 Relation between address and memory space in a virtual memory
The mapping is a dynamic operation, which means that every address is translated
immediately as a word is referenced by CPU.
Paging
In Paging memory management, each process is associated with a page table. Each
entry in the table contains the frame number of the corresponding page in the virtual
address space of the process. This same page table is also the central data structure for
virtual memory mechanism based on paging.
Control bits
Since only some pages of a process may be in main memory, a bit in the page table
entry, P in below Figure, is used to indicate whether the corresponding page is present
in main memory or not.
Another control bit needed in the page table entry is a modified bit, M, indicating
whether the content of the corresponding page have been altered or not since the page
was last loaded into main memory. This is often said swapping in and swapping out,
suggesting that a process is typically separated into two parts, one residing in main
memory and the other in secondary memory, and some pages may be removed from
172
one part and join the other. They together make up of the whole process image.
Actually the secondary memory contains the whole image of the process and part of it
may have been loaded into main memory. When swapping out is to be performed,
typically the page to be swapped out may be simply overwritten by the new page,
since the corresponding page is already on secondary memory. However sometimes
the content of a page may have been altered at runtime, say a page containing data. In
this case, the alteration should be reflected in secondary memory. So when the M bit
is 1, then the page to be swapped.
21.6 References