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M48T08 M48T08Y, M48T18 5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER ® SRAM Features

M48T08

M48T08Y, M48T18

5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER ® SRAM

Features

Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery

BYTEWIDE RAM-like clock access

BCD coded year, month, day, date, hours, minutes, and seconds

Typical clock accuracy of ±1 minute a month, at 25 °C

Automatic power-fail chip deselect and WRITE protection

WRITE protect V PFD = power-fail deselect voltage):

– M48T08: V CC = 4.75 to 5.5 V;

4.5 V V PFD 4.75 V

– M48T18/T08Y: V CC = 4.5 to 5.5 V;

4.2 V V PFD 4.5 V

Software controlled clock calibration for high accuracy applications

Self-contained battery and crystal in the CAPHAT DIP package

Packaging includes a 28-lead SOIC and SNAPHAT ® top (to be ordered separately)

SOIC package provides direct connection for a snaphat top which contains the battery and crystal

Pin and function compatible with DS1643 and JEDEC standard 8 K x 8 SRAMs

RoHS compliant

– Lead-free second level interconnect

2 8 1 PCDIP28 battery/crystal CAPHAT™ SNAPHAT ® battery/crystal 2 8 1 SOH28

2 8

1

PCDIP28

battery/crystal

CAPHAT™

SNAPHAT ®

battery/crystal

2 8 1 PCDIP28 battery/crystal CAPHAT™ SNAPHAT ® battery/crystal 2 8 1 SOH28

2 8

2 8 1 PCDIP28 battery/crystal CAPHAT™ SNAPHAT ® battery/crystal 2 8 1 SOH28

1

SOH28

June 2011

Doc ID 2411 Rev 11

1/31

Contents

M48T08, M48T08Y, M48T18

Contents

1 Description

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2 Operation modes

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2.1 READ mode

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2.2 WRITE mode

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2.3 Data retention mode

 

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2.4 Power-fail interrupt pin

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3 Clock operations

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3.1 Reading the clock

 

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3.2 Setting the clock

 

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3.3 Stopping and starting the oscillator

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3.4 Calibrating the clock

 

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3.5 V CC noise and negative going transients

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18

4 Maximum ratings

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19

5 DC and AC parameters

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6 Package mechanical data

 

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7 Part numbering

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27

8 Environmental information

 

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9 Revision history

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2/31

Doc ID 2411 Rev 11

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M48T08, M48T08Y, M48T18

List of tables

List of tables

Table 1.

Signal names

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Table 2.

Table 3.

. READ mode AC characteristics

Operating modes

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10

8

Table 4.

WRITE mode AC characteristics

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Table 5.

Table 6.

. Absolute maximum ratings

Register map

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15

Table 7.

Table 8.

Operating and AC measurement

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Capacitance

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characteristics

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20

20

Table 9.

DC

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Table 10.

Table 11.

Table 12.

Power down/up AC

Power down/up trip points DC characteristics

PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data

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22

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Table 13.

SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT ® , package mech.

24

Table 14.

SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package mech. data

25

Table 15.

SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, package mech. data

 

26

Table 16.

Ordering information scheme

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. 27

Table 17.

SNAPHAT®

battery table

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Table 18.

Document revision history

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. . . . . . . . . . . . . . . .

Doc ID 2411 Rev 11

3/31

List of figures

M48T08, M48T08Y, M48T18

List of figures

Figure 1.

Logic diagram

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5

Figure 2.

DIP connections

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6

Figure 3.

SOIC

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6

Figure 4.

Figure 5.

Figure 6.

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. WRITE enable controlled, WRITE AC waveform

READ

Block diagram

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. mode AC waveforms

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9

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Figure 7.

Chip enable controlled, WRITE AC waveforms

11

Figure 8.

Crystal accuracy across temperature

17

Figure 9.

Clock calibration

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Figure 10.

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Figure 11.

Figure 12.

Supply voltage protection AC testing load circuit

. Power down/up mode AC

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Figure 13.

PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline

 

23

Figure 14.

SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT ® , package

24

Figure 15.

SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package

25

Figure 16.

SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, package

26

Figure 17.

Recycling symbols

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Doc ID 2411 Rev 11

. . . . . . . . . . . . . . . .

M48T08, M48T08Y, M48T18

Description

1

Description

The M48T08/18/08Y TIMEKEEPER ® RAM is an 8 K x 8 non-volatile static RAM and real- time clock which is pin and function compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution.

The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

The 28-pin, 600 mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal and a long-life lithium button cell in a single package.

The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT ® housing containing the battery and crystal. The unique design allows the SNAPHAT ® battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT ® housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT ® housing is keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT ® ) part number is “M4T28-BR12SH” or “M4T32-BR12SH”.

Figure 1.

Logic diagram

V CC

13 8 A0-A12 DQ0-DQ7 W M48T08 M48T08Y E1 INT M48T18 E2 G
13
8
A0-A12
DQ0-DQ7
W
M48T08
M48T08Y
E1
INT
M48T18
E2
G

V SS

AI01020

V CC 13 8 A0-A12 DQ0-DQ7 W M48T08 M48T08Y E1 INT M48T18 E2 G V SS

Doc ID 2411 Rev 11

5/31

Description

M48T08, M48T08Y, M48T18

Table 1.

Signal names

A0-A12

Address inputs

DQ0-DQ7

Data inputs / outputs

 

INT

Power fail interrupt (open drain)

E1

Chip enable 1

E2

Chip enable 2

G

Output enable

W

WRITE enable

V

CC

Supply voltage

V

SS

Ground

6/31

Figure 2.

DIP connections

V SS Ground 6/31 Figure 2. DIP connections INT 1 2 8 V CC A12 2
INT 1 2 8 V CC A12 2 27 W A7 3 26 E2 A6
INT
1
2
8
V
CC
A12
2
27
W
A7
3
26
E2
A6
4
25
A
8
A5
5
24
A9
A4
6
2
3
A11
A
3
7
22
G
M4 8 T0 8
A2
8
M48 T1 8
21
A10
A1
9
20
E1
A0
10
19
DQ7
DQ0
11
1
8
DQ6
DQ1
12
17
DQ5
DQ2
1
3
16
DQ4
V
14
15
DQ 3
SS

AI011 8 2

Figure 3.

SOIC connections

V 14 15 DQ 3 SS AI011 8 2 Figure 3. SOIC connections INT 1 28
INT 1 28 V CC A12 2 27 W A7 3 26 E2 A6 4
INT
1 28
V
CC
A12
2 27
W
A7
3 26
E2
A6
4 25
A8
A5
5 24
A9
A4
6 23
A11
A3
7 22
G
8 M48T08Y
A2
21
A10
A1
9 20
E1
A0
10 19
DQ7
DQ0
11 18
DQ6
DQ1
12 17
DQ5
DQ2
13 16
DQ4
V
14 15
DQ3
SS

AI01021B

Doc ID 2411 Rev 11

9 20 E1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2

M48T08, M48T08Y, M48T18

Description

Figure 4. Block diagram O SCILLATOR AND CLOCK CHAIN 8 x 8 BiPORT S RAM
Figure 4.
Block diagram
O
SCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
S RAM ARRAY
3
2,76 8 Hz
CRY S TAL
A0-A12
POWER
DQ0-DQ7
8
1 8 4 x 8
S
RAM ARRAY
LITHIUM
CELL
E1
VOLTAGE S ENS E
AND
E2
V
PFD
W
S
WITCHING
CIRCUITRY
G
V
INT
CC
V SS
AI01 333
E1 VOLTAGE S ENS E AND E2 V PFD W S WITCHING CIRCUITRY G V INT

Doc ID 2411 Rev 11

7/31

Operation modes

M48T08, M48T08Y, M48T18

2 Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.

The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out-of-tolerance condition. When V CC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V CC . As V CC falls below the battery backup switchover voltage (V SO ), the control circuitry connects the battery which maintains data and clock operation until valid power returns.

Table 2.

Operating modes

Mode

 

V

CC

E1

E2

G

W

DQ0-DQ7

Power

Deselect

 

V

IH

X

X

X

High Z

Standby

Deselect

4.75 to 5.5 V or 4.5 to 5.5 V

X

V

IL

X

X

High Z

Standby

WRITE

V

IL

V

IH

X

V

IL

D

IN

Active

READ

V

IL

V

IH

V

IL

V

IH

D

OUT

Active

READ

 

V

IL

V

IH

V

IH

V

IH

High Z

Active

   

V

SO

to

           

Deselect

V

PFD

(min) (1)

X

X

X

X

High Z

CMOS standby

Deselect

V SO (1)

X

X

X

X

High Z

Battery backup mode

Note:

8/31

1. See Table 11 on page 22 for details.

X = V IH or V IL ; V SO = Battery backup switchover voltage.

Doc ID 2411 Rev 11

on page 22 for details. X = V I H or V I L ; V

M48T08, M48T08Y, M48T18

Operation modes

2.1 READ mode

The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access

time (t AVQV ) after the last address input signal is stable, providing that the E1, E2, and G

access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the chip enable access times (t E1LQV or t E2HQV ) or output enable access time (t GLQV ).

The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the outputs are activated before t AVQV , the data lines will be driven to an indeterminate state

until t AVQV . If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for output data hold time (t