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MB Encoding
Evaluate the proposed architecture by comparing it with the conventional BCU architecture 3 bits 2
twiddle factors
NR4SD
PP1 Generator
Pre-encoded
encoding
Partial Product
NR4SD
B cor 3 bits NR4SD 2
Generator PP2 Generator encoding
and the addition and subtraction of the result with a second variable , as shown in Fig. 1 below CSA Tree Multiplier B
CSA Tree
- CS output
C S
C S C S
xk +
Xk P=AB P=AB
+ D P=AB
+
(a) (b)
Fig. 3: (a) Modified Booth Multiplier, (b) NR4SD pre-encoded multiplier
yk - + D Yk We have implemented four designs, where the first two use the conventional architecture, as shown in
Fig. 2(a), and differentiate in the type of multipliers they use, Modified Booth and NR4SD multipliers, and
j 2a the last two designs, use the proposed Gauss Algorithm architecture and similarly differentiate in the
W e a
N
N
type of multipliers they use.
0 = ( ) 1.2
1.0
1 = ( )
0.8
2 = ( + )
0.6
0.4
The result of the complex multiplication is produced after adding M0 and M1 for the real part of the 0.2
result ( = 0 + 1 ), and M0 and M2 for the imaginary part ( = 0 + 2 ). 0.0
16 24 32 48 64
Input bit-width
Conventional and Proposed Architectures
Conventional MB Conventional NR4SD Gauss MB Gauss NR4SD
Conventional and Proposed Architectures are pipelined as shown in Fig. 2
yR yI yR
Subtrac t- Gain in Conventional architecture of NR4SD over MB
+
Multiply Unit
- yI
25.00
yI yR CS to MB
D D D D D D D D D D D D D D D D
+ + - - + + + + + + + + + + + + 10.00
4:2 Adder 4:2 Adder 4:2 Adder 4:2 Adder
xR D xI D xR D xI D
5.00
+ + + - - + + + + - - + + + + - - + + + + - - +
CSA CSA CSA CSA
0.00
CSA CSA CSA CSA
16 bits 24 bits 32 bits 48 bits 64 bits
CLA Adder CLA Adder CLA Adder CLA Adder CLA Adder CLA Adder CLA Adder CLA Adder Input bit-width
XR YR XI YI XR YR XI YI Area Power
(a) (b)
Fig. 2: (a) BCU Conventional Design, (b) BCU Gauss Algorithm Design Gain of Gauss with NR4SD over Conventional with MB
25.00
Conclusions 20.00
We have presented efficient designs for the FFT decimation-in-time (DIT), radix-2, Butterfly Unit, in
Gain (%)
15.00
terms of delay, area and power consumption. The proposed design BCU_Conv_2, which uses the
Conventional complex number multiplication algorithm and CS NR4SD multipliers, yields gain 5% in 10.00
the delay, 18% less area and 18% less power dissipation in average, compared to the Conventional
5.00
(BCU_Conv_1). We have also presented an alternative and efficient design (BCU_Gauss_2),
according to the Gauss complex multiplication algorithm, which is more suitable for low power and 0.00
area efficient applications, that presents a mean gain of 18% in area complexity and 13% in power 16 bits 24 bits 32 bits 48 bits 64 bits
dissipation. Input bit-width
Area Power