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HIGH-LEVEL SYNTHESIS
High-level synthesis: the automatic addition of
structural information to a design described by
an algorithm.
BEHAVIORAL D. STRUCTURAL D.
Systems
Algorithms Processors
Register transfers ALUs, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer Transistors
functions
Transistor layout
Cell layout
Module layout
Floor plans
Physical partitions
PHYSICAL D.
HARDWARE MODELS
FOR HIGH-LEVEL
SYNTHESIS
All HLS systems need to restrict the target hard-
ware. The search space is too large, otherwise.
o f (i 1, i 2)
CAD TOOLS FOR VLSI
HARDWARE MODELS
(Continued)
i0 i1 i2 i3
c1
c0
o + i k , k + 2c 1 ) c 0
CAD TOOLS FOR VLSI
HARDWARE MODELS
(Continued)
* busses: a connection shared between several
hardware elements, such that only one ele-
ment can write data at a specific time.
enable
o
CAD TOOLS FOR VLSI
HARDWARE MODELS
(Continued)
Parameters defining the hardware model for the
synthesis problem:
* clocking strategy: e.g. one- or two-phase
clocks.
* interconnect: e.g. allowing or disallowing
buses.
* clocking of functional units: allowing or dis-
allowing of:
+ multicycle operations;
+ chaninig;
+ pipelined units.
CAD TOOLS FOR VLSI
HARDWARE CONCEPTS:
DATA PATH + CONTROL
Hardware is normally partitioned into two parts:
INPUT FORMAT
The algorithm, that is the input for a high-level
synthesis system, is often provided in textual
form either:
* in a conventional programming language,
such as Pascal, or
* in a hardware description language, which is
more suitable to express the parallelism pres-
ent in hardware.
INTERNAL
REPRESENTATION
Most systems use some form of a data-flow
graph. A DFG may or may not contain informa-
tion on control flow.
DATA FLOW
x := a * b; y := c + d;
z := x + y;
a b c d
x y
z
CAD TOOLS FOR VLSI
a b c d a b c d
x y x y
z z
a b c d a b c d
x y x y
z z
CAD TOOLS FOR VLSI
CONDITIONAL DATA
FLOW
* selector
T F
selector
* distributor
distributor
T F
CAD TOOLS FOR VLSI
EXPLICIT ITERATIVE
DATA FLOW
a b
T sel. F
T distr. F
while a > b
a do
a := a b;
CAD TOOLS FOR VLSI
IMPLICIT ITERATIVE
DATA FLOW
* Iteration implied by stream of input tokens
arriving at regular points in time.
* Initial tokens act as buffers.
a b a b a b
a[0] a[1] b[1] a[1]
a[0]
c[1]
c c c
T0
c
CAD TOOLS FOR VLSI
ITERATIVE DFG
EXAMPLE
+
c8 o1
m1 d1 m2
T0
c2 c4 c6 c7
+ +
m3 d2 m4
T0
i1 c1 c3 c5
+
HIGH-LEVEL
TRANSFORMATIONS
Restructuring data and control flow graphs prior
to the actual mapping onto hardware.
Examples:
* Replacing division by 2 by shift.
* Loop unrolling.
* Replacing chain of adders by a tree.
x1 x2 x3 x4 x5 x6 x7 x8
y
+ + + + + + + +
x1 x2 x3 x4 x5 x6 x7 x8
+ + + +
+ +
+
y
CAD TOOLS FOR VLSI
TERMINOLOGY
Subtasks in high-level synthesis:
* Scheduling: determine for each operation the
time at which it should be performed such
that no precedence constraint is violated.
For an edge (v i, v j): t j w t i ) i
Remarks:
* The subproblems are strongly interrelated;
they are, however, often solved separately.
* Scheduling (except for a few versions) is NP-
complete heuristics have to be used.
CAD TOOLS FOR VLSI
EXAMPLE
The second-order filter section made acyclic:
+
c8 o1
o 2(d 1)
m1 m2
c2 c4
i 2(d 1)
c6 c7
+ +
m3 o 3(d 2) m4
i1 c1 c3 i 3(d 2) c5
+
c3 c4 c5 c6
+ c1 c2 c7 c8
0 5 10
CAD TOOLS FOR VLSI
EXAMPLE (Continued)
The resulting data path after register assign-
ment:
d1
i1 r1 r2 r3 r4
ROM d2
o1
CAD TOOLS FOR VLSI
OPTIMIZATION CRITERIA
Not surprisingly, the objective function to be op-
timized is similar to the one for the design of
VLSI circuits in general. It is a combination of:
* speed: how long does it take to perform the
intended computation,
* area: the addition of the areas of all function-
al units and registers, sometimes taking the
area of interconnection into account.
SCHEDULING METHODS
* As soon as possible (ASAP):
+ an operation can be scheduled when all its
predecessors have been scheduled.
+ very simple, as data-flow graph need only
to be traversed from inputs(s) to output(s).
* List scheduling:
+ similar to ASAP; however, now an extra
criterion is used for choosing between all
operations that have all their predecessors
scheduled.
CAD TOOLS FOR VLSI
SCHEDULING METHODS
(Continued)
* Critical-path list scheduling:
+ sorting criterion is the length of the longest
path from operation to output.
+ gives good results in practice!
* Freedom-based scheduling:
+ compute both ASAP and ALAP schedules
(longest-path computations from inputs to
operation and from operation to outputs).
+ the difference in scheduling position gives
the freedom or mobility of an operation
(operations in the critical path have mobil-
ity zero).
+ take advantage of mobility to find a good
position within scheduling range.
CAD TOOLS FOR VLSI
FORCE-DIRECTED
SCHEDULING
a1 +
a1
a2 + a2
+ a3 a3
^
* a partial schedule t, is a schedule where some
transfers have a fixed time positions and oth-
ers have a scheduling range.
* the resource utilization for resource r of a
^
partial schedule t at time t is given by the dis-
^ ^
tribution function q r(t, t).
CAD TOOLS FOR VLSI
FORCE-DIRECTED
SCHEDULING (Ctd.)
* When fixing an operations time, one makes
^
a transition from partial schedule t to partial
^
schedule s.
^ ^
* For every operation a force F r(t, s), is com-
puted for every possible position within an
operations range.
* Basic force function:
^ ^
F r(t, s) + ^ ^ ^ ^ ^ ^
q r(t, t)(q r(s, t) * q r(t, t))
trange(op)
* The lowest force determines which operation
is scheduled and at which position.
CAD TOOLS FOR VLSI
THE ASSIGNMENT
PROBLEM
Subtasks in assignment:
* operation-to-FU assignment
* value grouping
* value-to-register assignment
* transfer-to-wire assignment
* wire to FU-port assignment
ASSIGNMENT BY CLIQUE
PARTITIONING
* Tasks are compatible when they can be
executed on the same agent simultaneously
compatiblity graph.
* A clique is a maximal complete subgraph.
* Clique partitioning divides the vertices of a
graph into complete subgraphs.
v1
v1
v4 v5 v4 C 3 v5
v0 v0
C1 C4
v2 v7 C0 v7
v2
v3 v6 v3 v6
C2
(a) (b)
while Eck 6= ; do
begin
\nd vi; vj with largest set of common neighbors";
N := \set of common neighbors of vi and vj ";
s := i [ j ;
Vc
k+1 := V k [ fvsg n fvi ; vj g;
c
Ec
k +1 := ;;
for each (vm ; vn ) 2 Eck do
if vm 6= vi ^ vm 6= vj ^ vn 6= vi ^ vn 6= vj
then Eck+1 := Eck+1 [ f(vm ; vn )g;
for each vn 2 N do
Ec
k+1 := E k+1 [ f(vn ; vs)g;
c
k := k + 1
end
CAD TOOLS FOR VLSI
CLIQUE-PARTITIONING
EXAMPLE
v1 v0,1
v4 v5 v5
v0 v4
v2 v2
v7 v7
v3 v6 v3 v6
(a) (b)
v0,1,2
v0,1,2
v4 v5,6
v4 v5
v7
v7
v3
v3 v6
(c) (d)
v0,1,2,3 v0,1,2,3
v4 v5,6 v4 v5,6,7
v7
(e) (f)
CAD TOOLS FOR VLSI
HIGH-LEVEL
TRANSFORMATIONS
Restructuring data and control flow graphs prior
to the actual mapping onto hardware.
Examples:
* Replacing division by 2 by shift.
* Loop unrolling.
* Replacing chain of adders by a tree.
x1 x2 x3 x4 x5 x6 x7 x8
y
+ + + + + + + +
x1 x2 x3 x4 x5 x6 x7 x8
+ + + +
+ +
+
y