Hossein Rezaei

Career Vitae

PERSONAL DETAILS
Birth June 18, 1991, Fasa, Shiraz, Iran
Gender Male
Address 1 Farjadi Koosha, Bani Hashem St, Resalat Highway, Tehran, Iran
Phone (+98) 936-275-9058
Email hossein_rezaei70@yahoo.com

EDUCATION
MSc. in Electrical Engineering 2014-2016
Iran University of Science and Technology, Tehran, Iran
Research Area: Asynchronous and Elastic Circuits, VLSI Interconnect
Thesis: Design and Simulation of a High-Performance Elastic Pipeline Considering Inter-
connect Effects
Supervisors: Dr. Abdolreza Rahmati and Dr. Soodeh Aghli Moghaddam
GPA: 18.10/20

BSc. in Electrical Engineering 2010-2014

Khatam al Anbia University of Technology, Behbahan, Iran
Thesis: Design and FPGA Implementation of a New Square Root Algorithm using ISE
Supervisor: Dr. Maryam Saremi
GPA: 16.54/20

Pre-University Certification 2009-2010

Shahid Beheshti, Fasa, Fars, Iran
GPA: 19.66/20

LANGUAGES
Farsi Native

English Toefl IBT

HONORS AND AWARDS

Elected as Secretary of the Scientific Association in Khatam al Anbia University of
Technology, 2012-2013.
Manager of the Crusher Robot Construction Project in Khatam al Anbia University of
Technology, 2012-2013.
Silver Medal in Province Karate Championship, 2003.
Gold Medal in Khatam al Anbia University of Technology Bench Press Championship, 2012.
TEACHING EXPERIENCES
Teaching Assistant at Iran University of Science and Technology: 2016-2017
VLSI Interconnects Instructor: Dr. Aghli Moghaddam
Logical Circuits - Instructor: Prof. Mohammadi

Head of Laboratory at Khatam al Anbia University of Technology: 2012-2014

Electrronic 1, 2, 3 Instructor: Dr. Rouzi Talab
Logical Circuits Instructor: M.Sc. Bastani
Pulse Technique - Instructor: M.Sc. Esmaeily Taheri
Computer Architecture - Instructor: M.Sc. Rezaei

AVR Microcontroller Course: 2012-2013

Khatam al Anbia University of Technology
Science Way Educational Institute

RESEARCH EXPERIENCES
Research Assistant at Electronic Research Center (ERC), Iran University of Science and
Technology, Tehran, Iran, 2014-Present
Neural and Cognitive Brain Sciences Laboratory (Lashgari Lab), Department of Biomedical
Engineering, Iran University of Science and Technology(www.brainscience.ir), 2015-Present

WORK EXPERIENCE
Summer Internship 2011
National Iranian Oil Co., South oil industry, Aghagary gas and oil exploitation co., South
turbine company, Overhaul department
(National Iranian Oil Company)
Telecomunication Company Aug. 2015-Now
Core/MW Front Office Engineer at ZTE Telecom. Co., Tehran, Iran
(Rightel Project)

PUBLICATIONS
H. Rezaei and S. Aghli Moghaddam, Low-swing self-timed regenerators for high-speed
and low-power on-chip global interconnects, IEEE, 24th Iranian Conference on Electrical
Engineering (ICEE), pp. 188-192, 2016.
H. Rezaei and S. Aghli Moghaddam, Implementation of high-performance and low-power
asynchronous dual-rail join using domino logic gates in 16-nm technology, IEEE, 24th
Iranian Conference on Electrical Engineering (ICEE), pp. 142-147, 2016.
H. Rezaei, S. Aghli Moghaddam and A. Rahmati, PVT analysis of an on-chip synchronous
elastic data pipeline considering interconnect effects in 16-nm technology, IEEE, 1st Inter-
national Conference on New Research achievements in Electricel and Computer Engineering,
2016, Accepted
H. Rezaei, S. Aghli Moghaddam and A. Rahmati, High-speed low-power on-chip global
interconnects using low-swing self-timed regenerators, Microelectronics Journal, vol. 58, pp.
76-82, 2016.
 H. Rezaei, S. Aghli Moghaddam and A. Rahmati, DELP: Dynamic Elastic Pipelines,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, Under review

SELECTED RESEARCH AND SIMULATION PROJECTS

Iran University of Science and Technology

Simulation of an Inductor-Less Noise-Canceling Broadband LNA in 90-nm CMOS Technology

using ADS, November 2014.
Design, Simulation and Implementation of a Discrete LNA with 0.7-dB Noise Figure using
ADS and HFSS in X Band, 2016
Literature Review and Simulation of a Quick Prediction Algorithm Using Artificial Neural
Networks using MATLAB, April 2015.
Design and Post-Layout Simulation of a Global Clock Distribution Network in 0.18-m
CMOS Technology using Cadence, July 2015.
Skin-Effect Simulation and Capacitor Extraction in VLSI Interconnects using COMSOL
Multiphysics, May 2015.
Design and Post-Layout Simulation of a High-Speed Repeater-inserted Long Interconnect
using Cadence, June 2015.
Literature Review on IEEE 1149.1 (JTAG) Boundary-Scan Standard in Altera Devices,
December 2014.
Literature Review on an Elastic Buffer Architecture (ElastiStore) for NOC Routers, May
2015.
Characteristics Study of TMS320C6713 Floating-Point Digital Signal Processor, December
2015.
Design and Simulation of XOR and XNOR Gates using Dealy Insensitive Minterm Synthesis
(DIMS) Method, October 2016.
Design, Synthesis and FPGA Implementation of Asynchronous Fibonacci Sequence using
Petrify Tool and ISE, January 2016.
Literature Review and Presentation on Design and Optimization of Asynchronous NOC
Considering Interconnect Effects, November 2016.

COMPUTER SKILLS
Hardware Description (HDL): VHDL, VERILOG
Programming: Matlab, C++, Basic
CAD Tools: Cadence, Hspice, Xilinx ISE, Modelsim
Engineering Softwares: Advanced Design System (ADS), Altium Designer, Codevision,
COMSOL Multiphysics, CST Studio, Orcad PSpice, Proteus (ISIS), HFSS
General Computer Skills: Microsoft Office, Math type, LATEX
Telecommunication Softwares: Net Newman (RAN, Core), U2000 (MW), PNMSJ (MW),
U31 (IP)

REFERENCES
Available upon request