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LCD TV
SERVICE MANUAL
CHASSIS : LJ91D

MODEL : 42LH70YD 42LH70YD-SE

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL61862401 (0905-REV01) Printed in Korea


CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ..................................................................................3

SPECIFICATION ........................................................................................6

ADJUSTMENT INSTRUCTION ...............................................................14

TROUBLE SHOOTING ............................................................................17

BLOCK DIAGRAM...................................................................................58

EXPLODED VIEW .................................................................................. 59

SVC. SHEET ...............................................................................................

Copyright LG Electronics. Inc. All right reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE


Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1W), keep the resistor 10mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed


metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
such as WATER PIPE,
shock. CONDUIT etc.
To Instruments
0.15uF
exposed
Leakage Current Cold Check(Antenna Cold Check) METALLIC PARTS
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1
measured resistance should be between 1M and 5.2M. *Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright LG Electronics. Inc. All right reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service unit under test.
manual and its supplements and addenda, read and follow the 2. After removing an electrical assembly equipped with ES
SAFETY PRECAUTIONS on page 3 of this publication. devices, place the assembly on a conductive surface such as
NOTE: If unforeseen circumstances create conflict between the aluminum foil, to prevent electrostatic charge buildup or
following servicing precautions and any of the safety precautions on exposure of the assembly.
page 3 of this publication, always follow the safety precautions. 3. Use only a grounded-tip soldering iron to solder or unsolder ES
Remember: Safety First. devices.
4. Use only an anti-static type solder removal device. Some solder
General Servicing Precautions removal devices not classified as "anti-static" can generate
1. Always unplug the receiver AC power cord from the AC power electrical charges sufficient to damage ES devices.
source before; 5. Do not use freon-propelled chemicals. These can generate
a. Removing or reinstalling any component, circuit board electrical charges sufficient to damage ES devices.
module or any other receiver assembly. 6. Do not remove a replacement ES device from its protective
b. Disconnecting or reconnecting any receiver electrical plug or package until immediately before you are ready to install it.
other electrical connection. (Most replacement ES devices are packaged with leads
c. Connecting a test substitute in parallel with an electrolytic electrically shorted together by conductive foam, aluminum foil
capacitor in the receiver. or comparable conductive material).
CAUTION: A wrong part substitution or incorrect polarity 7. Immediately before removing the protective material from the
installation of electrolytic capacitors may result in an leads of a replacement ES device, touch the protective material
explosion hazard. to the chassis or circuit assembly into which the device will be
installed.
2. Test high voltage only by measuring it with an appropriate high CAUTION: Be sure no power is applied to the chassis or circuit,
voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged
Do not test high voltage by "drawing an arc". replacement ES devices. (Otherwise harmless motion such as
3. Do not spray chemicals on or near this receiver or any of its the brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity
4. Unless specified otherwise in this service manual, clean sufficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10% (by volume) Acetone and 90% (by 1. Use a grounded-tip, low-wattage soldering iron and appropriate
volume) isopropyl alcohol (90%-99% strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500F to 600F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500F to 600F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500F to 600F)
Some semiconductor (solid-state) devices can be damaged easily b. First, hold the soldering iron tip and solder the strand against
by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors and component lead and the printed circuit foil, and hold it there
semiconductor "chip" components. The following techniques only until the solder flows onto and around both the
should be used to help reduce the incidence of component component lead and the foil.
damage caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. splashed solder with a small wire-bristle brush.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the

Copyright LG Electronics. Inc. All right reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through Circuit Board Foil Repair
which the IC leads are inserted and then bent flat against the Excessive heat applied to the copper foil of any printed circuit
circuit foil. When holes are the slotted type, the following technique board will weaken the adhesive that bonds the foil to the circuit
should be used to remove and replace the IC. When working with board causing the foil to separate from or "lift-off" the board. The
boards using the familiar round hole, use the standard technique following guidelines and procedures should be followed whenever
as outlined in paragraphs 5 and 6 above. this condition is encountered.

Removal At IC Connections
1. Desolder and straighten each IC lead in one operation by gently To repair a defective copper pattern at IC connections use the
prying up on the lead with the soldering iron tip as the solder following procedure to install a jumper wire on the copper pattern
melts. side of the circuit board. (Use this technique only on IC
2. Draw away the melted solder with an anti-static suction-type connections).
solder removal device (or with solder braid) before removing the
IC. 1. Carefully remove the damaged copper pattern with a sharp
Replacement knife. (Remove only as much copper as absolutely necessary).
1. Carefully insert the replacement IC in the circuit board. 2. carefully scratch away the solder resist and acrylic coating (if
2. Carefully bend each IC lead against the circuit foil pad and used) from the end of the remaining copper pattern.
solder it. 3. Bend a small "U" in one end of a small gauge jumper wire and
3. Clean the soldered areas with a small wire-bristle brush. carefully crimp it around the IC pin. Solder the IC connection.
(It is not necessary to reapply acrylic coating to the areas). 4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
"Small-Signal" Discrete Transistor copper pattern. Solder the overlapped area and clip off any
Removal/Replacement excess jumper wire.
1. Remove the defective transistor by clipping its leads as close as
possible to the component body. At Other Connections
2. Bend into a "U" shape the end of each of three leads remaining Use the following technique to repair the defective copper pattern
on the circuit board. at connections other than IC Pins. This technique involves the
3. Bend into a "U" shape the replacement transistor leads. installation of a jumper wire on the component side of the circuit
4. Connect the replacement transistor leads to the corresponding board.
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder 1. Remove the defective copper pattern with a sharp knife.
each connection. Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
Power Output, Transistor Device 2. Trace along the copper pattern from both sides of the pattern
Removal/Replacement break and locate the nearest component that is directly
1. Heat and remove all solder from around the transistor leads. connected to the affected copper pattern.
2. Remove the heat sink mounting screw (if so equipped). 3. Connect insulated 20-gauge jumper wire from the lead of the
3. Carefully remove the transistor from the heat sink of the circuit nearest component on one side of the pattern break to the lead
board. of the nearest component on the other side.
4. Insert new transistor in the circuit board. Carefully crimp and solder the connections.
5. Solder each transistor lead, and clip off excess lead. CAUTION: Be sure the insulated jumper wire is dressed so the
6. Replace heat sink. it does not touch components or sharp edges.

Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Copyright LG Electronics. Inc. All right reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method


This specification is applied to the LCD TV used LJ91D 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety: CE, IEC specification
2. Requirement for Test - EMC: CE, IEC specification
Each part is tested as below without special appointment.

1) Temperature : 255C (779F), CST : 405C


2) Relative Humidity : 6510%
3) Power Voltage : Standard input voltage(100~240V@50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Electrical specification
4.1 General Specification

No Item Specification Remark


1. Receiving System 1) SBTVD / NTSC / PAL-M / PAL-N
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
3. Input Voltage 1) AC 100 ~ 240V 50/60Hz Mark : 110V, 60Hz
4. Market Central and South AMERICA
5. Screen Size 32 inch Wide(1920x1080) 32LH70YD-SH
42 inch Wide(1920x1080) 42LH70YD-SE
47 inch Wide(1920x1080) 47LH70YD-SE
6. Aspect Ratio 16:9
7. Tuning System FS
8. Module LC320WUD-SBA1(Vitaz 4) 32LH70YD-SH
LC420WUD-SBT1(Vitaz 4) 42LH70YD-SE
LC470WUD-SAT1(Vitaz 4) 47LH70YD-SE
9. Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %

Copyright LG Electronics. Inc. All right reserved. -6- LGE Internal Use Only
Only for training and service purposes
5. Chromiance & Luminance spec.
42LH70YD-SE

No Item Min Typ Max Unit Remark


1. Max Luminance Module 400 500 cd/m
(Center 1-point / Full White Set
400 500 cd/m
Pattern)
2. Luminance uniformity 77 % Full white
3. Color RED X Typ. 0.637 Typ.
4. coordinate Y -0.03 0.335 +0.03
5. GREEN X 0.290
6. Y 0.606
7. BLUE X 0.145
8. Y 0.062
9. WHITE X 0.279
10. Y 0.292
11. Color coordinate uniformity N/A
Contrast ratio 1000:1 1400:1 NORMAL
70000:1 100000:1 DCR

12. Color Cool 0.274 0.276 0.278 <Test Condition>


Temperature 0.281 0.283 0.285 85% Full white pattern
Standard 0.283 0.285 0.287 ** The W/B Tolerance is
0.291 0.293 0.295 0.015 for Adjustment
Warm 0.311 0.313 0.315 Dynamic contrast : off
0.327 0.329 0.331 Dynamic color : off
OPC : off
13. Color Distortion, DG 10.0 %
14. Color Distortion, DP 10.0 deg
15. Color S/N, AM/FM 43.0 dB
16. Color Killer Sensitivity -80 dBm

6. Component Input (Y, CB/PB, CR/PR)


No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.47 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 67.500 60 148.50 HDTV 1080P
10. 1920*1080 67.432 59.939 148.352 HDTV 1080P
11. 1920*1080 27.000 24.000 74.25 HDTV 1080P
12. 1920*1080 26.97 23.94 74.176 HDTV 1080P
13. 1920*1080 33.75 30.000 74.25 HDTV 1080P
14. 1920*1080 33.71 29.97 74.176 HDTV 1080P
15. 1920*1080 56.25 50.000 148.5 HDTV 1080P
16. 1920*1080 28.125 25.000 74.25 HDTV 1080P

Copyright LG Electronics. Inc. All right reserved. -7- LGE Internal Use Only
Only for training and service purposes
7. RGB Input (PC)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1. 640*350 31.468 70.09 25.17 EGA X
2. 720*400 31.469 70.08 28.32 DOS O
3. 640*480 31.469 59.94 25.17 VESA(VGA) O
4. 800*600 35.156 56.25 36.00 VESA(SVGA) O
5. 800*600 37.879 60.31 40.00 VESA(SVGA) O
6. 1024*768 48.363 60.00 65.00 VESA(XGA) O
7. 1280*768 47.776 59.870 79.5 CVT(WXGA) O
8. 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9. 1280*1024 63.981 60.020 108.00 VESA O
10. 1600*1200 75.00 60.00 162 VESA (UXGA) O
11 1920*1080 67.5 60 148.5 HDTV 1080P O

** RGB PC Monitor Range Limits


- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz

8. HDMI Input (PC/DTV)


No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1 640*350 31.468 70.09 25.17 EGA X
2 720*400 31.469 70.08 28.32 DOS O
3 640*480 31.469 59.94 25.17 VESA(VGA) O
4 800*600 35.156 56.25 36.00 VESA(SVGA) O
5 800*600 37.879 60.31 40.00 VESA(SVGA) O
6 1024*768 48.363 60.00 65.00 VESA(XGA) O
7 1280*768 47.776 59.870 79.5 CVT(WXGA) O
8 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9 1280*1024 63.981 60.020 108.00 VESA (SXGA) O
10 1600*1200 75.00 60.00 162 VESA (UXGA) O
11 1920*1080 66.587 59.934 138.5 HDTV 1080P O
DTV
1 720*480 31.47 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.500 60 148.50 HDTV 1080P
8 1920*1080 67.432 59.939 148.352 HDTV 1080P
9 1920*1080 27.000 24.000 74.25 HDTV 1080P
10 1920*1080 26.97 23.94 74.176 HDTV 1080P
11 1920*1080 33.75 30.000 74.25 HDTV 1080P
12 1920*1080 33.71 29.97 74.176 HDTV 1080P
17. 1920*1080 56.25 50.000 148.5 HDTV 1080P
18. 1920*1080 28.125 25.000 74.25 HDTV 1080P

** HDMI Monitor Range Limits


- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz

Copyright LG Electronics. Inc. All right reserved. -8- LGE Internal Use Only
Only for training and service purposes
9. Consignment Setting (OUTGOING CONDITION)
No Item Condition
1. Input Mode TV02CH
2. Volume Level 10
3. Mute Off
4. Aspect Ratio 16:9
5. System Color PAL-M
6 Booster On
7. Picture Picture Mode Vivid
Backlight 100
Contrast 100
Brightness 50
Sharpness 70
Color 70
Tint 0
Color Temperature Cool
Picture Reset
8. Audio Sound Mode Standard
Auto Volume Off
Clear Voice Off
SRS TruSurround XT Off
Balance 0
TV Speaker On
9. Time Clock Auto
Off Timer / On Timer Off
Sleep Timer / Auto Sleep
10. Option Language (Menu/Audio) Portugues
SimpLink On
Key Lock Off
Caption Off
Set ID 1
11. Channel Memory RF : 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 30, 51, 63
CATV : 15, 16, 17

10. Mechanical Specification


42LH70YD-SE

No. Item Con tent Unit Remark


1. Product Width (W) Length (D) Height (H) mm
Dim ension W/O Packing 1009.7 334.4 753.6 mm With Stand
1009.7 39.7 695.4 mm W/O Stand
With Packing 1330 228 770 mm With Stand
1120 228 770 mm W/O Stand
2. Product W/O Packing 19.8 Kg With Stand
Weight 17.2 Kg W/O Stand
With Packing 24.0 Kg With Stand
21.0 Kg W/O Stand

Copyright LG Electronics. Inc. All right reserved. -9- LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 4. PCB Assembly Adjustment

This specification sheet is applied all of the LJ91D, LJ92J 4.1. CPLD DOWNLOAD : JTAG MODE
LCD TV models, which produced in manufacture department
or similar LG TV factory.

2. Notice

1) Because this is not a hot chassis, it is not necessary to use


an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs. .
3) The adjustment must be performed in the circumstance of
25 5C of temperature and 6510% of relative humidity if
there is no specific designation.
4) The input voltage of the receiver must keep 100~220V, 4.2. << PRINT PORT >> PIN MAP
50/60Hz.
5) Before adjustment, execute Heat-Run for 5 minutes. Pin JTAG Mode Signal Name
2 TCK
After Receive 100% Full white pattern (06CH) then process
Heat-run 3 TMS
(or 8. Test pattern condition of Ez-Adjust status) 8 TDI
How to make set white pattern
1) Press Power ON button of Service Remocon 11 TDO
2) Press ADJ button of Service remocon. Select 8. Test 13 -
pattern and, after select White using navigation button,
15 VCC
and then you can see 100% Full White pattern.
18 TO 25 GND
* In this status you can maintain Heat-Run useless any
pattern generator

* Notice: if you maintain one picture over 20 minutes


(Especially sharp distinction black with white pattern
13Ch, or Cross hatch pattern 09Ch) then it can appear
image stick near black level.

3. Adjustment Items

3.1 PCB Assembly adjustment


CPLD DOWNLOAD
Adjust 480i Comp1
Adjust 1080p Comp1/RGB
- If it is necessary, it can adjustment at Manufacture Line
- You can see set adjustment status at 1. ADJUST
CHECK of the In-start menu

3.2 Set Assembly Adjustment


EDID (The Extended Display Identification Data ) / DDC
(Display Data Channel) download
Color Temperature (White Balance) Adjustment
Make sure RS-232C control
Selection Factory output option

Copyright LG Electronics. Inc. All right reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
4.3. << 10P WAFER >> PIN MAP

Copyright LG Electronics. Inc. All right reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
4.4. Using RS-232C
Adjust 3 items at 3.1 PCB assembly adjustments 4.1.3
sequence one after the order.

O Adjustment protocol

Order Command Set response


1. Inter the ad 00 00 d 00 OK00x
Adjustment mode
2. Change the kb 00 40 b 00 OK40x (Adjust 480i Comp1/1080p Comp1)
Source kb 00 60 b 00 OK60x (Adjust 1080p RGB)
3.Start Adjustment ad 00 10
4.Return the OKx ( Success condition )
Response NGx ( Failed condition )
5.Read (main) (main : component1 480i, RGB 1080p)
Adjustment data ad 00 20 000000000000000000000000007c007b006dx
(main) (main : component1 1080p)
ad 00 30 000000070000000000000000007c00830077x
6.Confirm ad 00 99 NG 03 00x (Failed condition)
Adjustment NG 03 01x (Failed condition)
NG 03 02x (Failed condition)
OK 03 03x (Success condition)
7. End of Adjustment ad 00 90 d 00 OK90x

See ADC Adjustment RS232C Protocol_Ver1.0

O Adjustment protocol
- Pattern Generator : (MSPG-925FA)
- Adjust 480i Comp1 (MSPG-925FA : model :209 , pattern
: 65)
- Adjust 1080p Comp1/RGB(MSPG-925FA:model : 225 ,
pattern : 65)
- Adjust RGB (MSPG-925FA:model :225 , Pattern :65)
RGB-PC Mode

* If you want more information then see the below Adjustment


method (Factory Adjustment)

O Adjustment sequence
- ad 00 00 : Enter the ADC Adjustment mode.
- xb 00 40: Change the mode to Component1 (No actions)
- ad 00 10: Adjust 480i Comp
- ad 00 10: Adjust 1080p Comp
- xb 00 60: Change to RGB-PC mode(No action)
- ad 00 10: Adjust 1080p RGB
- ad 00 90: End of the adjustment

Copyright LG Electronics. Inc. All right reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
5. Factory Adjustment

5.1 Manual Adjust Component 480i/1080p


RGB 1080p

O Summary : Adjustment component 480i/1080i and RGB


1080p is Gain and Black levelsetting at Analog
to Digital converter, and compensate the RGB
deviation
O Using instrument
- Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V0.1V p-p correctly)

5.2 EDID (The Extended Display


Identification Data) / DDC (Display Data
Channel) Download.

<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern > O Summary


It is established in VESA, for communication between
* You must make it sure its resolution and pattern cause every PC and Monitor without order from user for building user
instrument can have different setting condition. It helps to make easily use realize Plug and
Play function.
O Adjustment method 480i Comp1, Adjust 1080p For EDID data write, we use DDC2B protocol.
Comp1/RGB (Factory adjustment)
ADC 480i Component1 adjustment O Auto Download
- Check connection of Component1 After enter Service Mode by pushing ADJ key,
- MSPG-925FA Model: 209, Pattern 65 Enter EDID D/L mode.
Set Component 480i mode and 100% Horizontal Color Enter START by pushing OK key.
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to NORMAL Caution: - Never connect HDMI & D-sub Cable when the user
ADC 1080p Component1 / RGB adjustment downloading .
- Check connection both of Component1 and RGB - Use the proper cables below for EDID Writing.
- MSPG-925FA Model: 225, Pattern 65
Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to NORMAL
After get each the signal, wait more a second and enter
the IN-START with press IN-START key of Service
remocon. After then select 7. External ADC with
navigator button and press Enter.
After Then Press key of Service remocon Right
Arrow(VOL+)
You can see ADC Component1 Success
Component1 1080p, RGB 1080p Adjust is same
method.
Component 1080p Adjustment in Component1 input
mode
RGB 1080p adjustment in RGB input mode
If you success RGB 1080p Adjust. You can see ADC
RGB-DTV Success

Copyright LG Electronics. Inc. All right reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
Edid data and Model option download (RS232) - HDM2 EDID table (0x33, 0x1C)
NO Item CMD 1 CMD 2 Data 0
Enter Download When transfer the Mode In ,
download MODE ModeIn A E 0 0 Carry the command.
Edid data and
Automaticall y download
Model option Download A E *Note1 *Note2
download (The use of a internal Data)
Adjust Mode Out A E 9 0
Adjustment To check Download
Confirmation A E 9 9 on Assembly line.

O Manual Download
Write HDMI EDID data
- Using instruments
=> Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
=> S/W for DDC recording (EDID data write and
read)
=> D-sub jack
=> Additional HDMI cable connection Jig.

- Preparing and setting.


=> Set instruments and Jig. Like pic.5), then turn on
PC and Jig.
=> Operate DDC write S/W (EDID write & read) - HDMI-3 EDID table (0x33, 0x0C)
=> It will operate in the DOS mode.

Download jig

Main
PC
B/D
RGB cable

Pic.3) For write EDID data, setting Jig and another instruments.

EDID data for LJ91D Chassis (Model name = LG TV)


- HDMI-1 EDID table (0x33, 0x2C)

- Analog (RGB) EDID table (0x9B, 0x25)

Copyright LG Electronics. Inc. All right reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
5.3 Adjustment Color Temperature(White O White Balance Adjustment
If you cant adjust with inner pattern, then you can adjust
balance) it using HDMI pattern. You can select option at "Ez-Adjust
Menu 7. White Balance" there items "NONE, INNER,
O Using Instruments HDMI". It is normally setting at inner basically. If you cant
Color Analyzer: CA-210 (CH 9) adjust using inner pattern you can select HDMI item, and
- Using LCD color temperature, Color Analyzer (CA-210) you can adjust.
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the In manual Adjust case, if you press ADJ button of service
Coordination bellowed one. remocon, and enter "Ez-Adjust Menu 7. White
Auto-adjustment Equipment (It needs when Auto- Balance", then automatically inner pattern operates. (In
adjustment It is availed communicate with RS-232C : case of "Inner" originally "Inner" will be selected.
Baud rate: 115200)
Video Signal Generator MSPG-925F 720p, 216Gray Connect all cables and equipments like Pic.5)
(Model: 217, Pattern 78) Set Baud Rate of RS-232C to 115200. It may set
115200 orignally.
Connect RS-232C cable to set
O Connection Diagram (Auto Adjustment)
Connect HDMI cable to set
Using Inner Pattern

F u l l W h i t e P at t er n C A -100+

COL OR
A NA L Y ZER
T Y PE ; C A -100+

R S-232C

Using HDMI input


RS-232C Command (Commonly apply)

wb 00 00 White Balance adjustment start.


wb 00 10 Start of adjust gain (Inner white
pattern)
wb 00 1f End of gain adjust
wb 00 20 Start of offset adjust(Inner white
pattern)
wb 00 2f End of offset adjust
wb 00 ff End of White Balance adjust(Inner
pattern disappeared)

"wb 00 00": Start Auto-adjustment of white balance.


"wb 00 10": Start Gain Adjustment (Inner pattern)
"jb 00 c0" :
<Pic.5 Connection Diagram for Adjustment White balance> .

"wb 00 1f": End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00
2f-end)
"wb 00 ff": End of white balance adjustment (inner
pattern disappear)

Copyright LG Electronics. Inc. All right reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
O White Balance Adjustment (Manual adjustment)
Test Equipment: CA-210
- Using LCD color temperature, Color Analyzer (CA-
210) must use CH 9, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
2100. See the Coordination bellowed one.
Manual adjustment sequence is like bellowed one.
- Turn to "Ez-Adjust" mode with press ADJ button of
service remocon.
- Select "10.Test Pattern" with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.
- Press "ADJ" button of service remocon and select
"7.White-Balance" in "Ez-Adjust" then press "" 5.5 Test of RS-232C control
button of navigation key. Press IN-Start button of service remocon then set the 4.Baud
(When press "" button then set will go to full white rate to 15200, Then check RS-232C control and
mode)
- Adjust at three mode (Cool, Medium, Warm) 5.6 Selection of Country option.
- If "cool" mode Selection of country option is allowed only North American model
Let B-Gain to 192 and R, G, B-Cut to 64 and then (Not allowed Korean model). It is selection of Country about
control R, G gain adjustment High Light adjustment. Rating and Time Zone.
- If "Medium" and "Warm" mode Models: All models which use LA75A Chassis (See the first
Let R-Gain to 192 and R, G, B-Cut to 64 and then page.)
control G, B gain adjustment High Light adjustment. Press In-Start button of Service Remocon, then enter the
- All of the three mode Option Menu with PIP CH- Button
Let R-Gain to 192 and R, G, B-Cut to 64 and then Select one of these three (USA, CANADA, MEXICO)
control G, B gain adjustment High Light adjustment. defends on its market using Vol. +/-button.
- With volume button (+/-) you can adjust.
- After all adjustment finished, with Enter ( key) turn * Caution : Dont push The Instop Key ater completing the
to Ez-Adjust mode. Then with ADJ button, exit from function inspection.
adjustment mode

Attachment: White Balance adjustment coordination and color 6. GND and ESD Testing
temperature.

O Using CS-1000 Equipment. 6.1 Prepare GND and ESD Testing.


- COOL : T=11000K, uv=0.000, x=0.276 y=0.283 Check the connection between set and power cord
- MEDIUM : T=9300K, uv=0.000, x=0.285 y=0.293
- WARM : T=6500K, uv=0.000, x=0.313 y=0.329 6.2 Operate GND and ESD auto-test.
Fully connected (Between set and power cord) set enter
the Auto-test sequence.
Connect D-Jack AV jack test equipment.
5.4 EYE-Q Function check. Turn on Auto-controller(GWS103-4)
1) Turn on TV Start Auto GND test.
2) Press EYE Key of Adj R/C If its result is NG, then notice with buzzer.
3) Cover the Eye Q II sensor on the front of the using your If its result is OK, then automatically it turns to ESD Test.
hand and wait for 6 seconds Operate ESD test
4) Confirm that R/G/B va;ie os ;pwer tjam 10 of the Raw If its result is NG, then notice with buzzer.
Data (Sensor data, Back light). If after 6 seconds, R/G/B If its result is OK, then process next steps. Notice it with
value is not lower than 10, re[;ace EYE Q II sensor. Good lamp and STOPER Down.
5) Remove your hand from the EYE Q II sensor and wait for
6 sencond 6.3 Check Items.
6) Confirm that OK pop up. Test Voltage
If change is not seen, replace EYE Q II sensor - GND: 1.5KV/min at 100mA
- Signal: 3KV/min at 100mA
Test time: just 1 second.
Test point
- GND test: Test between Power cord GND and Signal
cable metal GND.
- ESD test: Test between Power cord GND and Live and
neutral.
Leakage current: Set to 0.5mA(rms)

Copyright LG Electronics. Inc. All right reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
Block Diagram
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC
TU_CVBS_IN DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
Block Diagram I2C
I2C &
& RS232
RS232 Communication
Communication

Sub B/D D3.3V Main B/D D3.3V +3.3V_HDMI

4.7k ohm

4.7k ohm

2.7k ohm

2.7k ohm
4.7k ohm

4.7k ohm
VA1G5BF8005

P SCL1 22 ohm 0 ohm HDMI


22 ohm 22 ohm SCL0
7 SDA1 22 ohm 0 ohm S/W
22 ohm 0 22 ohm SDA0
1

47PF
47PF

100 ohm

NTP3100L
100 ohm

33PF
D3.3V 33PF

4.7k ohm

4.7k ohm
+5V_ST
BCM3556
4.7k ohm
4.7k ohm

SCL3 22 ohm 22 ohm

MICOM
SDA3 22 ohm 22 ohm
RS232C_RxD P
100 ohm
MAX3232 7
0 100 ohm
RS232C_TxD
2 D3.3V

4.7k ohm

4.7k ohm
22 ohm
SCL2 100 ohm
MST7323
SDA2 22 ohm 100 ohm

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
Block Diagram

I2C channel [LH70]

CH0 (+3.3V)
CH0

TUNER
TUNER 11
0xC2
0xC2
Demod(0x30)
Demod(0x30)
QPSK(0x32)
QPSK(0x32)

CH1 CH1 (+ 3.3V)


AMP
AMP
NTP3100L HDMI
HDMI SW
SW
NTP3100L
0x54 TDA9996
TDA9996
0x54

BCM3556
BCM3556

CH2 CH2 (+3.3V)


EEPROM
EEPROM Micom
Micom
AT24C512
AT24C512 MTV416
MTV416
0xA6
0xA6 0x50
0x50

CH3 CH3 (+3.3V)

FRC
FRC
MST7323
MST7323

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
Block Diagram

D1.2V, D2.5V, +3.3V, +5.0V_ST

SPDIF , EDID_WP .

SCL0_3.3V, SDA0_3.3V, DDC_SCL, DDC_SDA MAIN


Jack Board
CVBS, SIF, AV, RGB ,COMPONENT, R/L,
Board
TU_SCLK, TU_DATA, TU_SYNK..

< Signal Interface >

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
1. Power-Up Boot Fail Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC
TU_CVBS_IN DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
1. Power-Up Boot Fail Trouble Shooting

N Y
Check P801 All Voltage Level
Check Power connector Replace Power board
(24V, 12V, 5V_ST)

Check All Voltage Level N Replace one of L805/L807/L808


at L805/L807/L808 & Recheck

N Replace one of N
Check Voltage Level 3.3V at L830 IC809/Q812/L828/L829/L830/L822
& Recheck

N Replace one of IC803/L824/L827 N


Check Voltage Level 2.5V at L827
& Recheck

Check Micom IC406


Y
Redownload or replace
Check Voltage Level 1.8V N Replace one of IC802/IC805/L815 N
at IC802 #2 pin or L815 & Recheck

N Replace one of N
Check Voltage Level 1.2V at L821 IC804/Q809/L811/L817/L821
& Recheck

N
Check X903 Clock 54MHz Replace X903

Check signal transition N


Maybe BCM3556 has troubles
at IC101 #9 pin

Replace IC101 Flash Memory

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
2. No OSD Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC
TU_CVBS_IN DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
2. No OSD Trouble Shooting

N Y
Check 12V Voltage Level
Check Power connector Replace Power board
at P801 #13 Pin

Check 12V Voltage Level N Replace one of L801/Q804


at L801 & Recheck

N Replace one of
Check 12V Voltage Level at L909 Q802/Q803/Q804/L801
& Recheck

N Replace one of IC803/L824/L827


Check Voltage Level 2.5V at L827
& Recheck

Check Voltage Level 1.8V N Replace one of IC802/IC805/L815


at IC802 #2 pin or L815 & Recheck

Check Voltage Level 1.26V N Replace IC807


at IC807 #6 pin & Recheck

Check P903 N Maybe BCM3556(IC100) or


#16(TXAC-), #17(TXAC+), 7329A(IC901)
#32(TXBC-), #33(TXBC+) has troubles

N
Check LVDS Cable Replace Cable

Check Voltage LCD Module

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
3. Digital TV Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
3. Digital TV Video Trouble Shooting

Check RF Cable

Y
Replace one of IC101, IC102 at
N Jack Board or IC803/ IQ812/ C804/
Check Tuner(TU101) Power Q809/+5V_ST and +12V of P801 at
(5.0V, 2.5V, 3.3V, 1.2V) Main Board& Recheck

Check TP Clock, Data, Sync N


Maybe Tuner(TU101) has problems
R107, R108, R109

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Baord

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
4. Analog TV Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
4. Analog TV Video Trouble Shooting

Check RF Cable

Y
Replace one of IC101, IC102 at
Check Tuner(TU101) Power N Jack Board or IC803/ Q812/ IC804/
(5.0V, 2.5V, 3.3V, 1.2V) IC809/Q809/+5V_ST and +12V of
P801 at Main Board& Recheck
Y

Check CVBS Signal N


Maybe Tuner(TU101) has problems
TU101 #7 Pin and R118

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Baord

Check CVBS Signal N Replace one of R703 and C110


R703 and C110 at Main Baord & Recheck

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
5. Component Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70)
( ) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
5. Component Video Trouble Shooting

Check Signal Format


Is it supported signal?

Check Component Cable

Check Component Jack JK209 at N


Replace Jack at Jack board
Jack Board

Y
Check Component Signal N Replace one of
R292, R293, R294 R292, R293, R294, R295, R296, R297
R295, R296, R297 L212, L213, L214, L215, L216, L217
at Jack Board & Recheck

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Baord

Check Component Signal N


C130, C131, C132 Replace it
C133, C134. C135

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
6. RGB Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
6. RGB Video Trouble Shooting

Check Signal Format


Is it supported signal?

Check RGB Cable

Check RGB Jack JK208 at Jack N


Replace JK208 at Jack board
Board

Check RGB Signal N


Replace one of L207, L208, L209
L207, L208, L209 at Jack Board at Jack Board & Recheck

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Board

Check RGB Signal N


Replace it
C127, C128, C129 at Main Board

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
7. AV Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
7. AV Video Trouble Shooting

Check Signal Format


Is it supported signal?

Check AV Cable

Check AV Jack JK209 at Jack N


Replace JK209 at Jack board
Board

Y
Check AV Signal N Replace one of R203, R204, R214,
R203, R204, R214, R215 at Jack R215 at Jack Board
Board & Recheck

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Board

Check AV Signal N
Replace it
C124, C125 at Main Board

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
8. HDMI Video Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
8. HDMI Video Trouble Shooting

Check Signal Format


Is it supported signal?

Check HDMI Cable

Check HDMI Jack N


Replace Jack
JK600, JK601, JK602

Check IC601 Voltage Level N Replace one of


+1.8V_HDMI, +5.0V_HDMI L601/L602/R619/R615

Check I2C Signal N


Replace It & Recheck
R624/R625/R157/R158

Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
9. All Source Audio Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
9. All Source Audio Trouble Shooting

Make sure you cant hear any audio

N
Check Speaker Replace Speaker

N
Check Connector P501 Replace Connector

N Replace one of N
Check Signal
L508/L509/L510/L507/L504/L505
L504, L505
& Recheck

Y
Check IC501 Power N Replace one of N
Maybe NTP3100 has problems.
24V, 3.3V, 1.8V L511L503/L501 and IC503
L511, L503, L501 & Recheck Replace It

Check BCM3556 I2S Output N N


Replace It & Recheck
R505, R506, R507

Maybe BCM3556(IC100) N
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
10. Digital TV Audio Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
10. Digital TV Audio Trouble Shooting

N Follow procedure digital TV video


Check video output
trouble shooting

Follow procedure All source audio N Maybe BCM3556 internal audio


trouble shooting DSP has problems. Replace It

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
11. Analog TV Audio Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
11. Analog TV Audio Trouble Shooting

N Follow procedure analog TV video


Check video output
trouble shooting

Y
Replace one of IC101, IC102 at
N Jack Board or IC803/ Q812/ IC804/
Check Tuner(TU101) Power IC809/Q809/+5V_ST and +12V of
(5.0V, 2.5V, 3.3V, 1.2V) P801 at Main Board& Recheck

Y
Check SIF Signal N
TU101 #6 Pin and R118 at Jack Maybe Tuner(TU101) has problems
Board

N Replace one of
Check SIF Signal
L505/L514/C502/C511/Q500/Q502
IC501 #4 Pin
IC501 & Recheck

N Replace one of C123, R120, R121,


Check SIF Signal
R124, L109, Q101, C128
C128 at Jack Board
& Recheck

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Baord

Check SIF Signal N Replace one of R704/R128/C106


R704 and C106 at Main Board & Recheck

Follow procedure All source audio N Maybe BCM3556 audio block has
trouble shooting problems. Replace It

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
12. Component / RGB / AV Audio Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
12. Component / RGB / AV Audio Trouble Shooting

N Follow procedure external input


Check Video Output
video trouble shooting

N
Check Jack JK208/JK209 Replace Jack

Check Signal Replace one of


R235, R236 (Comp1) R235/R236/C231/C232 (Comp1)
R216, R217 (Comp2) N R216/R217/C207/C208 (Comp2)
R249, R250 (RGB) R219/R221/C210/C212 (AV1)
R219, R221 (AV1) R218/R220/C209/C211 (AV2)
R218, R220 (AV2) R249/R250/C246/C247 (RGB)
at Jack Board & Recheck at Jack Board

Check cable between P203 at Jack N


Maybe Cable Pin has problems
Board and P701 at Main Baord

Y
Replace one of
R215/R228/C211/C232 (Comp1)
Check Signal N
R229/R230/C220/C221 (Comp2)
C206, C210, C211, C232, C220, R204/R214/C206/C210 (AV1)
C221, C224, C225, C226, C227 R231/R232/C224/C225 (AV2)
at Main Board R233/R234/C226/C227 (RGB)
& Recheck at Main Board
Y

Follow procedure All source audio N Maybe BCM3556 audio block has
trouble shooting problems. Replace It

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
13. HDMI Audio Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
13. HDMI Audio Trouble Shooting

N
Follow procedure HDMI video
Check video output
trouble shooting

N
Re-download EDID data Replace IC601

Follow procedure All source audio N Maybe BCM3556 audio block has
trouble shooting problems. Replace it

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
14. USB Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
14. USB Trouble Shooting

Check USB 2.0 Cable

Y
Check USB device
If devuce is 2.5 inch HDD,
Check power adaptor

N
Check P704 Replace Jack

Y
Replace one of
N
Check 5V voltage level at L703 IC701/L703/IC806/Q810/L819
& Recheck

Maybe BCM3556(IC100)
has problems. Replace It.

Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
14. Bluetooth Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
14. USB Trouble Shooting

N
Check Bluetooth Module Replace Bluetooth

Check Cable between Bluetooth N


Replace cable
and Main Board

N
Check P705 Replace Jack

N Replace one of
Check Signal
R3022, R3023
R3022, R3023
& Recheck

Maybe BCM3556(IC100)
has problems. Replace It.

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
15. Digital TV Recording Fail Trouble Shooting
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
15. Digital TV Recording Fail Trouble Shooting

N
Follow procedure digital TV
Check video/audio output
video/audio trouble shooting

N Follow procedure USB trouble


Check USB
shooting

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
18. Digital TV Video Trouble Shooting while recording (Watch & Record)
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
18. Digital TV Video Trouble Shooting while recording (Watch & Record)

Check RF Cable

N
Follow procedure digital TV
Check video/audio output
video/audio trouble shooting

N Follow procedure USB trouble


Check USB
shooting

N Follow procedure OSD trouble


Check Watch
shooting

N
Check HDD (User) Replace Jack

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
19. Digital TV Audio Trouble Shooting while recording (Watch & Record)
Overall Block Diagram
for Brazil DTV (LH70) TU_SCLK, TU_SDATA, TU_SYNC

TU_CVBS_IN
DDR2(256Mbit)

VA1G5BF8005
Qimonda/Hynix
TU_SIF

SDA0/SCL0_3.3V
LVDS LCD Module
RF_Switch, Gain_Switch FRC IC
(FHD, 120Hz)
(MST7323S)

CVBS, L/R, AV_DET FRC Block


AV1
SIDE_CVBS, SIDE_L/R, SIDE_DET
AV2
X-tal
12MHz
Y Pb Pr, L/R, DET
Component 1
Y Pb Pr, L/R, DET
Component 2
DDR_Data[0:15], DQS, DM
RGB/H/V DDR2 (1Gbit)
D-sub RGB Elpida/Hynix
Audio L/R Addr.[0:13], ctrl. data
Audio L/R (for RGB)
JACK BACK BCM3556 DDR2 (1Gbit)
at REAR HDMI 1 Elpida/Hynix
Data[16:31]
3x1
(Brazil)
HDMI 2
HDMI Switch
HDMI 3 Data [0 7]
NAND Flash
CS ,RE,WE (512Mbit)
SPDIF
Digital Audio (Optic)

RX/TX RX/TX
RS-232C (Ctrl./SVC) MAX3232

USB_DM1 I2S Digital AMP


DP1/DM1
Bluetooth Module NTP3100L
USB_DP1
DP2/DM2 USB_DM2
USB USB_DP2 SCL, SDA_3.3V
+5V O.C. Protector +5V NVRAM

Reset Switch Reset IC SCL, SDA_3.3V MICOM X-tal


(MTV416GMF) 24MHz

54MHz CLK,TDI,TDO,MS,RST
Copyright 2009 LG Electronics. Inc. All right reserved. X-tal JTAG LGE Internal Use Only
Only for training and service purposes
19. Digital TV Audio Trouble Shooting while recording (Watch & Record)

N Follow procedure digital TV video


Check video output trouble shooting while recording
(watch & record)
Y

Follow procedure All source audio N Maybe BCM3556 internal audio


trouble shooting DSP has problems. Replace It

Copyright 2009 LG Electronics. Inc. All right reserved.


LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

400

900
541

570
540

571
804
800

805
803

530

550
200N

910
802

801
200

200T

A10
120
200N

LV2
122
121
500

LV1
310
300

560
580

A2
510

Copyright LG Electronics. Inc. All right reserved. -59- LGE Internal Use Only
Only for training and service purposes
HDMI3

9:G4;N10;AA14 +3.3V_VDDP_ST * HDMI_CEC


R693
HDMI_POWER_0 47K +1.8V_AMP +1.8V_HDMI D3.3V +3.3V_HDMI
20 +3.3V_VDDP_ST
GND R687 OPT
0 L601
HDMI_HPD_0 Z13 BLM18PG121SN1D BLM18PG121SN1D
20
HP_DET R3021

10V

R690
OPT

VR607

OPT
68K

OPT
R684

1K
L602

MMBD301LT1G
19
5V 0 C629 C612
18 R611 0.1uF

D804
0.1uF

3.6K
GND Q601

VR601

30V
16V

OPT
R601
9.1K 16V

OPT

10V
C608 SSM6N15FU
17
DDC_DATA 0.1uF GND
16V
16 12:E6
DDC_CLK GND R605 DRAIN1 SOURCE1

0
SDA_HDMI_0 O8;Z13 CEC_REMOTE 6 1 HDMI_CEC
15
NC
14 SCL_HDMI_0 O8;Z12 H16;H26;I7;AL11
CE_REMOTE GATE2 GATE1
R657 0 5 2
CEC_REMOTE H16;I7;Y26;AL11
13
CK- R656 0
TMDS0_RXC- Z12 SOURCE2 DRAIN2 C602
12 4 3

10V
VR604
CK_GND 0.1uF
11 16V
CK+ R658 0
TMDS0_RXC+ Z12
10
D0- R607 0
TMDS0_RX0- Z12
9 GND
D0_GND R608 0
8 GND
D0+ R609 0
TMDS0_RX0+ Z11 OPT
7
D1- R603 0
TMDS0_RX1- Z11
6
D1_GND
5
D1+ R662 0
TMDS0_RX1+ Z11
4
D2- R663 0
TMDS0_RX2- Z10
3
D2_GND
2
D2+ R664 0
TMDS0_RX2+ Z10
1
+3.3V_HDMI

JK602 R619
YKF45-7058V NO FLANGE 0

C624
@optio GND

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
HDMI2

0.1uF
C625

C607

C609

C610

C613

C614

C615
HDMI0_RXC-_BCM 11:F4
HDMI0_RXC+_BCM 11:F4

HDMI0_RX0-_BCM 11:F4
HDMI0_RX0+_BCM 11:F4

HDMI0_RX1-_BCM 11:F4
HDMI0_RX1+_BCM 11:F4

HDMI0_RX2-_BCM 11:F4
HDMI0_RX2+_BCM 11:F4
HDMI_SCL
HDMI_SDA
9:G5;R10;AD6 +5.0V 0.1uF
HDMI_POWER_1 C626
+3.3V_VDDP_ST

0
R695 0.1uF
47K C627

R612
GND
20 R689 OPT 0.1uF
0 R614
HDMI_HPD_1 AD7 1.8K
20
HP_DET
OPT
10V

OPT
R692
VR609

19 R686
1K

5V 0 OPT R613
OPT

1.8K
18 C623
3.6K

VR606

GND
OPT
OPT
R683

0.1uF
10V

17 16V
DDC_DATA
GND
16
DDC_CLK GND +1.8V_HDMI
15 SDA_HDMI_1
NC T8;AD7
14 SCL_HDMI_1 T8;AE7
CE_REMOTE R665 0
CEC_REMOTE H26;I7;Y26;AL11 C622 C628
13 C620
0.1uF 0.1uF
CK- R666 0 0.1uF
TMDS1_RXC- AE7 16V 16V
16V

VDDC[1V8]_3

VDDH[3V3]_8

VDDH[3V3]_7

RXD_DDC_CLK
RXD_DDC_DAT
12
CK_GND

VDDO[1V8]
11

OUT_D0-
OUT_D0+

OUT_D1-
OUT_D1+

OUT_D2-
OUT_D2+

RXD_D2+
RXD_D2-

RXD_D1+
RXD_D1-

RXD_D0+
RXD_D0-

RXD_DC+
RXD_DC-

RXD_HPD
CK+ R667 0

VSS_12

VSS_11

VSS_10

RXD_5V
TMDS1_RXC+ AE7
10 HDMI_POWER_2
D0- R668 0
TMDS1_RX0- AE7
9
D0_GND
HDMI0

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
8
D0+ R669 0 VSS_1 VDDH[1V8]_2
TMDS1_RX0+ AF7 1 75
7 R634 C621
HDMI_POWER_0 OUT_C+ 2 74 R12K
D1- R670 0 0.1uF
TMDS1_RX1- AF7 OUT_C- VSS_9 12K
6 3 73 16V
D1_GND VDDO[3V3] RXC_D2+
4 72
TMDS2_RX2+ I4
5 OUT_DDC_CLK RXC_D2-
D1+ R671 0 5 71
TMDS1_RX1+ C605 TMDS2_RX2- I4
AF7 OUT_DDC_DAT 6 70 VDDH[3V3]_6
4 0.1uF
D2- R672 0 16V VSS_2 RXC_D1+
TMDS1_RX2- AG7 7 69
I5
3 VDDC[1V8]_1 RXC_D1- TMDS2_RX1+

2
D2_GND
RXA_HPD
8
9
IC601 68
67 VSS_8 TMDS2_RX1- I5

D2+ 0 I28 HDMI_HPD_0


R673 RXA_5V 10 66 RXC_D0+
1
TMDS1_RX2+ AG7
H26;O8 SDA_HDMI_0
RXA_DDC_DAT 11 TDA9996HL 65 RXC_D0- TMDS2_RX0+
TMDS2_RX0-
I6
I6
RXA_DDC_CLK 12 64 VDDH[3V3]_5
H26;O8 SCL_HDMI_0
RXA_C- 13 63 RXC_C+
H25 TMDS0_RXC- TMDS2_RXC+ I6
RXA_C+ 14 62 RXC_C-
JK600 H25 TMDS0_RXC+ TMDS2_RXC- I7
GND VDDH[3V3]_1 RXC_DDC_CLK
15 61
SCL_HDMI_2 I8;T4
YKF45-7058V TMDS0_RX0-
RXA_D0- 16 60 RXC_DDCC_DAT
H24 SDA_HDMI_2 I8;T4
@optio NO FLANGE H24 TMDS0_RX0+
RXA_D0+
VSS_3
17 59 RXC_5V
RXC_HPD
18 58
R635 HDMI_HPD_2 I10
RXA_D1- 19 57 CEC
TMDS0_RX1- CEC_REMOTE H16;H26;I7;Y26
HDMI1 H24
H23 TMDS0_RX1+
RXA_D1+ 20 56 VSS_7 0
VDDH[3V3]_2 21 55 VDDS[3V3]
RXA_D2- 22 54 CDEC_STBY HDMI2
+3.3V_VDDP_ST H23 TMDS0_RX2-
9:G5;R6;AK15 RXA_D2+ 23 53 INT/HP_CTRL R636 0
R694 H22 TMDS0_RX2+
HDMI_POWER_2 47K VDDH[1V8]_1 24 52 XTAL_OUT OPT

0.1uF
HDMI_POWER_0 HDMI_POWER_1

C619
NC 25 51 XTAL_IN
R688 OPT
GND
20 0 +5.0V

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
HDMI_HPD_2 AL11 R615
20 For Only TDA9996 ES3
0
OPT
10V

VSS_4
TEST
RXB_HPD
RXB_5V
RXB_DDC_DAT
RXB_DDC_CLK
RXB_C-
RXB_C+
VDDH[3V3]_3
RXB_D0-
RXB_D0+
VSS_5
RXB_D1-
RXB_D1+
VDDH[3V3]_4
RXB_D2-
RXB_D2+
VSS_6
CDEC_DDC
VDDC[1V8]_2
VDDC[3V3]
0 MODE
PD
SDA/SEL1
SCL/SEL0
R691
VR608

C603
HP_DET OPT 0.1uF
1K

R685
OPT

19
5V 0 OPT
18 C616
3.6K

R622
VR602

GND
OPT
OPT
R602

0.1uF R627
10V

R626 R604 R629 0


17 16V GND
DDC_DATA 47K 47K 47K 47K R632
+1.8V_HDMI
16
DDC_CLK GND OPT
SDA_HDMI_0 SDA_HDMI_1

0
15
NC SDA_HDMI_2 T4;AL12 C617 C618
SCL_HDMI_0 SCL_HDMI_1 0.1uF 0.1uF
14 SCL_HDMI_2 T4;AL12 C601 C604 C606
CE_REMOTE R677 16V 16V

R624
0 0.1uF 0.1uF 0.1uF
CEC_REMOTE
H16;H26;Y26;AL11

0
13 16V 16V 16V
CK- R678 0
TMDS2_RXC- AL12
12
CK_GND HDMI_HPD_1

R625
+3.3V_HDMI
11
CK+ R674 0 I19
TMDS2_RXC+ AL12 R628
10
D0- R675 0 4.7K OPT
TMDS2_RX0- AL13

SCL_HDMI_1
SDA_HDMI_1
HDMI_POWER_2 HDMI_POWER_1 R623
9

TMDS1_RXC-
TMDS1_RXC+

TMDS1_RX0-
TMDS1_RX0+

TMDS1_RX1-
TMDS1_RX1+

TMDS1_RX2-
TMDS1_RX2+
D0_GND R630
8 OPT
D0+ R679 0 TMDS2_RX0+ AL13
7 R631
D1- R680 0 TMDS2_RX1- AL13 OPT
6 C611
D1_GND
0.1uF
5

H17;T8
H17;T8
H16
H16

H15
H15

H14
H14

H13
H13
D1+ R681 0 TMDS2_RX1+ AL13
4

SDA1_3.3V
SCL1_3.3V
D2- R676 0 TMDS2_RX2- AL14
3 R653 R654

9:I4;3:D3

9:I4;3:D3
D2_GND 47K 47K
2 HDMI1
D2+ R682 0 SDA_HDMI_2
TMDS2_RX2+ AL14
1
SCL_HDMI_2

JK601 FLANGE EDID Pull-up


YKF45-7054V GND
@optio HDMI S/W For MSTAR Platform

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008. 10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR LEE GI YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI
2 15
IC503
D3.3V AZ1117H-1.8TRE1(EH13A) +1.8V_AMP

INPUT 3 1 ADJ/GND

2
C548
22uF
C549
0.1uF
OUTPUT
16V 16V GND

C551 C552
0.1uF 22uF
16V 16V

+24V +24V_AMP

L511
MLB-201209-0120P-N2

SPK_L+ H3
+24V_AMP
R518 C544
L504 0.01uF
5.6 AD-8770 50V
T_68uF_Capacitor R511 R523
3.3 EAP60684501 C540 R527
C531 0.1uF
1000pF 2S 2F 50V 4.7K
50V 3.3

C515 C520 C522


C538
0.47uF
50V
SPEAKER_L
C553
0.01uF 0.1uF 0.1uF 68uF C532 1S 1F R528
50V C526 1000pF
50V 50V 35V 50V C541 3.3
@optio 0.01uF 0.1uF R524
50V R519 50V C545
4.7K 0.01uF
C514 5.6 50V

MLB-201209-0120P-N2
D3.3V 22000pF SPK_L- H3
50V C519
22000pF
50V
L503

PGND1A_2
PGND1A_1

PVDD1A_2
PVDD1A_1
PVDD1B_2
PVDD1B_1

PGND1B_2
PGND1B_1
C521

OUT1A_2
OUT1A_1

OUT1B_2
OUT1B_1
1uF
R502 16V
Change 22uH(L504,L505) TO 15uH/6.3mm After DV1

BST1B
VDR1B
100
9:G7;9:I3;12:I4 AMP_RST
C506

56
55
54
53
52
51
50
49
48
47
46
45
44
43
1000pF
50V
BST1A 1 42 NC C523
C511 16V1uF
R504 VDR1A 2 41 VDR2A C525 SPK_R+ H3
9:G6 0 1uF 10V 22000pF
RESET 3 40 BST2A
+1.8V_AMP AUDIO_M_CLK 50V R520
AD 4 39 PGND2A_2 L505 C546
5.6
IC501
MLB-201209-0120P-N2

+1.8V_AMP DVSS_1 PGND2A_1 AD-8770


5 38 0.01uF
C508 EAP60684501 C539 C542 R525
0.1uF VSS_IO 37 OUT2A_2 C533 0.47uF 50V
MLB-201209-0120P-N2

6 1000pF 2S 2F 50V 0.1uF 4.7K R529


L502
CLK_I 7 36 OUT2A_1 50V 50V 3.3 SPEAKER_R
C507 VDD_IO 8 NTP-3100L 35 PVDD2A_2
R501

C504 1000pF C534 1S 1F


L501 50V DGND_PLL 9 34 PVDD2A_1 1000pF R530
100pF
0

R503 AGND_PLL PVDD2B_2 50V 3.3


50V 10 33
C543 R526
3.3K LFM 11 32 PVDD2B_1 R521 C547
0.1uF 4.7K 0.01uF
AVDD_PLL 12 31 OUT2B_2 5.6 50V 50V
DVDD_PLL 13 EAN60664001 30 OUT2B_1 SPK_R- H3
TEST0 14 29 PGND2B_2
C501 C502
10uF 0.1uF C503 C505 +24V_AMP

15
16
17
18
19
20
21
22
23
24
25
26
27
28
10V 16V 10uF 0.1uF
6.3V 16V R522
3.3

DVSS_2
DVDD
SDATA
WCK
BCK
SDA
SCL
MONITOR_0
MONITOR_1
MONITOR_2
FAULT
VDR2B
BST2B
PGND2B_1
+1.8V_AMP
C530
C527 C528 C529 C535 WAFER-ANGLE
0.1uF
0.01uF 0.1uF 68uF 0.01uF
50V
50V L507 5
50V 50V
120-ohm
C510 C518
1uF H5 SPK_L+
10uF C513 10V C524 4
10V 0.1uF L508
16V T_68uF_Capacitor 120-ohm
22000pF
50V H5 SPK_L-
3
L510
120-ohm
H4 SPK_R+
R513 2
AMP_MUTE 12:F3 L509
R505 100 100 120-ohm
11:F7 BCM_I2S_DATA_OUT C517
H4 SPK_R-
R506 100 33pF 1
11:F6 BCM_I2S_WORD_CLK 50V
R507 100
11:F7 BCM_I2S_BIT_CLK OPT P501
R508 100
SDA1_3.3V
9:I4;2:AH5
R509 100
2A => 5A
9:I4;2:AH5 SCL1_3.3V

C512 C509
33pF 33pF
50V 50V

MCLK SDATA WCK BCK TP is necessory


Monitor0_1_2 TP is necessory

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008. 10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR KIM JONG HYUN
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AUDIO 3 15
* FROM LIPS & POWER B/D -->Apply changed Pin Map

+3.3V_ST
+12V
+5V_ST
L806
MLB-201209-0120P-N2

E
L822 D3.3V
R873 R859
Q805 MLB-201209-0120P-N2 +3.3V_MEMC
R823 3.3K 330K C873

OPT
1uF +12V L829

B
1K

OPT
C820 R817 R820 1/10W MLB-201209-0120P-N2
15pF R829 25V
33K 33K 0
50V
P801 RT1P141C-T112
C IC809
D803

R3025
R828 SC2621ASTRT A3.3V
FM20020-24 Q807 B 1N4148W
RL_ON
2SC3875S(ALY) 100V

0
10K 12:I5;14:E5
OPT
BST
1 14
DH Well change SI4804 to KECs Product
E OPT
L830
N.C POWER_ON OCS PN L828 MLB-201209-0120P-N2
1 2 2 13

R3028
GND GND +5V_ST

A1[RD] OPT
3 4 2.2uH

16V C883

A2[GN]1K
C3013

10uF C882

C886
CB4532UK121E

C885
COMP GND_2

10uF C881

0.01uF C884
GND GND

C887
5 6 3 12
220uF ==> 100uF*2 + 22uF for Depth Q812
L807 R862 R864
5.2V 7 8 5.2V SI4804BDY
FB DL C3017
5.6K 620

100uF
C819 C842 4 11 10uF
5.2V 5.2V

6.3V

6.3V
C899 S1 D1_2
9 10 C827

LD1
22uF 1 8 6.3V

0.1uF
10uF

33uF
100uF 22uF

6.3V
C878

0.1uF
100uF 16V
+12V GND 11 12 GND 16V 16V LDOG DRV G1 D1_1 R861 470pF
5 10

C
L808 2 7

C1809
MLB-201209-0120P-N2 12V 13 14 12V C880
S2
3 6
D2_2 3.3
C824 LDFB NC
C896 C828 C826 GND 15 16 GND L805 +24V 6 9 SAM2333

0.1uF
47uF 0.1uF
22uF 0.1uF 50V CB4532UK121E G2 D2_1
50V 25V 24V 24V 4 5 OPT
16V OPT 17 18 GND_1 VCC
7 8 C872 10uF
N.C 19 20 Inverter_On C812 C804 25V
0.1uF
C807
1uF C802 C856 OPT 1uF C879

470pF
A.Dim Error_Out 68uF C1806
21 22 50V 35V 50V 68uF 6800pF C3023 470pF 1K

C862
35V 1uF 0.1uF 25V
N.C 23 24 PWM_Dim +5.0V 25V 50V R863
R854
JP1111

10K must be placed with pin#8,#10 as close as possible.


4.7K L804
25 R818
GND

R801 BG2012B080TF 3.3K +3.3V_ST


A_DIM
R815
9:G6;9:I3 100 OPT
C805 C808 R826
C

R816
6.8K
1uF 16V 10K
R824 R830

OPT
25V 0.1uF
B 10K 0
OPT
C895
* D1.8V
C
0.1uF R870 415 mA @85% efficiency
50V Q806 E
Q903 B 10K D1.8V
2SC3052 INV_ON/OFF +5.0V
2SC3875S(ALY) OPT 750 mA +1.8V_MEMC
12:I5 D3.3V
TruMotion_240Hz OPT
E R827
10K
OPT IC802
Except_OPC L826
AZ1085S-ADJTR/E1 400 mA + 600 mA
IC805

R843
R869 BG2012B080TF

10K
0 INPUT OUTPUT
AOZ1073AIL
PWM_DIM ERROR_OUT 3 2
9:G7;9:I3;7:I5 C829 R807 C806 R802 12:F6
1
L815
1uF 0.1uF 0 C822 3.6uH
R822 0 16V C811 PGND LX_2
25V C876 ADJ/GND 330uF 1 8
0 OPT OPT 0.1uF
OPC_OUT1 OPT 100uF C818 L812
16V 0.1uF 1%
7:I5 OPC_EN 1% 4V MLB-201209-0120P-N2 C859
R825 VIN LX_1 C3021 C855
R857 2 7 10uF 0.1uF
56 66.5 10uF
+12V 6.3V
MLB-201209-0120P-N2

R819 AGND EN
12:A3;A6;C4;F7;G7;I2;14:B2 3 6
R1
* +12V to +5.0V 56
1%
R2
L813

Vout = (1+R2/R1)*1.25 FB COMP


C840 C841 4 5
R832 R834 0.1uF 1000pF 10uF
+12V 1.8V_BCM3556 C836

R844
3.3K 150K C838 50V

11K
1/10W 1uF 12:A3;A6;B5;F7;G7;I2;14:B2 R871
25V 20K
0
R3032

IC806 +5.0V
SC2621ASTRT D802 12:A3;2:Y20;2:Z10;B3;C6;H5;7:A3;14:I7;14:J1 R845
C846
1N4148W 330pF 15K
100V 50V
BST DH
1 14

L819
* +1.8V_MEMC for FRC DDR
OCS PN
2 13

2.2uH R853
COMP GND_2
3 12 300
Q810 C853 C860 C863 C1808
SI4804BDY R849 C1801
FB DL 10K D3.3V
4 11 VOUT : 2.533V * +1.26V Core for FRC 600 mA

100uF
S1 D1_2
10uF 10uF 0.01uF

MLB-201209-0120P-N2
1 8 10uF

16V
C845

LDOG DRV G1 D1_1 R837 470pF 16V 16V 16V +1.8V_MEMC +1.26V_MEMC
5 10 2 7 IC807
C1802

D2.5V
S2 D2_2 3.3 C851 A2.5V SC4215ISTRT

L824
LDFB NC 3 6
6 9
0.1uF

12.4K
50V

G2 D2_1 NC_2
4 5 NC_3 NC_1 GND

R855

1%
GND_1 VCC 1 8
7 8 10uF 4 5 L827
25V MLB-201209-0120P-N2
C821 C848 VIN R852
2200pF

C837 VO
1.1K

OPT EN ADJ
R874

C832 10K
0.068uF C3022 1uF 470pF 3 6 2 7
C830

1K OPT
1uF

39K

10V

33uF 10V
0.1uF 0
25V EN ADJ

6.3V
25V 50V

6.3V
VIN VO

R846
3 6
R821 R835 2 7

6.3V

16V
6.3V
33uF
1.8K

R840
must be placed with pin#8,#10 as close as possible. NC_1 GND

C3007
10uF

10uF
NC_2 NC_3 R856

C877
C875
A2[GN]
4 5

A1[RD]
1 8 C868 C870 22K

0.1uF
10uF

10uF
C3014 10uF 0.1uF
C858

18K
10V 16V

C888
10uF 33uF

OPT
6.3V 10V
SC4215ISTRT

C1803

C3010

C3011
MLB-201209-0120P-N2

+5.0V

C
IC803

R841
D805
SAM2333
L811

R831 R833
6.8K 390K C835
1/8W 1uF * +5.0V to 1.2V
25V

IC804
SC2621ASTRT D801 +5V_ST D1.2V +12V
1N4148W A1.2V * +5v_ST to +3.3V_ST
100V
BST DH
0
R3033

1 14 Q804
SI4925BDY

CB3216PA501E
L821
OCS PN L817 MLB-201209-0120P-N2

L801
2 13 S1 1 8 D1_2
1.2K

* +12v -> PANEL_POWER


6.3V
R872

2.2uH
10uF 6.3V

COMP GND_2 G1 2 7 D1_1


R842

4V

3 12
0.01uF
2K

Q809 +3.3V_VDDP_ST 7:I5;7:I7


C852

SI4804BDY
0.1uF
S2 3 6 D2_2
C854

FB DL +5V_ST +3.3V_ST 12V_TCON


C1807
C861

4 11
10uF

C865

S1 D1_2 OPT
330uF

1 8
470pF

G2 4 5 D2_1
C1804
C844

IC801 C817
3.3

R812
R836

LDOG DRV 1uF


4.7uF
200

5 10 G1 D1_1 AZ1117D-3.3TRE1 47K 25V 1uF


R847

2 7 L8012 C833

C898
R810 25V
22uF
C839

MLB-201209-0120P-N2 25V
S2 D2_2 INPUT OUTPUT 22K 25V
LDFB NC 3 6 3 2 C3009
6 9

C814 0.1uF

16V
47K
0.1uF

16V

16V
G2 D2_1 1
25V

4 5 R813
1uF

C894
C801 C803 ADJ/GND

C810
GND_1 VCC
7 8 22uF 10uF 0.1uF OPT C

22uF
470pF

0.1uF
16V 16V R806
C815 16V
1.5K

10K B Q803
C847

R848
220pF

C1805
C1800

2200pF 2SC3052
C825

1uF

22K
C E
25V R805
12:I5 10K B

Q802
R814 PANEL_CTL

R811
15K
2SC3052 E
1%

FLASH, A1.2, +1.8_DDR_BCM3556, VTT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 08.10.16
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR AN SO YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 4 15
D1.8V

D1.8V

0.047uF

0.047uF
0.047uF

0.047uF

C323

C324

C325

C326
0.01uF

C327

C328
2700pF

C329

C330

C331

C332
0.01uF

C333

C334
2700pF

C335

C352

C353

C354
C305

C306

C307

C308
0.01uF

C309

C310
2700pF

C311

C312

C313

C314
0.01uF

C315

C316
2700pF

C317

C349

C350

C351

470pF

470pF
470pF

470pF

100uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
100uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

10uF

10uF
10uF

10uF
A1.2V

IC100
BCM3556

A6 0.1uF C345 DDR0_VREF0 DDR1_VREF0


DDR_BVDD0
A24 0.1uF C346
DDR_BVDD1
DDR_BVSS0
B7 Qimonda Qimonda
B24
DDR_BVSS1
F20
IC300 IC301
DDR_PLL_TEST DDR1_DQ[0-15]
DDR_PLL_LDO
B23 R312 0 R301 HYB18TC1G160C2F-1.9 HYB18TC1G160C2F-1.9
22 C300 C301 DDR0_DQ[0-15] C321 C322
B17 OPT DDR01_CKE B4 B4
DDR01_CKE E5;H5;I2
C22 R313 470pF 0.1uF 470pF 0.1uF
DDR_COMP
E16 240 DDR01_ODT B6;H6;H2;B5 DDR01_A[0-3,7-13] VREF J2 G8 DQ0 DDR0_DQ[0] VREF DQ0 DDR1_DQ[0]
DDR01_ODT E5;H5;I1 B6;E6;H2;B5 DDR01_A[0-3,7-13] J2 G8
C23 G2 DQ1 DDR0_DQ[1] DQ1 DDR1_DQ[1]
DDR_EXT_CLK G2
B12 DDR0_CLK H7 DQ2 DDR0_DQ[2] DQ2 DDR1_DQ[2]
DDR0_CLK E5 DDR01_A[0] A0 A0 H7
C12 B6;H2 DDR0_A[4-6] M8 DQ3 DDR1_A[4-6] DDR01_A[0] M8
DDR0_CLKb E5 H3 DDR0_DQ[3] B5;H1 H3 DQ3 DDR1_DQ[3]
DDR0_CLKB DDR01_A[1] A1 M3 DDR01_A[1] A1
A13 DQ4 DDR0_DQ[4] M3 DQ4
DDR1_CLK DDR1_CLK H5 A2 H1 H1 DDR1_DQ[4]
DDR01_A[2] M7 DDR01_A[2] A2 M7
A12 DDR1_CLKb H9 DQ5 DDR0_DQ[5] DQ5 DDR1_DQ[5]
DDR1_CLKB H5 DDR01_A[3] A3 A3 H9
B15 DDR01_A[0] N2 DQ6 DDR01_A[3] N2
F1 DDR0_DQ[6] F1 DQ6 DDR1_DQ[6]
DDR01_A00 DDR0_A[4] A4 N8 DDR1_A[4] A4
E14 DDR01_A[1] DQ7 DDR0_DQ[7] N8 DQ7
DDR01_A01 DDR01_A[0-3] E6;H6;H2 DDR0_A[5] A5 F9 F9 DDR1_DQ[7]
N3 DDR1_A[5] A5 N3
A15 DDR01_A[2] C8 DQ8 DDR0_DQ[8] DQ8 DDR1_DQ[8]
DDR01_A02 DDR0_A[6] A6 DDR1_A[6] A6 C8
D15 DDR01_A[3] N7 DQ9 N7
C2 DDR0_DQ[9] C2 DQ9 DDR1_DQ[9]
DDR01_A03 DDR01_A[7] A7 P2 DDR01_A[7] A7
E13 DDR0_A[4] DQ10 DDR0_DQ[10] P2 DQ10
DDR0_A[4-6] D6;H2 A8 D7 D7 DDR1_DQ[10]
DDR0_A04 DDR01_A[8] P8 DDR01_A[8] A8 P8
E12 DDR0_A[5] D3 DQ11 DDR0_DQ[11] DQ11 DDR1_DQ[11]
DDR0_A05 DDR01_A[9] A9 A9 D3
F13 DDR0_A[6] P3 DQ12 DDR01_A[9] P3
D1 DDR0_DQ[12] D1 DQ12 DDR1_DQ[12]
DDR0_A06 DDR01_A[10] A10/AP M2 DDR01_A[10] A10/AP
C14 DDR01_A[7] DQ13 DDR0_DQ[13] M2 DQ13
A11 D9 D9 DDR1_DQ[13]
DDR01_A07 DDR01_A[11] P7 DDR01_A[11] A11 P7
F14 DDR01_A[8] B1 DQ14 DDR0_DQ[14] DQ14 DDR1_DQ[14]
DDR01_A08 DDR01_A[12] A12 A12 B1
B14 DDR01_A[9] R2 DQ15 DDR01_A[12] R2
DDR01_A[7-13] E6;H6;H2 B9 DDR0_DQ[15] B9 DQ15 DDR1_DQ[15]
DDR01_A09
D14 DDR01_A[10]
DDR01_A10
C13 DDR01_A[11] DDR01_BA0 BA0 L2 D1.8V BA0 D1.8V
DDR01_A11 B5;H5;I1 B5;E5;I1 DDR01_BA0 L2
D13 DDR01_A[12] DDR01_BA1 BA1 L3 BA1
DDR01_A12 B5;H5;I1 VDD5 B5;E5;I1 DDR01_BA1 L3 VDD5
B13 DDR01_A[13] BA2 A1 A1
B5;H5;I1 DDR01_BA2 L1 B5;E5;I1 DDR01_BA2 BA2 L1
DDR01_A13 E1 VDD4 VDD4
F15 DDR1_A[4] E1
DDR1_A[4-6] H6;H1 B6 DDR0_CLK VDD3 B6 DDR1_CLK
DDR1_A04 J9 J9 VDD3
C15 DDR1_A[5]
DDR1_A05 R300 CK VDD2 R303 CK VDD2
D16 DDR1_A[6] 100 J8 M9 J8 M9
100
DDR1_A06 DDR0_CLKb CK K8 R1 VDD1 CK VDD1
F16 B6 B6 DDR1_CLKb K8 R1
DDR01_BA0 DDR01_BA0 CKE
B6;H5;I2 DDR01_CKE K2 B6;E5;I2 DDR01_CKE CKE K2
B16 DDR01_BA1
DDR01_BA1
E15 DDR01_BA2
DDR01_BA2
A17 DDR01_CASb DDR01_ODT ODT K9 A9 VDDQ10 ODT VDDQ10
DDR01_CASB B6;H5;I1 B6;E5;I1 DDR01_ODT K9 A9
A8 DDR0_DQ[0] CS L8 C1 VDDQ9 CS VDDQ9
DDR0_DQ00 L8 C1
B11 DDR0_DQ[1] DDR01_RASb RAS K7 C3 VDDQ8 RAS VDDQ8
DDR0_DQ01 B2;H5;I1 B2;E5;I1 DDR01_RASb K7 C3
B8 DDR0_DQ[2] DDR01_CASb CAS L7 C7 VDDQ7 CAS VDDQ7
DDR0_DQ02 B5;H5;I1 B5;E5;I1 DDR01_CASb L7 C7
D11 DDR0_DQ[3]
B2;H5;I1 DDR01_WEb WE K3 C9 VDDQ6 ELPIDA B2;E5;I1 WE VDDQ6 ELPIDA
DDR0_DQ03 DDR01_WEb K3 C9 IC301-*1
E11 DDR0_DQ[4] E9 VDDQ5 IC300-*1 VDDQ5
DDR0_DQ04 E9 EDE1116ACBG-1J-E
C8 DDR0_DQ[5] VDDQ4 EDE1116ACBG-1J-E
G1 G1 VDDQ4
DDR0_DQ05 DDR0_DQS0 LDQS F7 LDQS
C11 DDR0_DQ[6] B3 VDDQ3 B3 DDR1_DQS0 F7 VDDQ3
VREF J2 G8 DQ0

DDR0_DQ06 DDR0_DQ[0-15] G6 UDQS G3 VREF J2 G8 DQ0 G3 G2 DQ1


B3 DDR0_DQS1 B7 DQ1 B3 DDR1_DQS1 UDQS B7 DQ2
C9 DDR0_DQ[7] G7 VDDQ2 G2
VDDQ2 A0 M8
H7

DDR0_DQ07 A0 M8
H7 DQ2 G7 A1 M3
H3 DQ3
DQ3 DQ4
D8 DDR0_DQ[8] G9 VDDQ1 A1 M3
H3
VDDQ1 A2 M7
H1

DDR0_DQ08 A2 M7
H1 DQ4 G9 A3 N2
H9 DQ5
DQ5 DQ6
E10 DDR0_DQ[9] B3 DDR0_DM0 LDM F3 A3 H9
LDM A4 F1

DDR0_DQ09 A4
N2
N8
F1 DQ6 B3 DDR1_DM0 F3 A5
N8
N3
F9 DQ7
DQ7 DQ8
E9 DDR0_DQ[10] DDR0_DM1 UDM B3 A5 F9
UDM A6 C8

DDR0_DQ10 B3 A6
N3
N7
C8 DQ8 B3 DDR1_DM1 B3 A7
N7
P2
C2 DQ9
DQ9 DQ10
F11 DDR0_DQ[11] A7 P2
C2
DQ10
A8 P8
D7
DQ11
DDR0_DQ11 A3 VSS5 A8 P8
D7
VSS5 A9 P3
D3
F12 DDR0_DQ[12] A9 P3
D3 DQ11 A3 A10 M2
D1 DQ12
DQ12 DQ13
DDR0_DQ12 DDR0_DQS0b LDQS E8 E3 VSS4 A10 D1
LDQS VSS4 A11 D9
E8 DDR0_DQ[13] B3 A11
M2
P7
D9 DQ13 B3 DDR1_DQS0b E8 E3 A12
P7
R2
B1 DQ14
DQ14 DQ15
DDR0_DQ13 DDR0_DQS1b UDQS A8 J3 VSS3 A12 B1
UDQS VSS3 B9
D10 DDR0_DQ[14] B3 R2
B9 DQ15 B3 DDR1_DQS1b A8 J3
BA0
DDR0_DQ14 N1 VSS2 VSS2 L2
F8 DDR0_DQ[15] BA0 L2 N1 BA1 L3
A1 VDD_5
BA1 BA2
DDR0_DQ15 P9 VSS1 L3
A1 VDD_5 VSS1 L1
E1 VDD_4
C18 DDR1_DQ[0] NC4 BA2 L1 VDD_4 NC4 P9 VDD_3
R3 E1
R3 J9
DDR1_DQ00 J9 VDD_3 CK J8 M9 VDD_2
C20 DDR1_DQ[1] NC5 R7 CK J8 M9 VDD_2 NC5 CK K8 R1 VDD_1
DDR1_DQ01 CK K8 R1 VDD_1 R7 CKE K2
A18 DDR1_DQ[2] CKE K2
DDR1_DQ02 ODT VDDQ_10
B21 DDR1_DQ[3] B2 VSSQ10 VSSQ10 K9 A9

DDR1_DQ03 NC1 ODT K9 A9 VDDQ_10


NC1 B2 CS L8 C1 VDDQ_9

C21 DDR1_DQ[4] A2 VSSQ9 CS L8 C1 VDDQ_9 A2 RAS K7 C3 VDDQ_8


B8 RAS VDDQ_8 B8 VSSQ9 CAS VDDQ_7
DDR1_DQ04 NC2 E2
K7 C3
NC2 L7 C7
B18 DDR1_DQ[5] VSSQ8 CAS L7 C7 VDDQ_7 E2 VSSQ8
WE K3 C9 VDDQ_6

NC3 A7 WE VDDQ_6 A7 VDDQ_5


DDR1_DQ05 R8
K3 C9
VDDQ_5 NC3 R8
E9
VDDQ_4
B20 DDR1_DQ[6] DDR1_DQ[0-15] D2 VSSQ7 E9
VSSQ7 LDQS G1

DDR1_DQ06 J6 LDQS F7
G1 VDDQ_4 D2 UDQS
F7
B7
G3 VDDQ_3
VDDQ_3 VDDQ_2
D18 DDR1_DQ[7] D8 VSSQ6 UDQS B7
G3
VSSQ6 G7

DDR1_DQ07 G7 VDDQ_2 D8 G9 VDDQ_1


VDDQ_1 LDM
E18 DDR1_DQ[8] VSSDL E7 VSSQ5 G9
VSSQ5 F3

DDR1_DQ08 J7 LDM F3 VSSDL J7 E7 UDM B3


UDM
D21 DDR1_DQ[9] F2 VSSQ4 B3
VSSQ4 A3 VSS_5
DDR1_DQ09 A3 VSS_5 F2 LDQS E8 E3 VSS_4
F18 DDR1_DQ[10] F8 VSSQ3 LDQS E8 E3 VSS_4 VSSQ3 UDQS A8 J3 VSS_3
DDR1_DQ10 UDQS A8 J3 VSS_3 F8 N1 VSS_2
E20 DDR1_DQ[11] H2 VSSQ2 N1 VSS_2 VSSQ2 P9 VSS_1
DDR1_DQ11 P9 VSS_1 H2 NC_5 R3
NC_5 NC_6
A22 DDR1_DQ[12] VDDL J1 H8 VSSQ1 R3
VDDL VSSQ1 R7

DDR1_DQ12 NC_6 R7 J1 H8
VSSQ_10
F17 DDR1_DQ[13] VSSQ_10
NC_1 A2
B2
VSSQ_9
DDR1_DQ13 NC_1 A2
B2
VSSQ_9
NC_2 E2
B8
VSSQ_8
B22 DDR1_DQ[14] NC_2 E2
B8
VSSQ_8
NC_3 R8
A7
VSSQ_7
DDR1_DQ14 NC_3 R8
A7
VSSQ_7
D2
VSSQ_6
E17 DDR1_DQ[15] D2
VSSQ_6
D8
VSSQ_5
DDR1_DQ15 D8
VSSQ_5
VSSDL J7 E7
VSSQ_4
A10 DDR0_DM0
VSSDL J7 E7 F2

DDR0_DM0 E4 F2 VSSQ_4 F8 VSSQ_3


VSSQ_3 VSSQ_2
C10 DDR0_DM1
F8 H2

DDR0_DM1 E4 H2 VSSQ_2 VDDL J1 H8 VSSQ_1


VDDL VSSQ_1
A20 DDR1_DM0
J1 H8

DDR1_DM0 H4
F19 DDR1_DM1
DDR1_DM1 H4
B10 DDR0_DQS0
DDR0_DQS0 E4
B9 DDR0_DQS0b
DDR0_DQS0B E4
F10 DDR0_DQS1
DDR0_DQS1 E4
F9 DDR0_DQS1b
DDR0_DQS1B E4
B19 DDR1_DQS0
DDR1_DQS0 H4
C19 DDR1_DQS0b
DDR1_DQS0B H4 * DDR_VTT
E19 DDR1_DQS1
DDR1_DQS1 H4
D19 DDR1_DQS1b H4
DDR_VTT
DDR1_DQS1B
C16 DDR01_RASb DDR0_VREF0
DDR01_RASB
A7 E5;H5;I1 DDR1_VREF0 DDR_VTT D3.3V
DDR_VREF0
A23 DDR01_A[0-3,7-13]
DDR_VREF1
C17 D1.8V DDR01_WEb
DDR01_WEB DDR1_A[4] R304
C7
DDR_VDDP1P8_1 DDR01_A[0] 75
C361

D22 C336
C343

C342

C360
C347

C344

C358
C359

DDR_VDDP1P8_2 DDR0_A[4-6] DDR01_A[1] 0.01uF


IC808
D1.8V DDR01_A[2]
C355 C869 C874 C864 BD35331F-E2
0.1uF 100uF 0.1uF R305
1uF 470pF 470pF 1uF 1uF 470pF 470pF 1uF 10uF C337
16V 10V 16V DDR0_A[4] 75 0.01uF
GND VTT DDR0_A[5]
1 8
DDR0_A[6]
C338
DDR01_A[3] R306 0.01uF
EN VTT_IN
2 7 DDR01_A[7] 75
DDR1_VREF0 DDR01_A[8]
C339
VTTS VCC DDR01_A[9] 0.01uF
3 6
DDR0_VREF0 DDR01_A[10] R307
DDR01_A[11] 75
R850 0 VREF VDDQ C340
4 5 BCM recommends to remove this R DDR01_A[12] 0.01uF
DDR01_A[13]
R851 0 C871 OPT 75 R310
C867 C897 B6;E5;H5 DDR01_CKE C341
1uF
100uF 0.1uF DDR1_A[5] R308 0.01uF
6.3V
16V 16V DDR1_A[6] 75
16V
C866

C831 C834 B5;E5;H5 DDR01_BA1 C362


0.1uF 0.1uF 1M DDR1_A[4-6] 0.1uF
0.1uF

B5;E5;H5 DDR01_BA2
16V 16V
R858 B2;E5;H5 DDR01_RASb R309
B5;E5;H5 DDR01_BA0 75
B5;E5;H5 DDR01_CASb
B2;E5;H5 DDR01_WEb
B6;E5;H5 DDR01_ODT 75 R311

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 08.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR HONG YEON HYUK
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR Memory 6 15
LVDS_TX_0_DATA4_P
LVDS_TX_0_DATA4_N
LVDS_TX_0_DATA3_P
LVDS_TX_0_DATA3_N

LVDS_TX_0_DATA2_P
LVDS_TX_0_DATA2_N
LVDS_TX_0_DATA1_P
LVDS_TX_0_DATA1_N
LVDS_TX_0_DATA0_P
LVDS_TX_0_DATA0_N
LVDS_TX_1_DATA4_P
LVDS_TX_1_DATA4_N
LVDS_TX_1_DATA3_P
LVDS_TX_1_DATA3_N

LVDS_TX_1_DATA2_P
LVDS_TX_1_DATA2_N
LVDS_TX_1_DATA1_P
LVDS_TX_1_DATA1_N
LVDS_TX_1_DATA0_P
LVDS_TX_1_DATA0_N
R929

LVDS_TX_0_CLK_P
LVDS_TX_0_CLK_N
LVDS_TX_1_CLK_P
LVDS_TX_1_CLK_N
* XTAL 1M

X901

M_XTALO
M_XTALI
M_XTALO M_XTALI
C946 12MHz C947 C947-*1
C946-*1 20pF
15pF 15pF
20pF

FRC_XTAL_20PF
FRC_XTAL_20PF FRC_XTAL_15PF R917 R923
100 100
+3.3V_MEMC 12V_TCON
R918 R924

CB3216PA501E
+3.3V_MEMC

BLM18PG121SN1D

BLM18PG121SN1D
URSA_A0P
URSA_A0M
URSA_A1P
URSA_A1M
URSA_A2P
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A3P
URSA_A3M
URSA_A4P
URSA_A4M

URSA_B0P
URSA_B0M
URSA_B1P
URSA_B1M
100 100

L909
R919 R925

L907
100 100

L908
+1.26V_MEMC R920 R926 P903
100 100 TF05-51S
+3.3V_MEMC
R921 R927

BLM18PG121SN1D

10uF
1

10uF
BLM18PG121SN1D
2
100 100

L905

0.1uF 50V
22uF/16 CST PROBLEM

1000pF 50V
0.1uF
C943

C944
3

1uF
6.3V

6.3V

C961

C960
R922 R928 4

L906

C952
5

C954
100 100 6

0.1uF

0.1uF
C914 0.1uF

0.1uF
10uF
10uF

C3019 10uF

0.1uF
7

C940

C942
8

10V
10

C915

0.1uF

0.1uF
C916

0.1uF

0.1uF
C923

C926

C937
URSA_B4M

C935

C948

C949
10uF
11

C931

C933

10uF
URSA_B4P 12
URSA_B3M

AVDD_LVDS_1

AVDD_LVDS_2
13
PI Result
R931 URSA_B3P 14

GPIO[25]

AVDD_PLL
15

GPIO_13
GPIO_14

GPIO_12
820 URSA_BCKM

GPIO_2
GPIO_1

GPIO_9
GPIO_8

LVACKP
LVACKM

GPIO_6
GPIO_4
16

RECKP
RECKN

GND_6

ROCKP
ROCKN

GND_5

GND_2

LVA0P
LVA0M
LVA1P
LVA1M
LVA2P
LVA2M

LVA3P
LVA3M
LVA4P
LVA4M

LVB0P
LVB0M
LVB1P
LVB1M
URSA_BCKP 17

RE4P
RE4N
RE3P
RE3N

RE2P
RE2N
RE1P
RE1N
RE0P
RE0N

RO4P
RO4N
RO3P
RO3N

RO2P
RO2N
RO1P
RO1N
RO0P
RO0N

XOUT

SDAM
SCLM

REXT
R909 0

XIN
A3 ISP_RXD_TR 18
R910 0 C955 URSA_B2M 19
A3 ISP_TXD_TR URSA_B2P 20
URSA_B1M

B1
A1
C1
C2
A2
B2
B3
A3
C3
C4
A4
B4
F11
H8
B5
A5
C5
C6
A6
B6
B7
A7
C7
C8
A8
B8
G11
H7
K15
K16
D4
D3
B14
A14
D5
D6
N7
E11
D13
D11
G8
F10

B9
A9
C9
C10
A10
B10
B11
A11
C11
C12
A12
B12
D9
D7
B13
A13
C13
C14

D12
21
0.1uF
R911 100 SDAS GPIO_5 URSA_B1P 22

9:I4 SDA3_3.3V E1 D8 URSA_B0M 23


R912 100 SCLS GPIO_7
9:I4 SCL3_3.3V D1 D10 URSA_B0P OPT 24

0.1uF
GPIO[8] GPIO_11 R953
F1 E10 BIT_SEL 25

GPIO[9] GPIO_10 0
JP901 G1 E3
26
URSA_A4M 27
GND_14 K8 D2 GPIO_3 URSA_A4P
JP902 [E1] 28

OPT VDDC_1 E5 C15 LVB2P URSA_B2P URSA_A3M


[D1] 29

C929 GPIO[10] LVB2M URSA_B2M URSA_A3P 30


LVDS_SEL R3029 E2 B15
31
0 GPIO[11] LVBCKP URSA_BCKP
F2 A15 URSA_ACKM
9:G6;I5 32

1/16W GPIO[12] F3 A16 LVBCKM URSA_BCKM URSA_ACKP 33

5% GPIO[13] G2 B16 LVB3P URSA_B3P 34


URSA_A2M 35
+3.3V_MEMC GPIO[22] M4 C16 LVB3M URSA_B3M URSA_A2P 36
GPIO[23] M5 D15 LVB4P URSA_B4P URSA_A1M 37
+3.3V_MEMC URSA_A1P
GPIO[14] G3 D16 LVB4M URSA_B4M 38
URSA_A0M
BLM18PG121SN1D

R915 1K 39
GPIO[15] E4 F9 AVDD_33_2 C956 URSA_A0P 40
GPIO[16] F4 G10 GND_4 41
L903

GPIO[17] LVC0P URSA_C0P OPC_EN 42


G4 E15 R936 0 43
GPIO[18] LVC0M 0.1uF URSA_C0M OPC_OUT1
H4 E16 44
PWM_DIM 0
R916 1K GPIO[19] J4 E14 LVC1P URSA_C1P R937 45
OPT OPC_EN
C912 C913 GPIO[20] LVC1M URSA_C1M +3.3V_MEMC 46
C911

10uF

K4 F14
10uF
C910

0.1uF 0.1uF GPIO[21] LVC2P URSA_C2P 12V_TCON 47


L4 F16 48
16V 16V
C930 VDDP_2 LVC2M URSA_C2M

OPC_EN
J6 F15 49

R948

R954

3.3K
OPT
GND_7 LVCCKP URSA_CCKP 50

499
H9 G15
51
PI Result 0.1uF 0.1uF GND_15 K9 LVCCKM URSA_CCKM
G16
52
G14 LVC3P URSA_C3P R941 0 OPC_EN
OPC_EN
URSA_DQ[0-31]

VDDC_2 F6 H14 LVC3M URSA_C3M


C927 R940 0
URSA_DQ[20] MDATA[20] H1 H16 LVC4P URSA_C4P LVDS_SEL
URSA_DQ[19] MDATA[19] H2 H15 LVC4M URSA_C4M
J15 LVD0P URSA_D0P

R949

3.3K
3.3K

R955
IC901

OPT
+1.8V_MEMC URSA_DQ[17] MDATA[17] H3 J16 LVD0M URSA_D0M
URSA_DQ[22] MDATA[22] J1 J14 LVD1P URSA_D1P
BLM18PG121SN1D

K14 LVD1M URSA_D1M


L904

22uF/16 CST PROBLEM URSA_DQ[27] MDATA[27] J2


URSA_DQ[28] MDATA[28] J3

URSA_DQ[25]
C918 0.1uF
MDATA[25] K1
LGE7329A L14
G9 GND_3
LVD2P
C957

URSA_D2P
0.1uF

10uF
0.1uF
C3020

URSA_DQ[30] MDATA[30] LVD2M 0.1uF URSA_D2M


10uF

10uF
C901

K2 L15
C904

C907

C909

AVDD_DDR_2 K6 L16 LVDCKP URSA_DCKP


DQM[3] K3 M16 LVDCKM URSA_DCKM
URSA_DQM3
DQM[2] L1 F8 AVDD_33_1
URSA_DQM2 0.1uF GND_10 J8 M15 LVD3P URSA_D3P
C919
DQS[2] L2 M14 LVD3M URSA_D3M
URSA_DQS2
DQSB[2] L3 N16 LVD4P URSA_D4P
URSA_DQSB2
AVDD_DDR_4 L6 N15 LVD4M C953 URSA_D4M
* ISP Port for MEMC 0.1uF VDDP_3 L8
GND_8 H10 H6 VDDC_5
C928
DQS[3] GPIO[24] 0.1uF +3.3V_MEMC
URSA_DQS3 M1 N6
DQSB[3] M2 E12 GPIO[7]
URSA_DQSB3
AVDD_DDR_5 L7 D14 GPIO[6]
URSA_DQ[31] MDATA[31] M3 F12 GPIO[5]
URSA_DQ[24] 0.1uF MDATA[24] GPIO[4]
+5.0V N1 E13 P904
P902 TF05-41S
GND_11 J9 F13 GPIO[3]
C920

R938
TJC2508-4A

R942
1K

1K
URSA_DQ[26] MDATA[26] N2 G13 GPIO[2]
1
URSA_DQ[29] MDATA[29] N3 H13 GPIO[1]
2
+3.3V_MEMC AVDD_DDR_6 L10 J13 GPIO[0] URSA_D4M 3
1 URSA_D4P
BLM18PG121SN1D

URSA_DQ[23] MDATA[23] P1 K12 PWM0 4


OPT
2.2K
R908

2.2K
R907
OPT

URSA_D3M 5
URSA_DQ[16] MDATA[16] R1 L12 PWM1
[N13] URSA_D3P 6

2 URSA_DQ[18] MDATA[18] T1 K13 CSZ


[L9] [N12] M_SPI_CZ
7

URSA_DQ[21] MDATA[21] SDO URSA_DCKM


L902

8
T2 [N5] M12 M_SPI_DO URSA_DCKP

R939

R943
9
ISP_RXD_TR MCLK[0] SDI

OPT

OPT
1K

1K
URSA_MCLK R2 [N4] M13 M_SPI_DI 10
3 MCLKZ[0] SCK
B6 P2 L13 URSA_D2M 11
URSA_MCLKZ C925 0.1uF M_SPI_CK
GND_1 GPIO[30] URSA_D2P 12
G7 N14
URSA_D1M 13
4 AVDD_MEMPLL GPIO[29]
B6 L9 N13 URSA_D1P 14
0.1uF
C906

MVREF GPIO[28]
10uF
C908

URSA_D0M 15
ISP_TXD_TR N5 N12
ODT URSA_D0P 16
URSA_ODT N4 17
J10

L11

K10

T10
K11
R10
P10

T11
R11
J11
P11
T12

R12
P12

H11

T13
R13

P13
T14

R14
P14

T15
R15
P15
T16
R16
P16

N10
N11
M11
0.1uF C921
T3
R3
P3
T4
R4

P4
T5
R5
P5
T6
R6
P6
T7

R7
P7
T8
R8
P8
N8

F7
T9
R9
K7
P9

J7

N9

G6
18

URSA_C4M 19

URSA_C4P 20

GND_9
RASZ
CASZ
MADR[0]
MADR[2]
MADR[4]
GND_12
MADR[6]
MADR[8]
MADR[11]
WEZ
BADR[1]
BADR[0]
MADR[1]
MADR[10]
AVDD_DDR_7
MADR[5]
MADR[9]
MADR[12]
MADR[7]
MADR[3]
MCLKE
GND_16
VDDC_3
MDATA[4]
MDATA[3]
GND_13
MDATA[1]
MDATA[6]
AVDD_DDR_3
MDATA[11]
MDATA[12]

MDATA[9]
MDATA[14]
AVDD_DDR_1
DQM[1]
DQM[0]

DQS[0]
DQSB[0]

VDDP_1

DQS[1]
DQSB[1]

MDATA[15]
MDATA[8]

MDATA[10]
MDATA[13]

MDATA[7]
MDATA[0]
MDATA[2]
MDATA[5]
MCLK[1]
MCLKZ[1]
GPIO[26]
GPIO[27]
GND_17
RESET

VDDC_4
0.1uF GPIO8 PWM1 PWM0 URSA_C3M 21

URSA_C3P 22

23
C922
I2C HIGH LOW HIGH URSA_CCKM 24

URSA_CCKP 25

26

EEPROM HIGH URSA_C2M

0.1uF
HIGH LOW 27
0.1uF

C950
C941

URSA_C2P 28

URSA_C1M 29
* SPI FLASH URSA_C1P 30
SPI HIGH HIGH HIGH

0.1uF

0.1uF
C945

C951
URSA_C0M 31

URSA_C0P 32
+3.3V_MEMC
33
+3.3V_MEMC
C932

C934

C936

C938
R913

C939

34
10K

35

36

37
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

R930
38

0
0.1uF

4.7K
URSA_A[11]

URSA_A[10]

URSA_A[12]

39
C958

R933
URSA_A[0]
URSA_A[2]
URSA_A[4]

URSA_A[6]
URSA_A[8]

URSA_A[1]

URSA_A[5]
URSA_A[9]

URSA_A[7]
URSA_A[3]

40

41
IC902
0.1uF

C917

42
R914

C924
1uF

W25X20AVSNIG
10K

FRC_RESET
R945 56 CS
1 8
VCC
M_SPI_CZ
URSA_DQ[11]
URSA_DQ[12]

URSA_DQ[14]

URSA_DQ[15]

URSA_DQ[10]
URSA_DQ[13]
URSA_DQ[4]
URSA_DQ[3]

URSA_DQ[1]
URSA_DQ[6]

URSA_DQ[9]

URSA_DQ[8]

URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]
URSA_DQ[5]
R946 56 DO
2 7
HOLD
M_SPI_DO
R947 10K WP CLK R951 56
3 6
M_SPI_CK H3
GND
4 5
DIO R952 56
M_SPI_DI H3

URSA_DQ[0-31]
URSA_RASZ
URSA_CASZ

URSA_WEZ
URSA_BA1
URSA_BA0

URSA_MCLKE

URSA_A[0-12]

URSA_DQM1
URSA_DQM0

URSA_DQS0
URSA_DQSB0

URSA_DQS1
URSA_DQSB1

URSA_MCLK1
URSA_MCLKZ1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR PARK.S.W
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS / Mstar FRC 7 15
DDR2 1.8V By CAP - Place these Caps near Memory

+1.8V_MEMC +1.8V_FRC_DDR +1.8V_FRC_DDR +1.8V_FRC_DDR

BLM18PG121SN1D
L1002

10V

10V
0.1uF

0.1uF

0.1uF

C1006

C1008

C1010

C1011

C1012

C1013

C1014

C1015

C1016

C1017

C1018

C1019

C1020
C1043

C1044

C1045

0.1uF

C1003

C1007

C1009

C1021
C1042

C1024

0.1uF

C1005

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
C1026

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
10uF
C1027

C1028

C1029

C1030

C1031

C1032

C1033

C1034

C1035

C1036

C1037

C1038

C1039

C1040

C1041

C1004

0.1uF

0.1uF
C1025

10uF
10uF

10uF

10uF
10uF
PI Result

+1.8V_FRC_DDR +1.8V_FRC_DDR

R1002

1K 1%

R1022
URSA_DQ[0-31]

URSA_A[0-12]
AR1018

1K
7:G1;AM22 DDR_DQ[15] URSA_DQ[15]
URSA_DQ[0-31]
DDR_DQ[8] 56 URSA_DQ[8]
AR1004 DDR_DQ[10] URSA_DQ[10] 7:G1;C22
URSA_DQ[27] DDR_DQ[27]

R1023

1000pF
1K 1%
1000pF

R1003

C1022

0.1uF
C1023
C1002

0.1uF
C1001
DDR_DQ[13] URSA_DQ[13]
URSA_DQ[28] DDR_DQ[28]
IC1001 IC1002

1K
URSA_DQ[25] 56 DDR_DQ[25] AR1017
DDR_DQ[7] URSA_DQ[7]
URSA_DQ[30] DDR_DQ[30] H5PS5162FFR-S6C H5PS5162FFR-S6C DDR_DQ[0] URSA_DQ[0]
56
AR1003 DDR_DQ[2] URSA_DQ[2]
URSA_DQ[22] DDR_DQ[22]
DDR_DQ[5] URSA_DQ[5]
URSA_DQ[17] DDR_DQ[17] DDR_DQ[16] DQ0 G8 J2 VREF VREF J2 G8 DQ0 DDR_DQ[0]
URSA_DQ[19] 56 DDR_DQ[19] DDR_DQ[17] DQ1 G2 G2 DQ1 DDR_DQ[1] AR1016
URSA_A[3] AR1012 DDRA_A[3] DDR_DQ[11] URSA_DQ[11]
URSA_DQ[20] DDR_DQ[20] DDR_DQ[18] DQ2 H7 H7 DQ2 DDR_DQ[2]
M8 A0 DDRB_A[0] DDRA_A[0] A0 M8 DDR_DQ[12] 56 URSA_DQ[12]
DDR_DQ[19] DQ3 DDRB_A[10] AR1005 URSA_A[10] URSA_A[1] 22 DDRA_A[1] DQ3 DDR_DQ[3]
H3 H3
DDR_DQ[16-31]

AR1002 A1 DDRB_A[1] DDRA_A[1] A1 DDR_DQ[9] URSA_DQ[9]

DDR_DQ[0-15]
URSA_DQ[31] DDR_DQ[31] DDR_DQ[20] DQ4 M3 DDRB_A[1] 22 URSA_A[1] URSA_A[10] DDRA_A[10] M3 DQ4 DDR_DQ[4]
H1 A2 DDRB_A[2] DDRA_A[2] A2 H1
M7 M7 DDR_DQ[14] URSA_DQ[14]

DDRA_A[0-12]
URSA_DQ[24] DDR_DQ[24] DDR_DQ[21] DQ5 H9 DDRB_A[3] URSA_A[3] H9 DQ5 DDR_DQ[5]
A3 DDRB_A[3] DDRA_A[3] A3

DDRB_A[0-12]
URSA_DQ[26] 56 DDR_DQ[26] DDR_DQ[22] DQ6 N2 DDRB_A[9] URSA_A[9] URSA_A[9] DDRA_A[9] N2 DQ6 DDR_DQ[6]
F1 F1 AR1015
N8 A4 DDRB_A[4] AR1006 DDRA_A[4] A4 N8 DDR_DQ[6] URSA_DQ[6]
URSA_DQ[29] DDR_DQ[29] DDR_DQ[23] DQ7 DDRB_A[12] URSA_A[12] URSA_A[12] AR1013 DDRA_A[12] DQ7 DDR_DQ[7]
F9 A5 DDRB_A[5] DDRA_A[5] A5 F9
N3 DDRB_A[7] 22 URSA_A[7] 22 DDRA_A[7] N3 DDR_DQ[1] 56 URSA_DQ[1]
DDR_DQ[24] DQ8 C8 URSA_A[7] C8 DQ8 DDR_DQ[8]
AR1001 N7 A6 DDRB_A[6] DDRA_A[6] A6 N7 DDR_DQ[3] URSA_DQ[3]
URSA_DQ[23] DDR_DQ[23] DDR_DQ[25] DQ9 DDRB_A[5] URSA_A[5] URSA_A[5] DDRA_A[5] DQ9 DDR_DQ[9]
C2 A7 DDRB_A[7] DDRA_A[7] A7 C2
P2 DDRB_A[0] URSA_A[2] DDRA_A[2] P2 DDR_DQ[4] URSA_DQ[4]
URSA_DQ[16] DDR_DQ[16] DDR_DQ[26] DQ10 D7 URSA_A[0] D7 DQ10 DDR_DQ[10]
P8 A8 DDRB_A[8] DDRA_A[8] A8 P8
URSA_DQ[18] 56 DDR_DQ[18] DDR_DQ[27] DQ11 DDRB_A[2] AR1007 URSA_A[2] URSA_A[0] AR1014 DDRA_A[0] DQ11 DDR_DQ[11]
D3 A9 DDRB_A[9] DDRA_A[9] A9 D3
URSA_DQ[21] DDR_DQ[21] DDR_DQ[28] DQ12 P3 DDRB_A[4] 22 URSA_A[4] URSA_A[6] 22 DDRA_A[6] P3 DQ12 DDR_DQ[12]
D1 A10/AP DDRB_A[10] DDRA_A[10] A10/AP D1
DDR_DQ[29] DQ13 M2 DDRB_A[6] URSA_A[6] URSA_A[4] DDRA_A[4] M2 DQ13 DDR_DQ[13]
D9 A11 DDRB_A[11] DDRA_A[11] A11 D9
DDR_DQ[30] DQ14 P7 AR1008 AR1011 P7 DQ14 DDR_DQ[14]
B1 A12 DDRB_A[12] B_URSA_RASZ URSA_RASZ URSA_RASZ A_URSA_RASZ DDRA_A[12] A12 B1
DDR_DQ[31] DQ15 R2 R2 DQ15 DDR_DQ[15]
B9 B_URSA_CASZ URSA_CASZ URSA_CASZ A_URSA_CASZ B9
DDRB_A[11] URSA_A[11] URSA_A[8] 22 DDRA_A[8]
+1.8V_FRC_DDR BA0 DDRB_A[8] URSA_A[8] URSA_A[11] DDRA_A[11] BA0 +1.8V_FRC_DDR
L2 B_URSA_BA0 A_URSA_BA0 L2
L3 BA1 22 BA1 L3
VDD5 B_URSA_BA1 A_URSA_BA1 VDD5
A1 R1004 22 R1013 22 A1
VDD4 URSA_MCLK 7:B3 7:G1 URSA_MCLK1 VDD4

R1001
E1 E1

R1024
OPT

OPT
150

150
VDD3 J9 J8 CK CK J8 J9 VDD3
VDD2 M9 K8 CK R1005 22 R1014 22 CK K8 M9 VDD2
URSA_MCLKZ 7:B3 7:G1 URSA_MCLKZ1
VDD1 R1 K2 CKE CKE K2 R1 VDD1
B_URSA_MCLKE T11 U10 A_URSA_MCLKE

K9 ODT R1006 22 R1015 22 ODT K9


URSA_ODT 7:B3;X15 7:B3;Q15 URSA_ODT
VDDQ10 A9 L8 CS CS L8 A9 VDDQ10
VDDQ9 C1 K7 RAS RAS K7 C1 VDDQ9
B_URSA_RASZ R17 X17 A_URSA_RASZ
VDDQ8 C3 L7 CAS CAS L7 C3 VDDQ8
B_URSA_CASZ R17 X17 A_URSA_CASZ
VDDQ7 C7 K3 WE WE K3 C7 VDDQ7
B_URSA_WEZ T11 U10 A_URSA_WEZ
VDDQ6 C9 C9 VDDQ6
VDDQ5 E9 E9 VDDQ5
F7 LDQS R1007 56 R1016 56 LDQS F7
VDDQ4 URSA_DQS2 7:B4 7:F1 URSA_DQS0 VDDQ4
G1 UDQS R1008 56 R1017 56 UDQS G1
VDDQ3 B7 URSA_DQS3 7:B4 7:F1 URSA_DQS1 B7 VDDQ3
G3 G3
VDDQ2 G7 G7 VDDQ2
VDDQ1 G9 F3 LDM R1009 56 R1018 56 LDM F3 G9 VDDQ1
URSA_DQM2 7:B4 7:F1 URSA_DQM0
B3 UDM R1010 56 R1019 56 UDM B3
URSA_DQM3 7:B4 7:F1 URSA_DQM1

VSS5 A3 E8 LDQS R1011 56 R1020 56 LDQS E8 A3 VSS5


URSA_DQSB2 7:B4 7:F1 URSA_DQSB0
VSS4 E3 A8 UDQS R1012 56 R1021 56 UDQS A8 E3 VSS4
URSA_DQSB3 7:B4 7:F1 URSA_DQSB1
VSS3 J3 J3 VSS3
VSS2 N1 N1 VSS2
L1 NC4 AR1009 NC4 L1
VSS1 P9 P9 VSS1
NC5 B_URSA_BA0 URSA_BA0 7:D1;T11 NC5
R3 R3
NC6 B_URSA_BA1 URSA_BA1 7:D1;T10 NC6
R7 R7
Q16 B_URSA_MCLKE URSA_MCLKE 7:E1;T10
VSSQ10 Q14 B_URSA_WEZ URSA_WEZ 7:D1;T10 VSSQ10
B2 NC1 22 NC1 B2
VSSQ9 A2 A2 VSSQ9
B8 NC2 AR1010 NC2 B8
VSSQ8 E2 E2 VSSQ8
A7 NC3 7:D1;U12 URSA_BA0 A_URSA_BA0 AA17 NC3 A7
VSSQ7 R8 R8 VSSQ7
D2 +1.8V_FRC_DDR 7:D1;U12 URSA_BA1 A_URSA_BA1 +1.8V_FRC_DDR D2
AA17
VSSQ6 D8 D8 VSSQ6
7:E1;U11 URSA_MCLKE A_URSA_MCLKE Z16
VSSQ5 E7 VSSDL VSSDL E7 VSSQ5
J7 7:D1;U11 URSA_WEZ A_URSA_WEZ X14 J7
VSSQ4 22 VSSQ4
F2 F2
VSSQ3 F8 F8 VSSQ3
VSSQ2 H2 H2 VSSQ2
VSSQ1 H8 J1 VDDL VDDL J1 H8 VSSQ1

resonance Compensation

+1.8V_MEMC
+1.8V_FRC_DDR
0.1uF
C1046

0.1uF

0.1uF
C1047

C1048

C1049

C1050

C1051

C1052

C1053
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 08.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
M-STAR FRC DDR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HONG.Y.H 8 15
RESET Hot Plug input pin should be feeded over 5mA.
BCM Recommend
IC100
D3.3V
P100 BCM3556
D3.3V D3.3V GIL-G-06-S3T2
R2003
0 J23 N26
OPT EBI_ADDR3 GPIO_00
R2025 J24 L26
OPT 1 EBI_ADDR4 GPIO_01 TUNER_RESETb I3;14:A6

R409
0 H25 N25

910
POWER_DET EBI_ADDR2 GPIO_02

R410
IC400 H24 L25 R199 22

10K
12:B3;12:I4 EBI_ADDR1 GPIO_03 OPT
KIA7029AF 2 H23 K27 R2001 22
G6 BCM_AVC_DEBUG_TX1 EBI_ADDR0 GPIO_04 OPT
J25 K28 R2002 22
R408 EBI_ADDR5 GPIO_05
330 I O F26 K24
RESET 1 3 SYS_RESETb 3 D3.3V EBI_ADDR6 GPIO_06 OPT
G6 BCM_AVC_DEBUG_RX1 H28 K26 100 OPT R2005
2 10:E4 EBI_ADDR8 GPIO_07 AMP_RST
10:I2;12:I5 J26 K25 100 R2004
G EBI_ADDR9 GPIO_08 VREG_CTRL
C400 4 H27 AA27
10uF EBI_ADDR13 GPIO_09 PWM_DIM I3;4:A5;7:I5
G26 AA28 R2009 100

4.7K

R116
EBI_ADDR12 GPIO_10
J27 AA26
5 EBI_ADDR11 GPIO_11 GAIN_SWITCH 14:A6
G5 BCM_AVC_DEBUG_TX2 J28 L1
EBI_ADDR10 GPIO_12 DSUB_DET
F27 L3 OPT
EBI_ADDR7 GPIO_13
6 G24 L2 0 R189
G5 BCM_AVC_DEBUG_RX2 EBI_TAB GPIO_14
R117 H26 Y25
EBI_WE1B GPIO_15 BCM_RX
33 G27 Y26
EBI_CLK_IN GPIO_16 BCM_TX
G28 M27
EBI_CLK_OUT GPIO_17
K23 AA25
EBI_RWB GPIO_18 RF_SWITCH 14:A6
G25 R25
EBI_CS0B GPIO_19
NAND_IO[0-7] N28
GPIO_20 SIDE_CVBS_DET
N27 R105
GPIO_21 22
D3.3V NAND_IO[0] U24 AH18
NAND_DATA0 GPIO_22 AUDIO_M_CLK 3:C4
NAND_IO[1] T26 P23 0 R195
NAND_DATA1 GPIO_23 OPT
NAND_IO[2] T27 M23
NAND_DATA2 GPIO_24 A_DIM

4.7K
4.7K
4.7K
NAND_IO[3] I3;4:A6
U26 AD19 100 R2008
NAND_DATA3 GPIO_25
NAND_IO[4] U27 AE19
NAND_DATA4 GPIO_26
NAND_IO[5] V26 M4
NAND_DATA5 GPIO_27 BIT_SEL
NAND_IO[6] V27 M5 R2018 OPT 100

R194
R193
R192
NAND_DATA6 GPIO_28 LVDS_SEL
NAND_IO[7] V28 L23 R3030 100
NAND_DATA7 GPIO_29 OPT
T24 Y28
NVRAM D3.3V C3
C2
C3
NAND_CEb
NAND_ALE
NAND_REb
R23
T23
NAND_CS0B
NAND_ALE
GPIO_30
GPIO_31
Y27
G2 SF_SCK 0 R198 OPT
BCM_AVC_DEBUG_TX1
BCM_AVC_DEBUG_RX1
C7
C7
NAND_REB GPIO_32
C2 NAND_CLE T25 G3 SF_MISO 0 R196 OPT
NAND_CLE GPIO_33
C2 NAND_WEb R24 G5 SF_MOSI 0 R197 OPT
NAND_WEB GPIO_34
C3 NAND_RBb U25 G6 SF_CSB 0 R109 OPT
NAND_RBB GPIO_35
IC403 G4
GPIO_36 AV1_CVBS_DET 14:A5
L24 0 R161
AT24C512BW-SH-T GPIO_37 BLUETOOTH_RESET I3;14:I3
4.7K

W24 P25
4.7K

R422

SF_MISO GPIO_38
U23 L5 R103 100
R419

SF_MOSI GPIO_39 FRC_RESET 7:H2


A0 VCC V23 K4
1 8 SF_SCK GPIO_40
V24 K1
C416 SF_CSB GPIO_41
0.1uF L27
A1 WP GPIO_42 BCM_AVC_DEBUG_RX2 C6
2 7 M26
GPIO_43 BCM_AVC_DEBUG_TX2 C7
N23
R3016 R411 GPIO_44
A2 SCL R28
4.7K 22 GPIO_45
3 6 SCL2_3.3V I4;12:F3 R27
GPIO_46
R412 R26
GND SDA 22 GPIO_47
4 5 P28
SDA2_3.3V I4;12:F3 GPIO_48
P27
GPIO_49
K6
GPIO_50 R2024
K5 22
GPIO_51 DDC_SCL I3;14:A6
P26 22 R160 D3.3V
GPIO_52 DDC_SDA I3;14:A6
M3 22 R102
GPIO_53
M2
GPIO_54 HDMI_HPD_IN
M1
GPIO_55 COMP1_DET 14:A6

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K
R187

R184

R183

R180

R177

R176

R171

R170
L4
GPIO_56
L6
GPIO_57 COMP2_DET 14:A5
W27 22 R186
SGPIO_00 SCL0_3.3V 14:A6
W28 22 R174
SGPIO_01 SDA0_3.3V 14:A6
W26 22 R175
SGPIO_02 SCL1_3.3V 3:D3;2:AH5
W25 22 R178
SGPIO_03 SDA1_3.3V 3:D3;2:AH5
J2 22 R179
SGPIO_04 SCL2_3.3V B5;12:F3
J1 22 R181
SGPIO_05 SDA2_3.3V B5;12:F3
K3 22 R182
SGPIO_06 SCL3_3.3V 7:B6
K2
* NAND FLASH MEMORY 1Gbit (128M) SGPIO_07
22 R185
SDA3_3.3V 7:B6

Boot Strap D3.3V


D3.3V

D3.3V D3.3V D3.3V


IC101

2.7K
NAND01GW3A2CN6E

R2016

R2010

R2011

R2013

R2014

R2015
2.7K

2.7K

2.7K

2.7K

2.7K
R2032

2.7K
OPT
2.7K

* I2C MAP
2.7K
2.7K

R316
R314

R131
E3;E6 NC_1 NC_29
1 48
NAND_IO[0] NAND_IO[3] NAND_IO[2]
NC_2 NC_28
* I2C_0 : TUNER
2.7K

G6;4:A6
2.7K

E3;E6 2 47 A_DIM
R2029

E3;E6 G7;4:A5;7:I5 PWM_DIM


OPT

2.7K
2.7K

NC_3 NC_27 * I2C_1 : Audio amp, HDMI S/W


R317

3 46
BLUETOOTH_RESET
NC_4 NC_26 NAND_IO[0-7]
4 45 * I2C_2 : NVRAM,Micom
R191
R2040

NC_5 I/O7 NAND_IO[7]


5 44 G7;12:I4;3:C5 AMP_RST
NC_6 I/O6
* I2C_3 : FRC
NAND_IO[6] VREG_CTRL
6 43
Open Drain RB I/O5 HDMI_HPD_IN
NAND_RBb 7 42 NAND_IO[5]
E5 G7;14:A6 TUNER_RESETb
D3.3V R I/O4
D3.3V NAND_REb 8 41 NAND_IO[4]
E6
E NC_25
E6 NAND_CEb 9 40
R2033
2.7K

NC_7 NC_24 D3.3V


R321
2.7K

10 39
OPT

C3024
4700pF NC_8 NC_23

NAND_IO[0-7]
E3;E6 11 38 C136 10uF
NAND_IO[4] NAND_IO[5] NAND_IO[6] 6.3V
VDD_1 VDD_2
E3;E6 C114 12 37
R2031

E3;E6
R2030

C115
2.7K

2.7K

0.1uF
2.7K

VSS_1 VSS_2 0.1uF


R315

13 36
NC_9 NC_22
OPT

14 35
NC_10 NC_21
15 34
CL NC_20
E5 NAND_CLE 16 33
NAND_IO[0] : Flash Select (1) IF FUNDMENTAL IS USED => LOW
AL I/O3 NAND_IO[3]
E6 NAND_ALE 17 32
0 : Boot From Serial Flash
IF DIP IS USED => HIGH W I/O2 NAND_IO[2]
1 : Boot From NAND Flash E5 NAND_WEb 18 31
D3.3V WP I/O1 NAND_IO[1]
19 30
NAND_IO[1] : NAND Block 0 Write (DNS)
NC_11 I/O0 NAND_IO[0]
0 : Enable Block 0 Write 20 29
R136
4.7K

1 : Disable Block 0 Write NC_12 NC_19


21 28
NC_13 NC_18
NAND_IO[3:2] : NAND ECC (10) 22 27
00 : No ECC C
NC_14 NC_17
23 26
01 : 1 ECC Bit
B Q101 NC_15 NC_16
10 : 4 ECC Bit FLASH_WP_1 KRC103S
24 25
11 : 8 ECC Bit
E
NAND_IO[4] : CPU Endian (0)
0 : Little Endian
1 : Big Endian

NAND_IO[6:5] : Xtal Bias Control (1, DNS)


00 : 1.2mA
01 : 1.8mA
10 : 2.4mA (Recommand)
11 : 3.0mA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 & NAND FLASH 9 15
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
IC100 54MHz X-TAL
BCM3556 When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF

D23 B4
TU_SCLK JP204 PKT0_CLK LVDS_TX_0_DATA0_P LVDS_TX_1_DATA4_N 7:D7
C24 A4
TU_SDATA JP205 PKT0_DATA LVDS_TX_0_DATA0_N LVDS_TX_1_DATA4_P 7:D7
B26 C6
TU_SYNC JP206 PKT0_SYNC LVDS_TX_0_DATA1_P LVDS_TX_1_DATA3_N 7:D7 C230
A25 B6 22
JP207 RMX0_CLK LVDS_TX_0_DATA1_N LVDS_TX_1_DATA3_P 7:D7 12pF
B25 B3 R212
JP208 RMX0_DATA LVDS_TX_0_DATA2_P LVDS_TX_1_DATA2_N 7:D7
A26 A3
JP209 RMX0_SYNC LVDS_TX_0_DATA2_N LVDS_TX_1_DATA2_P 7:D7
A1

C3012

1008LS-272XJLC 33pF
LVDS_TX_0_DATA3_P LVDS_TX_1_DATA1_N 7:D7
A2
LVDS_TX_0_DATA3_N LVDS_TX_1_DATA1_P 7:D7
G23 D5
POD2CHIP_MCLKI LVDS_TX_0_DATA4_P LVDS_TX_1_DATA0_N 7:D7
D25 D6

2
POD2CHIP_MDI0 LVDS_TX_0_DATA4_N LVDS_TX_1_DATA0_P 7:D7

54MHz
D24 C5

X903

3
L8014
POD2CHIP_MDI1 LVDS_TX_0_CLK_P LVDS_TX_1_CLK_N 7:D7
C25 B5 54MHz_XTAL_N
POD2CHIP_MDI2 LVDS_TX_0_CLK_N LVDS_TX_1_CLK_P 7:D7
E27 B1

1
POD2CHIP_MDI3 LVDS_TX_1_DATA0_P LVDS_TX_0_DATA4_N 7:E7 54MHz_XTAL_P
E26 B2
POD2CHIP_MDI4 LVDS_TX_1_DATA0_N LVDS_TX_0_DATA4_P 7:E7

R3027
D28 C2
POD2CHIP_MDI5 LVDS_TX_1_DATA1_P LVDS_TX_0_DATA3_N 7:E7

604
D27 C3
POD2CHIP_MDI6 LVDS_TX_1_DATA1_N LVDS_TX_0_DATA3_P 7:E7
D26 D1
POD2CHIP_MDI7 LVDS_TX_1_DATA2_P LVDS_TX_0_DATA2_N 7:E7
E23 D2
POD2CHIP_MISTRT LVDS_TX_1_DATA2_N LVDS_TX_0_DATA2_P 7:E7
E24 E1
POD2CHIP_MIVAL LVDS_TX_1_DATA3_P LVDS_TX_0_DATA1_N 7:E7
F25 E2 22
CHIP2POD_MCLKO LVDS_TX_1_DATA3_N LVDS_TX_0_DATA1_P 7:E7 R211 12pF
C27 E3
CHIP2POD_MDO0 LVDS_TX_1_DATA4_P LVDS_TX_0_DATA0_N 7:E7 C229
C26 E4
CHIP2POD_MDO1 LVDS_TX_1_DATA4_N LVDS_TX_0_DATA0_P 7:E7
B28 D3 A1.2V A2.5V
CHIP2POD_MDO2 LVDS_TX_1_CLK_P LVDS_TX_0_CLK_N 7:E7
B27 D4
CHIP2POD_MDO3 LVDS_TX_1_CLK_N LVDS_TX_0_CLK_P 7:E7
A27 F5 C228 OPT
CHIP2POD_MDO4 LVDS_PLL_VREG 10uF
F24 F1
CHIP2POD_MDO5 LVDS_TX_AVDDC1P2
F23 F4
CHIP2POD_MDO6 LVDS_TX_AVDD2P5_1
E25 F2
CHIP2POD_MDO7 LVDS_TX_AVDD2P5_2
C28 C1
A3.3V A1.2V A2.5V CHIP2POD_MOSTRT LVDS_TX_AVSS_1
A28 F3
CHIP2POD_MOVAL LVDS_TX_AVSS_2

0.1uF

0.1uF

0.1uF
4.7uF

4.7uF
C4

C2000
0

0
R236

R237

C236

C239

C242

C295
LVDS_TX_AVSS_3
A5
L202 LVDS_TX_AVSS_4
BLM18PG121SN1D AC18 E5
VDAC_AVDD2P5 LVDS_TX_AVSS_5
AF20 E6
VDAC_AVDD1P2 LVDS_TX_AVSS_6
AG20 D7
VDAC_AVDD3P3_1 LVDS_TX_AVSS_7

4.7uF
AG21 E7

0.1uF

0.1uF

0.1uF
VDAC_AVDD3P3_2 LVDS_TX_AVSS_8

C214

C219

C223
C212
F7
BROAD BAND STUDIO LVDS_TX_AVSS_9
G7
LVDS_TX_AVSS_10 A1.2V
AF19 H7
VDAC_AVSS_1 LVDS_TX_AVSS_11
AD20 A2.5V
VDAC_AVSS_2

0.1uF
C2001
D3.3V AE20
R220 560AH22 VDAC_AVSS_3
R220 : BCM recommened resistor 562 ohm AD27

C2002
0.1uF
P200 C215 VDAC_RBIAS CLK54_AVDD1P2
R241 0 AH20 AD28
TJC2508-4A 0.1uF VDAC_1 CLK54_AVDD2P5
OPT AG19 AD26
VDAC_2 CLK54_AVSS
C213 AC26
JP200 0.01uF CLK54_XTAL_N 54MHz_XTAL_N I2
MNT OUT FOR BCM AH21 AC27
4.7uF

R200
1.5K

54MHz_XTAL_P
R201
1.5K

1 VDAC_VREG CLK54_XTAL_P I2
C200

AE25
JP201 CLK54_MONITOR
R242 0 Y23
PM_OVERRIDE
2 OPT M25
BSC_S_SCL
JP202 M24
BSC_S_SDA
AA23 A1.2V
3 VCXO_AGND_1
AB24
JP203 VCXO_AGND_2
R6 AC24 L203
USB_AVSS_1 VCXO_AGND_3 BLM18PG121SN1D
4 T6 AF25
A3.3V USB_AVSS_2 VCXO_AVDD1P2
R7 AF24 C233 C235
A1.2V USB_AVSS_3 VCXO_PLL_AUDIO_TESTOUT 0.1uF 4.7uF
A2.5V T7
USB_AVSS_4
T8
USB_AVSS_5 D3.3V
R3 P24
USB_AVDD1P2 RESET_OUTB
U3 F6 SYS_RESETb
USB_AVDD1P2PLL RESETB 4.7K 9:B7
L200 T4 N24
BLM18PG121SN1D USB_AVDD2P5 NMIB
T3 J5 R221
USB_AVDD2P5REF TMODE_0
R4 J4 A2.5V
USB_AVDD3P3 TMODE_1
U4 J6 L201
USB_RREF TMODE_2 BLM18PG121SN1D
Route INCM between associated V1 J3
0.1uF
0.1uF
0.1uF

4.7uF
0.1uF

USB_DM1 USB_DM1 TMODE_3


left and right signals of same channel V2 V25 A1.2V
USB_DP1 USB_DP1 SPI_S_MISO C231 C234
C201 R209 U1 AH3 10uF 0.1uF
The INCM trace ends at the 3.9K USB_DM2 USB_DM2 POR_OTP_VDD2P5
100pF U2 AB8
same point where the connector
D3.3V USB_DP2 USB_DP2 POR_VDD1P2
ground connects to the board ground T5 D3.3V
C207

C208
C209
C202
C203

(thru-hole connector pin). R210 USB_MONCDR


120 R5 H4
USB_MONPLL EJTAG_TCK
Place test points, resistors R1 H3
USB_OCD1 USB_PWRFLT_1 EJTAG_TDI OPT OPT
near audio connector. R235 R2 H2 R224 R225
Connect the other side of USB_PWRFLT_2 EJTAG_TDO
the resistor to GND as close 2.7K T2 H1 4.7K 4.7K
USB_CTL1 USB_PWRON_1 EJTAG_TMS
as possible to the ground T1 G1
connection of the associated USB_PWRON_2 EJTAG_TRSTB
H6
audio connector. EJTAG_CE0

P6
EJTAG_CE1
H5
CONNECT NEAR BCM CHIP
R218 EPHY_VREF
240 1K R219 P5 L204 A1.2V R226 R227
EPHY_RDAC BLM18PG121SN1D 4.7K 4.7K
P3 AB26
EPHY_RDN PLL_MAIN_AVDD1P2
P2 AC25

A1.2V A2.5V
N3
EPHY_RDP PLL_MAIN_AGND
AB27 R240 INCM
EPHY_TDN PLL_MAIN_MIPS_EREF_TESTOUT
N2 M6 390 L207 A1.2V
EPHY_TDP PLL_RAP_AVD_TESTOUT OPT BLM18PG121SN1D C4001 0.1uF
P1 N6 5.1
EPHY_AVDD1P2 PLL_RAP_AVD_AVDD1P2 TU_CVBS_INCM
P4 N7

0.1uF

4.7uF
3:T25 SIDE_INCM

0.1uF

4.7uF

C240
C241

C237
EPHY_AVDD2P5 PLL_RAP_AVD_AGND

C238
N4 R4009 3:T18
0.15uF
EPHY_PLL_VDD1P2 C4010 0.47uF
N1
EPHY_AGND_1 C4014
N5 AA24
EPHY_AGND_2 BYP_CPU_CLK C4002 0.1uF
P7 Y24
EPHY_AGND_3 BYP_DS_CLK SIDE_CVBS_INCM
AE24 3:T19 5.1
1K R222
BYP_SYS216_CLK AV1_INCM 3:T20
AD25 1K R223
BYP_SYS175_CLK R4011
R204 51 C206 0.015uF AE6 0.15uF
14:A5 AV1_L_IN AUDMX_LEFT1 C4011
R214 51 C210 0.015uF AD7 0.47uF
14:A5 AV1_R_IN AUDMX_RIGHT1
AF6 C4003 0.1uF C4015
AV1_INCM AUDMX_INCM1 AV1_CVBS_INCM
14:A5 AH4
R215 51 C211 0.015uF 3:T19
14:A6 COMP1_L_IN AUDMX_LEFT2
R228 51 C232 0.015uF AG5

R4000

R4004

R4006
14:A6 COMP1_R_IN AUDMX_RIGHT2 5.1
AG4
COMP1_INCM AUDMX_INCM2 COMP1_INCM

34

34

34
14:A6 AG6
R229 51 C220 0.015uF R4012
14:A5 COMP2_L_IN AUDMX_LEFT3 3:T24
R230 51 C221 0.015uF AF7 0.15uF C4016
14:A5 COMP2_R_IN AUDMX_RIGHT3 C4008
AE7 0.47uF
14:A5 COMP2_INCM AUDMX_INCM3
R231 51 C224 0.015uF AH5
14:A4 SIDE_L_IN AUDMX_LEFT4
R232 51 C225 0.015uF AG7
14:A4 SIDE_R_IN AUDMX_RIGHT4
AH6
14:A4 SIDE_INCM AUDMX_INCM4
R233 51 C226 0.015uF AD8 C4004 0.1uF 5.1
14:A3 PC_L_IN AUDMX_LEFT5 COMP1_VID_INCM 3:T23
R234 51 C227 0.015uF AF8 COMP2_INCM
14:A3 PC_R_IN AUDMX_RIGHT5 3:T22
AE8 R4010
0.15uF
14:A3 PC_INCM AUDMX_INCM5
AH7 C4009 0.47uF
OPT AUDMX_LEFT6 C4005 0.1uF
AH8 COMP2_VID_INCM C4013
51 0.015uF

R4001

R4005
AUDMX_RIGHT6 3:T21
R202 C204 AG8
AUDMX_INCM6

34

34
OPT AF5
C205 AUDMX_AVSS_1
14:D5 SPK_P AB9 5.1
R203 51 AUDMX_AVSS_2
0.015uF AA10
0.047uF
0.047uF

0.047uF
0.047uF
0.047uF
0.047uF
C2007 0.047uF
C2008 0.047uF
C2009 0.047uF
C2010 0.047uF

PC_INCM
0.047uF

0.047uF

AUDMX_AVSS_3
14:F4 SPK_INCM AB10 R4008 3:T14
AUDMX_AVSS_4 C4000 0.1uF 0.15uF
AA11 R_VID_INCM C4012 0.47uF
C222 AUDMX_AVSS_5 3:T15 C4017
AB11
0.1uF AUDMX_AVSS_6
AC8
C274

C277
C279
C296
C298
C299
C260

C273

AUDMX_LDO_CAP C4006 0.1uF


AE5 G_VID_INCM
AUDMX_AVDD2P5 3:T15

C4007 0.1uF
B_VID_INCM

R4002

R4003

R4007
3:T15

34

34

34
A2.5V

C217
10uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 AUD_IN/LVDS 10 15
IC100
BCM3556

AG28 AE18 R162 0


DS_AGCI_CTL I2S_CLK_IN
AH28 AF18 OPT
DS_AGCT_CTL I2S_CLK_OUT BCM_I2S_BIT_CLK 3:D3
AA21 AD17 R163 0
EDSAFE_AVSS_1 I2S_DATA_IN
A2.5V AB22 AH19 OPT
EDSAFE_AVSS_2 I2S_DATA_OUT BCM_I2S_DATA_OUT
AF26 AD18 R164 0 3:D3
EDSAFE_AVSS_3 I2S_LR_IN
A1.2V AF27 AG18 OPT
BLM18PG121SN1D EDSAFE_AVSS_4 I2S_LR_OUT 0 BCM_I2S_WORD_CLK 3:D3
AF28 AG26 R165
L102 EDSAFE_AVSS_5 AUD_LEFT0_N A2.5V
AG27 AH26 OPT
EDSAFE_AVDD2P5 AUD_LEFT0_P
AE26 AF23
EDSAFE_DVDD1P2 AUD_AVDD2P5_0
AE28 AA20 C147 C155 C162
C113 C116 EDSAFE_IF_N AUD_AVSS_0_1 0.01uF 0.1uF 10uF
A1.2V AE27 AB21
0.1uF 4.7uF C144 EDSAFE_IF_P AUD_AVSS_0_2
0.1uF AD24 AC22
L103 PLL_DS_AGND AUD_AVSS_0_3
AB19 AC23
PLL_DS_AVDD1P2 AUD_AVSS_0_4
BLM18PG121SN1D C119 C122 AB25 AD23
PLL_DS_TESTOUT AUD_AVSS_0_5 R168 0
0.1uF 4.7uF AH25
A1.2V A2.5V AUD_RIGHT0_N
AG25 OPT
AUD_RIGHT0_P
AB18 AH23 R166 0
BLM18PG121SN1D SD_V5_AVDD1P2 AUD_LEFT1_N
C111 C112 AC17 AG23 OPT
SD_V5_AVDD2P5 AUD_LEFT1_P R167 0
0.1uF 0.1uF
L104 C120 C123 AB17 AG24
SD_V5_AVSS AUD_RIGHT1_N
1000pF 0.01uF AD14 AH24 OPT
BLM18PG121SN1D SD_V1_AVDD1P2 AUD_RIGHT1_P
AD16 AE22
SD_V1_AVDD2P5 AUD_AVDD2P5_1
AB15 AB20 C148 C156 C163
L105 SD_V1_AVSS_1 AUD_AVSS_1_1
AC15 AC21 0.01uF 0.1uF 10uF
C117 SD_V1_AVSS_2 AUD_AVSS_1_2
1000pF C118 AD13 AE23
0.01uF SD_V2_AVDD1P2 AUD_AVSS_1_3 R169 0
AE13 AF21
SD_V2_AVDD2P5 AUD_LEFT2_N
AC13 AE21 OPT
SD_V2_AVSS_1 AUD_LEFT2_P R172 0
AB14 AF22
SD_V2_AVSS_2 AUD_RIGHT2_N
AC14 AG22 OPT
SD_V2_AVSS_3 AUD_RIGHT2_P
14:A4 DSUB_R AC12 AD21
SD_V3_AVDD1P2 AUD_AVDD2P5_2 A2.5V
14:A4 R_VID_INCM AD12 AC20 C149 C157 C164 A2.5V
SD_V3_AVDD2P5 AUD_AVSS_2_1 0.01uF 0.1uF 10uF
14:A4 DSUB_G AB13 AD22

470

270
SD_V3_AVSS_1 AUD_AVSS_2_2
14:A3 G_VID_INCM AA14 AH2
SD_V3_AVSS_2 AUD_SPDIF SPDIF_OUT14:A3

OPT
14:A3 DSUB_B AC11 AC6
SD_V4_AVDD1P2 SPDIF_AVDD2P5
AD11 AE4

R3041
OPT
14:A3 B_VID_INCM

R3042
SD_V4_AVDD2P5 SPDIF_AVSS C150 +5.0V
AB12 AF3 0.1uF
C127 SD_V4_AVSS SPDIF_IN_N
0.1uF AD10 AH1

75

R118 75
14:A6 COMP1_Y_IN

R119 75
SD_R SPDIF_IN_P
AC10

R2035
COMP1_Pr_IN HDMI_HPD_IN_5MA

10pF

10pF
14:A5

10pF
C101

C102

C103
SD_INCM_R
R115
14:A6 COMP1_Pb_IN C128 0.1uF AE9 R2036
SD_G C
1K

0
14:A6 COMP1_VID_INCM AF9 AG1
SD_INCM_G HDMI_RX_0_CEC_DAT Q906 B
OPT

C129 0.1uF AH9 AA6 ISA1530AC1 HDMI_HPD_IN 9:G4;9:I3


R120 91

R127 91

R129 91

SD_B HDMI_RX_0_HTPLG_IN HDMI_HPD_IN_5MA G5


AG9 AA5 R188 10K A2.5V
10pF

C130 SD_INCM_B HDMI_RX_0_HTPLG_OUT E


C104

0.1uF AG15 AB3 0 R157


SD_Y1 HDMI_RX_0_DDC_SCL HDMI_SCL 2:AA19
C131 0.1uF AE15 Y6 0 R158
SD_PR1 HDMI_RX_0_DDC_SDA HDMI_SDA 2:AA19
C132 0.1uF AF15 AC4 499 R152
SD_PB1 HDMI_RX_0_RESREF C3006
AH15 AC1
SD_INCM_COMP1 HDMI_RX_0_CLK_N HDMI0_RXC-_BCM 2:AA18 0.1uF
C133 0.1uF AG16 AC2
14:A5 COMP2_Y_IN SD_Y2 HDMI_RX_0_CLK_P HDMI0_RXC+_BCM 2:AB18 16V
C134 0.1uF AF16 AD1
14:A5 COMP2_Pr_IN SD_PR2 HDMI_RX_0_DATA0_N HDMI0_RX0-_BCM 2:AB18
C135 0.1uF AH17 AD2
14:A5 COMP2_Pb_IN SD_PB2 HDMI_RX_0_DATA0_P HDMI0_RX0+_BCM 2:AB18 A3.3V
AH16 AE1
14:A5 COMP2_VID_INCM SD_INCM_COMP2 HDMI_RX_0_DATA1_N HDMI0_RX1-_BCM 2:AC18
OPT 0 R147 AG14 AE2
OPT

HDMI0_RX1+_BCM
R135 91

R138 91

R140 91 SD_Y3 HDMI_RX_0_DATA1_P 2:AC18


OPT 0 R148 AE14 AF1 BLM18PG121SN1D
SD_PR3 HDMI_RX_0_DATA2_N HDMI0_RX2-_BCM 2:AC18 L109
OPT 0
10pF

R149 AF14 AF2


C105

OPT SD_PB3 HDMI_RX_0_DATA2_P HDMI0_RX2+_BCM 2:AD18


R145 34 C126 0.1uF AH14 AD3 A1.2V A2.5V

OPT
SD_INCM_COMP3 HDMI_RX_0_VDD3P3
OPT 0 R150 AH10 AE3
SD_L1 HDMI_RX_0_VDD1P2
OPT 0 R151 AG10 AC3
SD_C1 HDMI_RX_0_VDD2P5
C107 0.1uF AE10 AD4 C145 C153 C160
SD_INCM_LC1 HDMI_RX_0_AVSS_1 4.7uF 0.1uF 0.1uF
R142 91 OPT 0 R154 AE11 AB5
SD_L2 HDMI_RX_0_AVSS_2 BLM18PG121SN1D
OPT 0 R155 AF11 AB6
SD_C2 HDMI_RX_0_AVSS_3 L107
R143 91 C108 0.1uF AH11 AG2
SD_INCM_LC2 HDMI_RX_0_AVSS_4
OPT 0 R156 AH13 AB4
SD_L3 HDMI_RX_0_AVSS_5
R141 OPT 0 R159 AE12 AA7
75 SD_C3 HDMI_RX_0_AVSS_6
OPT C109 0.1uF AF12 Y8
OPT SD_INCM_LC3 HDMI_RX_0_PLL_AVSS C158 C151 C165
C110 0.1uF AD9 AC5 1000pF 0.01uF 10uF
14:A6 TU_CVBS_IN SD_CVBS1 HDMI_RX_0_PLL_DVDD1P2
C124 0.1uF AG11 W8
14:A5 AV1_CVBS_IN SD_CVBS2 HDMI_RX_0_PLL_DVSS
C125 0.1uF AG12
14:A5 SIDE_CVBS_IN SD_CVBS3 D3.3V

10K
10K

10K

10K
AF13

R2037
SD_CVBS4

OPT
14:A6 TU_CVBS_INCM AC9 AA3
14:A5 AV1_CVBS_INCM SD_INCM_CVBS1 HDMI_RX_1_CEC_DAT
AF10 V4

R146

R2039
SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN

R2038
14:A5 SIDE_CVBS_INCM A2.5V AH12 U6
A2.5V
SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT
AG13 V5
AF17
SD_INCM_CVBS4 HDMI_RX_1_DDC_SCL
V3
R4020 SD_SIF1 HDMI_RX_1_DDC_SDA
R137 AG17 W4 499 R153
10K 10K SD_INCM_SIF1 HDMI_RX_1_RESREF
AD15 W2
0.1uF SD_FB HDMI_RX_1_CLK_N
R128 C106 A1.2V AE16 W3
0 SD_FS HDMI_RX_1_CLK_P
L106 AE17 Y1
14:A6 TU_SIF SD_FS2 HDMI_RX_1_DATA0_N
BLM18PG121SN1D AB16 Y2
R3055 HDMI_RX_1_DATA0_P A3.3V
R139 AA15 PLL_VAFE_AVDD1P2 AA2
240 C121 C140
12K PLL_VAFE_AVSS HDMI_RX_1_DATA1_N
0.1uF 4.7uF AC16
HDMI_RX_1_DATA1_P AA1
AG3 PLL_VAFE_TESTOUT AB2 BLM18PG121SN1D
RGB_HSYNC HDMI_RX_1_DATA2_N
R4021

AF4 AB1 L110


12K

C4020 RGB_VSYNC HDMI_RX_1_DATA2_P


120
R3056

Y3 A1.2V A2.5V
0.1uF HDMI_RX_1_VDD3P3
Y4
HDMI_RX_1_VDD1P2
W5
HDMI_RX_1_VDD2P5
W1
HDMI_RX_1_AVSS_1
U5 C146 C154 C161
14:A3 RGB_HSYNC HDMI_RX_1_AVSS_2 4.7uF 0.1uF 0.1uF
W6
14:A3 RGB_VSYNC HDMI_RX_1_AVSS_3 BLM18PG121SN1D
CONNECT NEAR BCM CHIP U7
HDMI_RX_1_AVSS_4 L108
V7
HDMI_RX_1_AVSS_5
W7
HDMI_RX_1_AVSS_6
U8
HDMI_RX_1_AVSS_7
V8
HDMI_RX_1_AVSS_8
Y5
HDMI_RX_1_AVSS_9
V6
HDMI_RX_1_PLL_AVSS
AA4
HDMI_RX_1_PLL_DVDD1P2
Y7 C159 C152 C166
HDMI_RX_1_PLL_DVSS 1000pF 0.01uF 10uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 2008. 10. 15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H.
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 VIDEO IN 11 15
14:E6
14:E7

14:E5
9:A7;B3

14:E5

4:C5
UCOM_SDA_3.3V
UCOM_SCL_3.3V

LED_WARM_STBY

LED_POWER_ON
POWER_DET

ERROR_OUT
R475
+3.3V_ST

1K

R435 : READY FO 1.2V BCM ENABLE


D3.3V
R454 2K

2:AD26
R451 2K

100

100

100
100

100

OPT

OPT
HDMI_CEC

4.7K

100

R435

R439
+3.3V_ST +3.3V_ST

R440
R464

R471

R474
R470
IC402 +3.3V_ST

OPT
R3010

R444
R442
6.8K

0
+3.3V_ST

R414
10K

P1.4/DA3
P1.3/DA2
P1.2/DA1
P1.1/DA0
P1.0/ET2
P4.2/AD2
R407
47K
KIA7029AF

R2023
C GND C410 C411
C407

33K
Q401 0.1uF 100uF
I O B OPT
16V 16V

P5.0
P5.1
P5.2
P5.3
1 3 OPT
2SC3875S(ALY)

VDD
2
E
C402 G C403 GND
0.1uF 0.1uF +3.3V_ST R430
16V 16V GND
100

R401

44
43
42
41
40
39
38
37
36
35
34
1K
HSYNC/P1.5 P5.4

4.7K
R427
GND GND GND
1 33 R465OPT 100
PANEL_CTL 4:H1

M5V_ON
OPT VSYNC/P1.6 2 32 P5.5 R466 100
R403 0
R416 0
P1.7/SOGI 3 31 P5.6 R468 100

OPT
INV_ON/OFF 4:C5
+3.3V_ST
RST P5.7/CLKO2

OPT
4 30 R467 22
RL_ON 4:C7;14:E5

R402

R3017

R3018
HSCL1/P3.0/RXD P7.0/HBLANK

4.7K

4.7K
R406 R431 100
R417 22
5 29 RESET 9:A7
GND 4.7K
IC406 OPT
9:G7;14:A4 DDC_SCL P4.3/AD3 6 28 P4.1/AD1
HSDA1/P3.1/TXD MTV416GMF P7.1/VBLANK
9:G7;14:A4 DDC_SDA R420 22 7 27 R469 100
FLASH_WP_1 9:C1
OPT
R421 4.7K
P3.2/INT0 8 26 P7.2/HCLAMP
14:A3;14:E6 IR AMP_RST 9:G7;9:I3;3:C5
R405
220 R423 OPT P3.3/INT1 9 25 P6.7 R449 100
14:H2 UCOM_RX
OPT
R424 22
ISDA/P3.4/T0 10 24 P6.6 R450 100 OPT +5.0V
R404
OPT
14:I1 UCOM_TX
220
R425 22
ISCL/P7.5 11 23 P6.5

15K

R472
4.7K
12
13
14
15
16
17
18
19
20
21
22

R460

6.8K
C412

68K
R461
C3016 R429 0.1uF

OPT
R428
R418 0.1uF OPT OPT EDID_WP 14:A4
4.7K

OPT
16V

HSDA2/P7.4
HSCL2/P7.3
X2
X1
VSS
P4.0/AD0
P6.0/CLKO1
P6.1
P6.2
P6.3
P6.4
C
GND B Q907
+3.3V_ST RT1N141C-T112-1
R459
4.7K E

GND R447 4.7K


POWER DETECT +3.3V_ST
+5V_ST +24V
OPT
R455
4.7K GND
R452 R462
+5.0V 47K 100

R485 KEY2 14:E6


IC405 +3.3V_ST GND
+12V OPT 10K 9:A7;I4 R456
R481 R482 R484
OPT

R478 POWER_DET 30K 100


30K KEY1 14:E6
10K 0 OPT

R453
100
OPT C

22

1K
OPT

0
0
R479 X401
R476 B Q405 24LC16BT-I/SN 24MHz
15K 2SC3052 R3024 OPT
1K 0 C414

R446
R415

OPT C

R441

R443

R445
R413

C413

22

22
R3031 E C408 C409 0.1uF
0 A0 VCC 0.1uF
B Q404 R480 1 8 22pF 22pF GND 16V
IC1003 C406

OPT

OPT
2.2K
R432

READY FO 1.2V BCM ENABLE


50V 50V

R434

R436
2SC3052
47K

OPT OPT NCP803SN293 0.1uF


R477 E A1 WP 16V
2 7
4.7K

4.7K

6.8K RESET VCC OPT


2 3
1 R486 A2 SCL
R487 3 6
0 GND
R3026

GND GND
100K
5.1K

OPC_EN
AMP_MUTE
OPT VSS SDA
4 5

SDA2_3.3V

SCL2_3.3V

3:E3
R483 GND

7:I5
0

9:B5;9:I4

9:B5;9:I4

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LIM.K.R MICOM 12 15
D1.2V

C243 C249 C250 C251 C252 C253 C254 C286 C287


0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF 10uF 33uF 33uF

IC100
BCM3556

D1.2V D1.2V
IC100 AD5 P16
BCM3556 AD6
DVSS_1 DVSS_62
R16
DVSS_2 DVSS_63
J7 T16
DVSS_3 DVSS_64
K7 U16
H8 DVSS_4 DVSS_65
VDDC_1 L7 V16
C244 C246 C256 C258 C259 C262 C265 C266 C288 C290 J8 DVSS_5 DVSS_66
1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF VDDC_2 M7 AA16
K8 DVSS_6 DVSS_67
VDDC_3 AB7 D17
L8 DVSS_7 DVSS_68
VDDC_4 AC7 L17
M8 DVSS_8 DVSS_69
VDDC_5 G8 M17
N8 DVSS_9 DVSS_70
VDDC_6 D9 N17
P8 DVSS_10 DVSS_71
VDDC_7 AA9 P17
R8 DVSS_11 DVSS_72
VDDC_8 G10 R17
AA8 DVSS_12 DVSS_73
D3.3V VDDC_9 A11 T17
H9 DVSS_13 DVSS_74
VDDC_10 L11 U17
H10 DVSS_14 DVSS_75
VDDC_11 M11 V17
H11 DVSS_15 DVSS_76
VDDC_12 N11 AA17
H12 DVSS_16 DVSS_77
VDDC_13 P11 AC19
C245 C255 C257 C261 C263 C264 C267 C289 C291 H13 DVSS_17 DVSS_78
4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF VDDC_14 R11 G18
H14 DVSS_18 DVSS_79
VDDC_15 T11 L18
H15 DVSS_19 DVSS_80
VDDC_16 U11 M18
H16 DVSS_20 DVSS_81
VDDC_17 V11 N18
H17 DVSS_21 DVSS_82
VDDC_18 D12 P18
H18 DVSS_22 DVSS_83
VDDC_19 G12 R18
H19 DVSS_23 DVSS_84
VDDC_20 L12 T18
D3.3V H21 DVSS_24 DVSS_85
VDDC_21 M12 U18
J21 DVSS_25 DVSS_86
VDDC_22 N12 V18
K21 DVSS_26 DVSS_87
VDDC_23 P12 D20
L21 DVSS_27 DVSS_88
VDDC_24 R12 G20
M21 DVSS_28 DVSS_89
C216 C268 C269 C270 C271 C292 C293 C294 VDDC_25 T12 H20
N21 DVSS_29 DVSS_90
0.1uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF VDDC_26 U12 A21
P21 DVSS_30 DVSS_91
VDDC_27 V12 E21
R21 DVSS_31 DVSS_92
VDDC_28 L13 F21
T21 DVSS_32 DVSS_93
VDDC_29 M13 G21
A3.3V U21 DVSS_33 DVSS_94
VDDC_30 N13 E22
V21 DVSS_34 DVSS_95
VDDC_31 P13 F22
W21 DVSS_35 DVSS_96
R205 VDDC_32 R13 G22
Y21 DVSS_36 DVSS_97
D1.8V 20 VDDC_33 T13 H22
DVSS_37 DVSS_98
U13 J22
DVSS_38 DVSS_99
V13 K22
AH27 DVSS_39 DVSS_100
AGC_VDDO G14 L22
D3.3V DVSS_40 DVSS_101
L14 M22
DVSS_41 DVSS_102
C247 C272 C275 C276 C278 C280 C297 C2003 M14 N22
C2004 AA12 DVSS_42 DVSS_103
0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 4.7uF 4.7uF 33uF 0.1uF VDDO_1 N14 P22
AA13 DVSS_43 DVSS_104
VDDO_2 P14 R22
AA18 DVSS_44 DVSS_105
VDDO_3 R14 T22
AA19 DVSS_45 DVSS_106
VDDO_4 T14 U22
E28 DVSS_46 DVSS_107
VDDO_5 U14 V22
L28 DVSS_47 DVSS_108
VDDO_6 V14 W22
U28 DVSS_48 DVSS_109
VDDO_7 L15 Y22
AB28 DVSS_49 DVSS_110
VDDO_8 M15 AA22
D1.8V DVSS_50 DVSS_111
D1.8V N15 W23
DVSS_51 DVSS_112
P15 AB23
A9 DVSS_52 DVSS_113
DDRV_1 R15 F28
G9 DVSS_53 DVSS_114
DDRV_2 T15 M28
C248 C281 C282 C283 C284 C285 C2005 C2006 G11 DVSS_54 DVSS_115
1000pF 0.01uF 0.01uF 0.01uF 0.01uF DDRV_3 U15 T28
1000pF 1000pF 1000pF G13 DVSS_55 DVSS_116
DDRV_4 V15 AC28
A14 DVSS_56 DVSS_117
DDRV_5 A16
G15 DVSS_57
DDRV_6 G16
G17 DVSS_58
DDRV_7 L16
A19 DVSS_59
DDRV_8 M16
G19 DVSS_60
DDRV_9 N16
DVSS_61

D1.8V

C365 C364 C363 C357 C348 C320 C319 C318 C304


C356
0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 10V 16V 16V 16V 16V 16V 16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL DVR DV 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
JANG.J.H BCM3549 POWER 13 15
USB JACK & USB +5V Current Protection

D3.3V
+5.0V
BCM Tolerance

MLB-201209-0120P-N2
R712 R713
USB_POWER_OUT_2 IC701 2.7K
MIC2009YM6-TR 2.7K L701

P701 * CONTROL IR & LED


GF05C-96S VOUT VIN
6 1
P1101
12507WR-14L ILIMIT GND C701
1 R701 0 5 2
1 TU_SCLK 10:D1
0.1uF
2 2 16V
TU_SDATA 10:D1
3 3 FAULT/ ENABLE
TU_SYNC 10:D1 4 3
4 SCL
4 1 R702

CDS3C05HDMI1

CDS3C05HDMI1
UCOM_SCL_3.3V 12:F6 USB_CTL1
5 5 180
SCL0_3.3V 9:I4 10:D5
6 6
SDA0_3.3V 9:I4 SDA
7 2 UCOM_SDA_3.3V
7 OPT OPT 12:F6
8 R707 0 C2019 C2020
8 TUNER_RESETb9:G7;9:I3 R711
9 R703 0 GND ZD1106 ZD1107 1000pF 1000pF USB_OCD1 10:D4
9 R4063 TU_CVBS_IN 11:B4 3
0 50V 50V 47
10 10 L1103
11 BG2012B080TF USB_POWER_OUT_2
11 KEY1
12 R704 0 4 KEY1 P704
12 TU_SIF 11:B3 12:H3
13 R4051 0 L1104 KJA-UB-0-0037 Make this trace minimum 12 mil
13 BG2012B080TF
14 KEY2 L703
14 5 KEY2 12:H3
15 15 R705 0
GAIN_SWITCH 9:G7 BLM18PG121SN1D
16 16 1
RF_SWITCH 9:G6 5V_ST +5V_ST
17 R706 0 6
17
18 R4052 0
18 C1102 C1104 CB3216PA501E 2
19 GND C1101 USB_DM2 10:D4
19 COMP1_L_IN 10:C6 7 0.1uF 0.1uF L1101 C705 C3018
ZD1101 0.1uF
20 20 L1102 100uF 100uF
COMP1_R_IN 10:C6 ZD1103
21 BG2012B080TF 3 16V
21 COMP1_DET 9:G4 IR USB_DP2 10:D4
22 R4053 0 8
22 IR 12:D4;A3
23 23 OPT
COMP1_Y_IN 11:B5 L1105 +3.3V_ST 4
24 GND ZD1104 C1103 Not enough space
24 COMP1_Pb_IN 11:B5 9 CB3216PA501E +3.3V_ST
25 100pF
25 COMP1_Pr_IN 11:B5

5
0.1uF
26

C1107

R2020
26 R4054 3.3V_ST D701
0 10 C1109 D702
27

10K
27 1000pF CDS3C05GTA
5.6V CDS3C05GTA
28 50V
28 10:C6 R3036 OPT 5.6V
COMP2_L_IN WARM_ST
29 29 0 OPT
COMP2_R_IN 10:C6 11
30 30
C2017

CDS3C05HDMI1
R4055 0 COMP2_DET 9:G4
31 31 0.1uF C
POWER_ON
32 12 16V R2021
32 11:C4 Q904 B 0
COMP2_Y_IN

ZD1108

ZD1102
33 LED_WARM_STBY

8.2V

5.6V
33 11:C4 2SC3052

R3037
COMP2_Pb_IN GND OPT
34

120K
34

OPT
COMP2_Pr_IN 11:C4 13 OPT E
35 35
R4056 0 +3.3V_ST
36 36
AUDIO_OUT
37 14 SPK_P
37

R3035
AV1_L_IN 10:C5 R1102 OPT
38 10:C6 OPT

10K
38 10:C5 C1105
R4057 0 AV1_R_IN 15 0
39 39 0.1uF R3038 R3039
16V 0 0
40 40
AV1_CVBS_IN 11:B4 RL_ON
41 ZD1105 OPT C3015
41 9:G5
42 42
R4058 0
AV1_CVBS_DET OPT 0.1uF
16V
C
R3034 R3040 * Blue Tooth
43 43 Q905 B 4.7K 0
2SC3052 LED_POWER_ON
44 44
SIDE_CVBS_IN 11:B3 D3.3V
45 45 JP1112 E
SIDE_CVBS_DET 9:G6

CB3216PA501E
46 R4059 0
46
47 47
SIDE_L_IN 10:C6 L702
48 48
SIDE_R_IN 10:C6
49 49
10:C6 11
50 D1.2V C1108 0.47uF JP703
50
51 SPK_INCM
51 10
52 52 9:G7;12:D5
DDC_SCL

R1105

5.1
53 C703
53 DDC_SDA 9:G7;12:D4 100uF
54 +5V_ST 9
54 16V
55 JP702 R3022
55 27
56 56 USB_DM1 10:D4
PCB Path(SPK_INCM) go along The SPK_N/P 8
57 D703
57 CDS3C05GTA
58 58 5.6V
59 7 OPT JP704
59 EDID_WP 12:I4
60 R3023
60 9:G7 27
DSUB_DET
61 61 D704 USB_DP1 10:D4
6
62 CDS3C05GTA
62 11:B5 5.6V
R4050 0 DSUB_R
63 63 OPT
64 5
64 11:B5
R4060 0 DSUB_G R2022
65 65
0
66 BLUETOOTH_RESET
66 11:B5 4
R4061 0 DSUB_B
67 67
68 68
69 3
69 11:D2
RGB_HSYNC R2019
70 70
RGB_VSYNC 11:D2 D3.3V 0
71 VREG_CTRL
71 2
72 R4062 0
72
73 73
PC_L_IN 10:C6
74 1
74 10:C6
PC_R_IN
75 75
76 76
77 77 12507WR-10L
78 78 P705
79 79
SPDIF_OUT 11:E5
80 80
81 81
RS232C_RxD I2 D2.5V
82 82
RS232C_TxD I2
83 83
IR 12:D4;E6
84 84
85 85
86 +12V
86 RS232_SWITCHING
87 87
88 88 R512
89 0
89
90 90 RS232_BYPASS

91 91 IC502
92 92 MC14053BDR2G
93 0ISTL00024A +5V_ST
93
94 94
L506
95 95 R510 MLB-201209-0120P-N2
0 Y1 VDD
96 96 1 16
9:G6 BCM_RX
C537
Y0 Y A3 C536
97 2 15 47uF
12:D4 UCOM_RX RS232C_RxD
97

16V 0.1uF 16V


Z1 X RS232_BYPASS
3 14 RS232C_TxD A3

R516
0
R514
Z X1 0
4 13 BCM_TX 9:G6

Z0 X0 +5.0V
5 12 UCOM_TX 12:D4
R517
INH A 4.7K R_RS232_SWITCHING
6 11

RS-232 SET ON PROBLEM


VEE B R517-*1
7 10
2.7K
R515
VSS C 100K
R515-*1
8 9 4.7K

RS-232 SET ON PROBLEM

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 2008.10.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR DO.J.G
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETC SUB BOARD I/F 14 15
A B C D E F G H I J

COMPONENT1/2,AV1/2 +3.3V +3.3V R,G,B PC&DDC


+5V_ST

R231

R202
10K

10K
R232 R205
1K 1K
COMP1_DET COMP2_DET D227

ZD141
ENKMC2838-T112

5.1V

ZD233
3:T21 3:T23 A1

5.1V
C278

ZD232
C279 C

5.1V
100pF

ZD234
5.1V
100pF
50V A2
7 50V
BCM RECOMMAND

L212 L215
R292 CM2012FR27KT CM2012FR27KT R295
15 15
COMP1_Y_IN COMP2_Y_IN

ZD227
5.1V
IC202

ZD202
3:T21 50V 3:T23 C253

5.1V
50V 50V C254
27pF +5V M24C02-RMN6T

ZD228
27pF 27pF C242 0.1uF

5.1V
4700pF

ZD203

R255
4.7K
C202

5.1V
C233

R253
4.7K
C213 R258 50V
0.1uF 50V
10K
50V E0 VCC
27pF 1 8 OPT
L213 C228 L216
R293 CM2012FR27KT CM2012FR27KT R296 R247 R260
15 15 22 E1 WC 0
COMP1_Pb_IN COMP2_Pb_IN 2 7 EDID_WP
RGB_VSYNC

ZD206

ZD229
JK209

5.1V

5.1V
3:T21 50V 3:T22 3:T14 3:T16
50V PPJ225-01 50V
27pF E2 SCL

ZD205

ZD209
27pF 27pF

5.1V

5.1V
3 6 DDC_SCL

D2A

D2B

D3A

D3B

VCC
C234 C203 C214

Q2

Q3
9J [GN]E-LUG 3:T17
50V [GN]O-SPRING-L 5J 4A [GN]O-SPRING-S VSS SDA
4 5

10

11

12

13

14
27pF DDC_SDA
L214 C229 L217 3:T17
R294 CM2012FR27KT [GN]CONTACT-L 6J 3A [GN]CONTACT-S CM2012FR27KT R297 R257
22 R259
15 15

74F08D
22

IC201
COMP1_Pr_IN 9K [BL]E-LUG COMP2_Pr_IN

ZD204
5.1V

ZD244
6

5.1V
3:T20 50V 50V 50V 3:T22
ZD230 [BL]C-LUG-L 7K 8B [BL]C-LUG-S 27pF
27pF 5.1V 27pF

ZD252
5.1V
C235 C204 C215
9L [RD]E-LUG_1

1
D226 D230
50V [RD]C-LUG_L 7L 8C [RD]C-LUG-S ADMC5M03200L
ADMC5M03200L

GND

Q1

D1B

D1A

Q0

D0B

D0A
27pF 5.6V
C230 5.6V
9M [WH]E-LUG_1
C232 C208
[WH]C-LUG-L_1 7M 8D [WH]C-LUG-S_1
COMP1_L_IN COMP2_L_IN D222
C266 ADUC30S03010L
470K
R234

R207
470K
0 0 R248
ZD212

ZD210
3:T22 9N [RD]E-LUG_2 3:T23
5.1V

5.1V
C268 R236 1uF 1uF R217 100pF 22 30V
100pF 25V 25V 50V RGB_HSYNC
ZD207

ZD213
[RD]O-SPRING-L_1 5N 4E [RD]O-SPRING-S_1
5.1V

5.1V
50V 3:T14 D221
ADUC30S03010L
[RD]CONTACT-L_1 6N 3E [RD]CONTACT-S_1 30V
9P [YL]E-LUG BCM Reference
C231 C207
COMP1_R_IN [YL]O-SPRING-L 5P 4F [YL]O-SPRING-S COMP2_R_IN

ZD214
0 0

5.1V
470K
R233

3:T21 C269 C267 3:T23

R206
470K
1uF 1uF L207
ZD208

R235 [YL]CONTACT-L 6P 3F [YL]CONTACT-S R216


5.1V

100pF 25V 25V 100pF 0

ZD215
5.1V

ZD250
50V 50V 3:T15 DSUB_B

5.1V
ZD211

9Q [WH]E-LUG_2
5.1V

C243 L207-*1

ZD249
5.1V
[WH]C-LUG-L_2 7Q 8G [WH]C-LUG-S_2 47pF
50V BG1608B121F RGB_BEAD

5 AV1_CVBS_IN
R204
15
[RD]O-SPRING-L_2 5R
9R

4H
[RD]E-LUG_3

[RD]O-SPRING-S_2
R203
15
3:T19
SIDE_CVBS_IN
+5V

3:T18 C217 C216 L208 R262


ZD221

ZD216
[RD]CONTACT-L_2 6R 3H [RD]CONTACT-S_2
5.1V

5.1V
47pF 47pF 0 10K
3:T15 DSUB_G

ZD248
50V 50V

5.1V
ZD231

ZD217
+3.3V
5.1V

5.1V
+3.3V C244 L208-*1 1K

ZD247
47pF R264

5.1V
R211 50V BG1608B121F RGB_BEAD DSUB_DET
10K R210 3:T16
R215
1K 10K 3:T19
R214
AV1_CVBS_DET SIDE_CVBS_DET C280 D231

ZD243
ZD236

5.1V
1K
5.1V

3:T18 C206 C205 L209 100pF ADMC5M03200L


0.1uF 0.1uF 50V 5.6V

ZD235
0
ZD254

OPT
5.1V

0
5.1V

ZD246
16V 16V 3:T16 DSUB_R

5.1V

R291

R290
C245 L209-*1

ZD245
5.1V
47pF
50V BG1608B121F RGB-BEAD
C210
R219 1uF 25V
0 C209 R218 3:T20
AV1_L_IN SIDE_L_IN
3:T18 C221 0 C220
1uF
ZD223

ZD218
5.1V

5.1V
100pF R213 25V 100pF
470K R212
ZD224

ZD219
5.1V

5.1V
470K
4

11

12

13

14

15
C212
R221 C211
0 1uF 25V
R220 3:T20
JK208

16
AV1_R_IN SIDE_R_IN

10
6

9
3:T18 0
C219 1uF
KCN-DS-1-0089
ZD225

ZD220

100pF
5.1V

5.1V

R209 R208 25V C218


470K 470K
ZD226

ZD222

100pF

5
5.1V

5.1V

RS-232C PC AUDIO
3 +5V_ST

L211 JK206
BLM18PG121SN1D PEJ024-01

3 E_SPRING
C259

R252
0.1uF
50V JK207 6A T_TERMINAL1
IC203 4.7K
R285 C246
0 7A B_TERMINAL1 R249
MAX3232CDR R251
RS232C_RxD 3:T12 KCN-DS-1-0088 PC_R_IN

ZD253
5.1V
4.7K 1uF 0
C257 R286 R_SPRING 3:T13

R245
470K
4 25V

ZD251
0.47uF 0

5.1V
25V RS232C_TxD 3:T12 1
C1+ 1 16 VCC T_SPRING
5
C258 R279 6
0.1uF 220 C247
50V 2 7B B_TERMINAL2 R250
V+ 2 15 GND R256
50V

50V

PC_L_IN

ZD242
100

5.1V
1uF 0 3:T13
OPT R278 T_TERMINAL2

R246
470K
7 6B 25V

ZD241
220

5.1V
220pF

220pF

C1- 3 14 DOUT1
3
C255 SHIELD_PLATE
ZD238

8
ZD240
5.1V

0.47uF
5.1V

25V 50V 50V 8

2 C2+ 4 13 RIN1 47pF 47pF


ZD237

ZD239
5.1V

5.1V

C270 C271 4
C249

C250

R254
100
C2- 5 12 ROUT1 9
OPT
C251
0.47uF 5
25V V- DIN1
6 11 10
+5V_ST
SPDIF OPTIC JACK
+5V_ST
US_Commercial

DOUT2 7 10 DIN2
3.3K
R263

RIN2 8 9 ROUT2 JK204


R289
3.3K

+5V JST1223-001
+3.3V
OPT

US_Commercial
C
R288 R265 GND

Fiber Optic
0 100K B Q201
2SC3052 R201
100K
R266

R283 C US_Commercial 1K VCC

2
R287 E
US_Commercial

100
10K B Q202
3:T11 IR
2SC3052
R284 OPT VINPUT

3
SPDIF_OUT
100 E

4
OPT G4;3:T12
ZD201 C201

1 OPT
5.6B
0.1uF
50V
FIX_POLE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 08.11.14
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR DO JAE GEUN
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IN.OUT 1 3
A B C D E F G H I J

TUNER

6 TU_+5.0V +3.3V
L107
+5V

MLB-201209-0120P-N2

GND2
TP129
+3.3V
IC102

R115
4.7K

OPT
LGIT

L112

KIA78R05F OPT
C104-*1 C124 C126 C129
0.1uF 4.7uF 100uF

TP124
0.1uF
6 16V 10V 16V
CTR 50V 0 RF_SWITCH
1 LGIT 3:T24
C104
RF_SWITCH TU_+5.0V
RF-GAIN_SW R113

TP125

R101
2 2200pF

100
16V C134 50V 0 GAIN_SWITCH
B0[+5V] 1 2 3 4 5
3 22uF 0.1uF GAIN_SWITCH 3:T24 TU_+5.0V
C275 50V TU101 R112 L108

VIN

VC

VOUT

NC

GND1
VTU R280 0 LGIT
4 LGIT VA1G5BF8005 C106 MLB-201209-0120P-N2
LGIT

TP132
RF_AGC 2200pF L106
R281 0 LGIT
5 50V +12V

TP113
LGIT TP142

B1[+5V] RF_SW C125 C130


6 1 TP126 C127

TP114
C116 C118 C120 IC101 0.1uF 4.7uF 100uF
TU102 NC_1 GAIN_SW AS7809DTRE1 TP122
16V 16V
7 2 10V
0.01uF 22uF 0.1uF L101
TDYR-H071F SIF BB OPT
D2.5V TP137 MLB-201209-0120P-N2
8 3 INPUT OUTPUT
Place close to Pin 1 3
VIDEO_OUT B1 TP118
9 4 2
+3.3V
5 NC_2 AFT
L102
TP115

0 GND
10 5 TP127
C277
L104 C276 C103 C108 C111 C113 C115
NC_3 SIF R103 C112
TP106

C110 TP135 0.1uF 100uF C101 C102 0.33uF 0.1uF 47uF 0.1uF 0.01uF
11 6 0.1uF 16V 16V 0.1uF 100uF
22uF 16V 50V 16V 50V 50V
AIF R282 0 VIDEO C114 C119 50V 16V
12 7 TP128 0.1uF
22uF
B2[2.5V] LGIT B2
TP109

TP136
13 8
D1.2V A1[RD]

TP147
B3[3.3V] B3 C R125 330
TP110

14 9 A2[GN]
TP151
B4[1.2V] B4 L105
TP111

15 10 D101
TP117

TP139
SAM2333
RESET[SYRSTN] RESET 22 R104 C122
16 11 C121
TUNER_RESETb 3:T26
0.1uF
SDA SDA 22uF
TP102

22 R105 SAM2333 +3.3V


17 12 SDA0_3.3V 3:T26
TP140 D102
SCL SCL
TP103

22 R106
18 13 SCL0_3.3V R122
3:T26 A1[RD]
1K

TP144
RSEORF RSEORF
TP112

C TP152
19 14 A2[GN]
SBYTE SBYTE
TP107

20 15 22 R107
TU_SYNC 3:T27
SPBVAL SPBVAL TU_+5.0V
TP108

TP133
0
21 16
SRDT SRDT R111
TP104

22 17 22 R108
TU_SDATA 3:T27
SRCK SRCK
4
TP105

23 18 22 R109 L109
TU_SCLK

TP143
3:T27
24 C272 C273
22pF 22pF 19
50V 50V

R120

R124
SHIELD SHIELD

12K

470
LGIT LGIT C128

TP150
R123 0.01uF
TU_+5.0V 0

TP145
TU_SIF 3:T25

TP141
OPT
C123 E
0.01uF
OPT

L103 2SA1530A-T112-1R
B Q101
TP123

R121
C
10K
C117
IC103 0.1uF
TP146
OPT
R110
4.7K

FMS6400CS1X
TP116

OPT
C105 R118
FI-C3216-103KJT

TP120

YIN YOUT 56 TP138


1 8

10uF 16V
R119
R102

OPT

OPT

ASEL VCC TU_CVBS_IN 3:T25


L210
OPT

56

2 7
OPT
82

OPT
TP121

0
3
TP130

GND CVOUT
C274 3 6
GND
91pF R117
TP134
TP131

50V OPT CIN COUT


4 5
TP119

OPT
C107 R116
0.1uF 0
16V

OPT

10uF C109

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 08.11.14
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR HA JAE MIN
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TNER 2 3
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP

29

28

97
97
27 TU_SCLK 2:C4
96 96
TU_SDATA 2:C4
95 95
TU_SYNC 2:C4
94 94

26 93
92
93
92
SCL0_3.3V
SDA0_3.3V
2:C4
2:C4
91 91
90 90
TUNER_RESETb 2:C4
89 89
TU_CVBS_IN 2:D3
25 88
87
88
87
86 86
TU_SIF 2:E4
85 85
84 84

24 83
82
83
82
GAIN_SWITCH
RF_SWITCH
2:C5
2:C6
81 81
80 80
79 79
COMP1_L_IN 1:E3
23 78
77
78
77
COMP1_R_IN
COMP1_DET
1:E3
1:E4
76 76
75 75
74 COMP1_Y_IN 1:E4
74
COMP1_Pb_IN 1:E4
22 73
72
73
72
COMP1_Pr_IN 1:E3

71 71
70 70
69 COMP2_L_IN 1:A3
69
COMP2_R_IN 1:A3
21 68
67
68
67
COMP2_DET 1:A4

66 66
65 COMP2_Y_IN 1:A4
65
64 COMP2_Pb_IN 1:A4
64
COMP2_Pr_IN 1:A3
20 63
62
63
62
61 61
AV1_L_IN 1:E2
60 60
59 AV1_R_IN 1:E1
59

19 58
57
58
57
AV1_CVBS_IN
AV1_CVBS_DET
1:E3
1:E2
56 56
55 55
54 54
SIDE_CVBS_IN 1:A2
18 53
52
53
52
SIDE_CVBS_DET 1:A2

51 51
50 SIDE_L_IN 1:A2
50
SIDE_R_IN 1:A1
49 49
D1.2V
17 48
47
48
47
R114 0

46 46 DDC_SCL 1:I4
45 45 DDC_SDA 1:I4 +5V_ST
44 44

16 43
42
43
42
41 41
40 40
39 39 EDID_WP 1:I4
15 38
37
38
37
DSUB_DET 1:J3

36 36
35 DSUB_R 1:G3
35
34 34
DSUB_G 1:G3
14 33
32
33
32
DSUB_B 1:G3
31 31
30 30
29 29
RGB_HSYNC 1:F4
13 28
27
28
27
RGB_VSYNC 1:F4

26 26
25 25
PC_L_IN 1:H2
24 24 +3.3V
PC_R_IN 1:H2
12 23
22
23
22
21 21
20 20
19 19
SPDIF_OUT 1:A7;1:G4
11 18
17
18
17
RS232C_RxD 1:H6
16 16
RS232C_TxD 1:H6
15 15 IR 1:J6 D2.5V
14 14

10 13
12
13
12
+12V
11 11
10 10
9 9

9 8
7
8
7
6 6
5 5
4 MAYBE WILL BE ADDED.
4

8 3
2
3
2
1 1

7 GF05C-96S
P203

5 JACK INTERFACE SIGNAL

2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 08.11.14
1 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR YUN GWI SEOB
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BOARD INTERFACE 3 3

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