03 Comb - Seqlogic 4up PDF

3 Representations of Logic Functions
Combinational & n Recall that any complex logic function can be

expressed in 3 ways: Truth Table, Boolean
Sequential Logic Expression, Schematics
n Only Truth Table representation is unique
ENGG1203
n We can convert representation from one form
2nd Semester, 2012/13
to the other Truth Table
Dr. Kenneth Wong

Department of Electrical and
Electronic Engineering
Boolean
Schematics
http://www.eee.hku.hk/~engg1203
Expression
2nd semester, 2012/13 ENGG1203 - K. Wong 2
Minimization by Karnaugh Maps

n What is a Karnaugh map?
Karnaugh map (K map) is a graphical tool used to simplify a logic
equation or to convert a truth table to its corresponding logic circuit
With a simple and orderly process, the resulting logic expression will be
in its simplest SOP form !!!
n K map format:
3 Variable K map: A\BC 00 01 11 10
0
1
A grid of squares
SIMPLIFYING LOGIC Each square represents one product term
eg: top-left represents A B C , bottom-right represents A B C
CIRCUITS The variables are ordered according to Gray code
only one variable changes between adjacent squares
Squares on edges are considered adjacent to squares on opposite edges
2nd semester, 2012/13 ENGG1203 - K. Wong 3 2nd semester, 2012/13 ENGG1203 - K. Wong 4
4 Variable K map
AB\CD
00
00 01 11 10
Filling out a Karnaugh Map
n Given an initial (unsimplified) logic Boolean expression
01 ? ?? n Write the expression in SOP form
11 n For each product term, write a 1 in all the squares which are included in the
term, 0 elsewhere
10 All variables present in the product term: one square
One variable missing: two adjacent squares
The square marked ? represents A B C D Two terms missing: 4 adjacent squares
A\BC 00 01 11 10
The square marked ?? represents A B C D nExample 1:
0 0 0 1 0
Note that they differ in only the C variable. X = ABC + ABC + ABC + ABC
1 0 1 1 1
Karnaugh maps become clumsier to use with more than 4 variables
A\BC 00 01 11 10
General procedure for using K map: n Example 2:
0 1 0 0 0
1. Fill out the K map for a given Boolean expression X = BC + ABC + AC 1 1 1 1 1
2. Simplify the expression by properly combining those squares in the
K map that contains 1s. This process is called looping A\BC 00 01 11 10
n Example 3: 0 1 1 0 1
X = B + ABC + A 1 1 1 1 1
Looping More examples on looping of two

n Minimization is done by spotting patterns of 1's and 0's
n Pairs of adjacent 1's (Looping groups of two)
remember that adjacent squares differ by only one variable
hence the combination of 2 adjacent squares has the form P( A + A )
this can be simplified (from before) to just P
Example 1 (continue) X = ABC + ABC + ABC + ABC
A\BC 00 01 11 10
0 0 0 1 0
1 0 1 1 1
-- the adjacent squares A B C and ABC differ only in A

-- hence they can be combined into just BC, indicated by the blue loop
-- looping can also be done by grouping ABC and A B C to give AC,
as indicated by the red loop
-- furthermore, looping can also be done by grouping A B C and ABC
to give AB, as indicated by the yellow loop
-- The simplified Boolean equation is one that sums all the terms
corresponding to each of the group:
X = AC + BC + AB
Looping group of four (quads) Looping group of eight (Octets)
n A K map may contain a group of four 1s that are adjacent to each other. n A group of eight 1s that are adjacent to one another is called an octet
This group is called quad n Looping an octet of adjacent 1s eliminates the three variables that
n Looping a quad of adjacent 1s eliminates the two variables that appear in both complemented and uncomplemented form
appear in both complemented and uncomplemented form n Examples:
n Examples:
Complete Simplification Process n Examples:

1. Construct the K map and place 1s and 0s in the squares according to AB\CD 00 01 11 10 AB\CD 00 01 11 10
the truth table.
00 0 1 0 0 00 0 0 0 0
2. Group the isolated 1s which are not adjacent to any other 1s (single
loops). 01 0 1 0 0 01 1 0 0 1
3. Group any pair which contains a 1 adjacent to only one other 1 (double 11 1 1 1 1 11 1 0 1 1
loops).
10 0 1 0 0 10 0 0 0 0
4. Group any octet even if it contains one or more 1s that have already
been grouped.
5. Group any quad that contains one or more 1s that have not already Step2. Isolated 1: None Step2. Isolated 1: None
been grouped, making sure to use the minimum number of groups. Step3. Adjacent to only one 1: None Step3. Adjacent to only one 1: red loop
Step4. Octet: None Step4. Octet: None
6. Group any pairs necessary to include any 1s that have not yet been Step5. Quad: Blue and red loops Step5. Quad: Green loops
grouped, making sure to use the minimum number of groups. Step6. All 1s have been looped => skip this step Step6. All 1s have been looped => skip this step
7. Form the OR sum of all the terms generated by each group.
AB + C D BD + ABC
Dont Care Conditions Quick Quiz
n In certain cases, some of the input conditions may never occur or it AB\CD 00 01 11 10 AB\CD 00 01 11 10
may not matter what happens even if they do
00 0 0 0 1 00 0 1 0 0
In such cases we fill in the K map with and X
meaning don't care 01 0 1 1 0 01 0 1 1 1
When minimizing an X is like a "joker" 11 0 1 1 0 11 1 1 X 0
X can be 0 or 1 - whatever helps best with the minimization 10 0 0 X 0
10 0 0 X X
E.g.,: ABC will never occur or we dont care what is the output
even if it occur
A\BC 00 01 11 10 1 BCD + BD 1 ABC + ACD + ACD + ABC
0 0 0 1 X
2 BCD + BD 2 ABC + ACD + ABC + BD
1 0 0 1 1
3 ABCD + BD 3 ABC + ACD + ABC
simplifies to B if X is assumed 1
If we assume X = 0, the output becomes AB+BC, which is more 4 ABCD + BD 4 ABC + ACD + ACD + ABC
complicated
Binary Numbers Decimal Binary

n Represents numbers in base 2 0 0
1 1
n E.g.: 2310 = 101112 2 10
3 11
n Almost all computers today
4 100
utilize binary representation of
5 101
numbers internally 6 110
7 111
Putting It Together
8 1000
FROM SINGLE-BIT TO MULTI- 9

10
1001
1010
BIT ADDER 11 1011
12 1100
From Binary to Decimal Example
n Note that the value of a binary number is n Convert the binary number 11001 into
given by: decimal representation
2i bi 25 24 23 22 21 20
i= 0
where bi is the digital at position i, starting 1 1 0 0 1 = 1 2 4 + 1 2 3 + 0 2 2 + 0 21 + 1 2 0

counting from zero from the far right. = 24 + 23 + 20
= 16 + 8 + 1
n Converting
from binary to decimal can be
done by adding the power-of-2 where there is = 25
a1

Value Binary Bitstring (8-

bit)
From Decimal to Binary Positive Integers 0
1
0
1
00000000
00000001
n Can be found using short n Non-negative binary numbers 2 10 00000010

(0, 1, 2, 3, ) can be
division: 2 19 1 represented naturally with
3 11 00000011
4 100 00000100
Successively divide the 2 9 1 bitstrings that corresponds to
dividend by 2 their binary representation 5 101 00000101
2 4 0 6 110 00000110
The remainders form the n Represents equally spaced 7 111 00000111
resulting binary number when 2 2 0 integers on the number line
8 1000 00001000
counted from the bottom 1 n Sometimes called unsigned 9 1001 00001001
integer
n Example: Converts 1910 into 10 1010 00001010
binary 1910 = 100112

11 1011 00001011
0 1 2 3 4 5 6 7 8
Positive Integers Positive Integers Addition
n With a bitstring of width n, the following n Two +ve integers can be added similar to the
properties hold: way decimal numbers are added in long
min value : 0 addition
max value : 2 n 1
n The value of a bistring {bn1 bn2b0 }can be 2 3 1 0 1 1 1
calculated as: + 1 1 9 + 1 1 0
1 0
1 1
1 1
n1
2i bi 4 2 1 0 1 0 1 0

i= 0
n E.g. The value of
101112 = 2 4 + 2 2 + 21 + 2 0 How do we implement binary addition in
= 16 + 4 + 2 + 1 hardware?
= 23

Half Adder Full Adder
n Basic addition of two 1-bit values n The subsequent bits need to be slightly
n Generate a carry out to the next bit if the smarter than a half adder
result is 2 There may be carry input from the bit to the right
a b co s n A 3-input function (a, b, ci)

0 0 0 0 s= ab ci a b co s s = a b ci
0 1 0 1 0 0 0 0 0
1 0 0 1 co = a b 0 0 1 0 1 co = a b + ci ( a + b)
1 1 1 0 0 1 0 0 1
0 1 1 1 0
1 0 1 1 1 1 0 0 0 1 1 0 1 1 1
+ 1 1 0
1 0
1 1
1 1 1 0 1 1 0 + 1 1 0
1 0
1 1
1 1
1 1 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0
1 1 1 1 1
Multi-bit Adder Multi-bit Adder
n Both HA and FA can add 1 bit only a<3> b<3> a<2> b<2> a<1> b<1> a<0> b<0>
A half-adder is simply a full-adder with the carry input
tied to 0 a b a b a b a b
n To make a multi-bit adder, we can connect the Carry co FA

ci co FA
ci co FA
ci co FA
ci 0
out
carry output from one FA to the carry input of s s s s
another one
s<3> s<2> s<1> s<0>
n Start from least significant bit (usually rightmost
bit) and propagate the carry to the left (the most n Note: the <> notation is a shorthand to denote a bit
significant bit) within a multi-bit signal.
Other common notation: a(0), a[0], a0, etc
1 0 1 1 1
n Mimic the action of a n Engineer sometimes call multi-bit signal a bus, or a
+ 1 1 0
1 0
1 1
1 1
long addition signal bus.
1 0 1 0 1 0
Short Summary
n Truth Table, Schematics and Boolean Expression
are 3 different ways to represent the same
functionality
Conversion between the 3 is relatively straight-forward
TT is the only representation that is unique
n Logic circuits can be minimized/manipulated by
Boolean algebra
May use TTs for proofs as they are unique
K map is a handy graphical ways to obtain minimized
logic functions
n Combinational techniques allow us to build large
circuits
Multi-bit Adder from single-bit HA and FA
Administrivia Combinational vs Sequential
n Homework 1 has been posted on Course website +
Moodle today
Due on Feb 22, 2013
n Individual homework Sequential
Combinational

You may discuss the basic idea of the homework questions
with your classmates, but you must complete the questions
on your own and submit your own work.
n Make sure you finalize your submission in the Moodle
system. n In combinational logic, the output is a pure
Make changes to your draft as many time as you want function of the present input only, i.e. no
Finalize when it is ready
Will not cater I uploaded the wrong file requests
memory effect
n Remember, plagiarism is a serious act with heavy n In sequential logic, the output depends not
consequences only on the present input, but also on the
history of the input, i.e. memory effect
2nd semester, 2012/13 ENGG1203 - K. Wong 29 1st semester, 2012 ENGG1015 - H. So 30
Sequential Logic Why Sequential Circuit?

n Sequential logic circuits are circuits that Introduces the notion of time in the circuit
contains state elements n Provide order to the operation of the circuit
n State elements are circuits that remember its E.g. part of a circuit must not start computing until the
inputs are ready
input
Allow a circuit to have memory of its past
n Coordinate different parts of circuit to operate on
the correct set of data
n All state elements of a circuit collectively store E.g. A circuit that computes the final grade should take
input (homework, exam grades, etc) of the same
the current state of the circuit student
n The output of the circuit depends on both n Recall previous values
Current Input E.g. Echo cancellation by subtracting previous output
State (memory) of circuit sound wave 1 ms ago from input signals
State Elements Flip-Flops
n A state element (circuit component) stores a n An edge-trigger flip-flop (FF) is a circuit
1 or 0 permanently regardless of the that changes it output only when the value
changes in input of its clock input changes
0 1 = Rising Edge
n Simple example: 1 0 = Falling Edge
If x is 0, then y is 1, then x is 0,
x y n For simplicity, we will only use rising edge
If x is 1, then y is 0, then x is 1, triggered FF in this class
The value stored inside the circuit will not change
n An edge-triggering signal pin is usually
clk
To be useful: Need a way to change the state
denoted by a wedge in the schematic
symbol.
D Flip-Flop Ex Delay Line/Shift Register

D
D Q
clk Q b a
a D Q D Q c
clk
clk clk
b
time
c
clk
n A D-FF has 1 data input port D, and a single clk
output port Q, plus
Clock input n The simplest (but useful) way to use DFFs is
Optional: reset (clear) input to form a delay line.
Optional: enable n A delay line with n DFFs delays the input
n At the rising edge of clock signal, the value at signal by n clock cycles
input D is captured. n Note: In hardware designs, all parts of the
Captured data is output at Q circuit operate simultaneously
Quick Quiz Quick Quiz Explained
y y
x D Q x D Q
x
clk clk
clk clk
n Which of the following best describes the n The value at x contains the value of x from previous
function of the circuit above? cycle

1 Always output the inverse of x n y = x x" = TRUE iff exactly one of the two is
TRUE
Always output x in previous cycle
2 x=0, x=1
Output 1 when x changes from 1 to 0
3 x=1, x=0
Output 1 when x stays 0 for 2 cycles
4
n y is HIGH for 1 cycle if the value of x changes from its
value in previous cycle
n Note the DFF has given us memory of x from
previous cycle
y
Timing x D Q
clk
x
D Q
clk
Example Implement Toggle FF
n A toggle flip-flop toggles the output at rising
clk
clock edge when the toggle signal (T) is
HIGH.
y x is a delayed Otherwise, the output remains unchanged.
version of x
x T
T Q
x Q clk
instantly y = x x"
clk clk
time
cycle 0 1 2 3 4
x 0 1 1 0 0 Can we use a DFF to implement a TFF?

y 0 1 0 1 0
Ex: Implementing TFF with DFF Ex: Implement TFF using DFF
n 1st step: express the function of TFF in a table n 2nd step: Use a DFF to implement the function
similar to a truth table of storing next_Q into Q after the next clock
next_Q denotes the value that should be output at edge
Q after the next clock edge
T Q next_Q
Current Next Q
0 0 0 cycle cycle next_Q
D Q Q
0 1 1 T
clk
1 0 1 T
clk
1 1 0
Q
Q next_Q clk
T
Register d3
D Q
q3 Accumulator
n A register is a parallel clk n An accumulator accumulates the input values (x)
composition of D-flip-flops. into the internally stored sum on every clock
An n-bit register contains n edge.
d2 q2
D Q
DFFs X x0 x1 x2
clk
n A register stores multi-bit sum 0 x0 x0 + x1 x0 + x1 + x2
values d1 q1
clk
D Q
n For simplicity, a single bus clk
connection to a DFF NOTE
symbol is often used d0 q0 n Instead of simple 0 and 1, the value in the
D Q
clk signal X and S are used
clk clk
clk n The initial value of S must be reset to the value
zero for correct behavior
Synchronous vs Asynchronous
Accumulator
Sequential Circuit
current_sum next_sum
A
S sum This synchronous

x B clk Course
Sequential
Combinational

clk asynchronous

n It can be constructed using an adder with a

register: n In synchronous sequential circuits, all state
Step 1: the next value of sum after the clock edge elements are updated synchronously
should be the sum of input x and the current_sum
Step 2: At clock edge, we store the value of next_sum according to a single clock signal
using a register
n In asynchronous sequential circuits, state
Step 3: the newly stored value becomes the
current_sum after the clock edge elements may be updated with multiple
clocks, no clock signal, or any other schemes.
Synchronous Sequential Circuits Clock Signal

n A synchronous sequential circuit contains exactly 1 n A clock signal is particularly important signal in a
clock signal synchronous sequential circuit
It controls the action of all DFFs
n All state elements are connected to the same clock
signal n A clock signal toggles between 0 and 1
the state of the entire circuit is updated at the same time periodically
n Common form of synchronous sequential circuits: n The frequency of the toggling determines the
maximum speed of the circuit
E.g.: in the accumulator example earlier, the output S
cannot change faster than the clock frequency
input Comb Comb Comb Comb output x0 x1 x2
X
Logic Logic Logic Logic 1
S 0 x0 x0 + x1 x0 + x1 + x2 = clock frequency
clk clk clk clock period
clk
clk
e.g. Intel CPU runs at 3 GHz,
Mobile phone processors at 1 GHz
clock period Lab FPGA board at 50 MHz
Problem: Ticket Gate at MTR
Card Valid Gate Close Passenger Passed Gate Open
Card Valid Gate Open
WAIT_CARD WAIT_PASS
reset
Passenger Passed Gate Close
n The gate should only open after a valid

FINITE STATE MACHINE Octopus card is scanned.
n It should close the gate after a person has
passed through the gate.
FSM Overview Defining Finite State Machines

n Finite State Machine (FSM) is an abstraction of n Each FSM defines:
computation Finite number of states that the machine can be in
Can be used to model many computing tasks, both in The conditions under which it will transition from
software and in hardware
one state to another
n Very useful abstraction to help design sequential
circuits n At any moment in time, an FSM can only exist
It is systematic, and can be analyzed mathematically in 1 of the defined states
n Used to describe very complex behavior of n The output of an FSM depends on the state
circuits and systems that the FSM
Decision making
Optionally depend on the input to the FSM
Network communication
Card Valid Gate Close Passenger Passed Gate Open Card Valid Gate Close Passenger Passed Gate Open
Microprocessor control Card Valid Gate Open Card Valid Gate Open
WAIT_CARD WAIT_PASS WAIT_CARD WAIT_PASS
reset reset
Passenger Passed Gate Close Passenger Passed Gate Close
State Transition Diagram Quick Quiz
n A graphical tool to describe reset
n Which of the following is/ reset
the behavior of an FSM are possible sequence(s)
n Represent states as blocks of states that the FSM
S0 may go through? S0
Labeled: name of the state
n Represent transitions as S1 S1
directed edge 1
S0 S1 S3 S2 S0
Direction of an edge S0 S1 S1 S2 S2 S0
2
represents the direction of S3 S3
state transition S0 S0 S1 S1 S3 S3 S3
3
S2 S2 S0 S0 S0 S0
4
n All possible states & S2 S2
transitions are included
State Transitions Ex: Ticket Gate at MTR

condition / output Card Valid Gate Open
S0 S1
WAIT_CARD WAIT_PASS
reset
n Each state transition is labeled with:
1. Condition that the transition should take place
2. Output of the FSM during the transition
n The gate should only open after a valid
n There should only be 1 active transition at Octopus card is scanned.
any one time
n It should close the gate after a person has
The input conditions of all transitions in a FSM
passed through the gate.
should be mutually exclusive
FSM in Hardware Ticket Gate Control (1)
n FSM can be efficiently implemented in Card Valid Gate Close
Card Valid Gate Open
Passenger Passed Gate Open
hardware using synchronous sequential WAIT_CARD WAIT_PASS
circuits reset
FSM states can be implemented by registers

Step 1: Define the input/output signals
State transition conditions can be implemented by
combinational function on input signals and the n We use the following signals:
states Type Name Description
FSM outputs are simply output signals of the input valid 1 if a valid Octopus card is presented,
circuit 0 otherwise
input passed 1 if a passenger has completely
n Transition condition is checked on every clock passed through the gate, 0 otherwise
edge output motor 1 close the ticket gate by turning on a
motor , 0 otherwise

Ticket Gate Control (2) Ticket Gate Control (3a)

Card Valid Gate Close Passenger Passed Gate Open Card Valid Gate Close Passenger Passed Gate Open
Card Valid Gate Open Card Valid Gate Open
WAIT_CARD WAIT_PASS WAIT_CARD WAIT_PASS
reset reset
Passenger Passed Gate Close Passenger Passed Gate Close
Step 2: Determine how the FSM states will be Step 3: Implement the state transition logic
represented in hardware n At each cycle, determine what is the next state
this FSM should be in the next cycle
n 2 FSM states 1 DFF needed Determine which transition is active by checking all the
transition conditions
n Encode the state as follows:
0 WAIT_CARD state n The next state logic is a combinational function of
the current state and the input signals
1 WAIT_PASS state
The input to the state register
Can be found using a truth table
Ticket Gate Control (3b) Ticket Gate Control (4a)
Card Valid Gate Open Card Valid Gate Open
WAIT_CARD WAIT_PASS
WAIT_CARD WAIT_PASS
reset
reset Passenger Passed Gate Close
Passenger Passed Gate Close ns = s valid + s passed Step 4: Determine the output logic
s valid passed ns
n Can be performed similar to the way the next
0 0 0 0
0 0 1 0
state logic is obtained
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Ticket Gate Control (4b) Ticket Gate Control (5)

Card Valid Gate Open Step 4: Implement the circuit
WAIT_CARD WAIT_PASS s
Next State ns s
reset state output
input Logic register Output
Passenger Passed Gate Close motor = s valid + s passed
Logic
s valid passed ns motor clk
0 0 0 0 1
0 0 1 0 1 n Next state (ns) is a combinational function on
0 1 0 1 0 current state (s) and current input
0 1 1 1 0 n After clock edge, ns becomes the current state
1 0 0 1 0 (s) in the next cycle connect to state register
1 0 1 0 1 n Output depends on current state
1 1 0 1 0
n Output may depend on input as well
1 1 1 0 1
Summary
n In sequential circuits, output depends on both the
current input and the state of the circuit
Output of combinational circuit depends only on the
current input
n D-Flip-Flops are the most common state element
to hold states in a circuit
The output value of and edge-triggered DFF only
changes at positive clock edge.
A multi-bit DFF is sometimes referred as a register
n State machine is an important abstraction for
computation
Straight forward implementation as synchronous
sequential logic
2nd semester, 2012/13 ENGG1203 - K. Wong 65

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3 Representations of Logic Functions

Combinational & n Recall that any complex logic function can be

Dr. Kenneth Wong

Minimization by Karnaugh Maps

Looping More examples on looping of two

-- the adjacent squares A B C and ABC differ only in A

Complete Simplification Process n Examples:

Binary Numbers Decimal Binary

FROM SINGLE-BIT TO MULTI- 9

where bi is the digital at position i, starting 1 1 0 0 1 = 1 2 4 + 1 2 3 + 0 2 2 + 0 21 + 1 2 0

Value Binary Bitstring (8-

From Decimal to Binary Positive Integers 0

n Can be found using short n Non-negative binary numbers 2 10 00000010

binary 1910 = 100112

a b co s n A 3-input function (a, b, ci)

n To make a multi-bit adder, we can connect the Carry co FA

Sequential Logic Why Sequential Circuit?

D Flip-Flop Ex Delay Line/Shift Register

n It can be constructed using an adder with a

Synchronous Sequential Circuits Clock Signal

n The gate should only open after a valid

FSM Overview Defining Finite State Machines

WAIT_CARD WAIT_PASS WAIT_CARD WAIT_PASS

State Transitions Ex: Ticket Gate at MTR

hardware using synchronous sequential WAIT_CARD WAIT_PASS

FSM states can be implemented by registers

Ticket Gate Control (2) Ticket Gate Control (3a)

WAIT_CARD WAIT_PASS WAIT_CARD WAIT_PASS

Ticket Gate Control (4b) Ticket Gate Control (5)

2nd semester, 2012/13 ENGG1203 - K. Wong 65

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