!

l
i t

i
1
,

!
R'Iassachusetts Institute of Technoldgy
InstrumentationLaboratory .
Cambridge, hlassachusetts

, i

I
TO: AGC4 Distribution . {
I
FROM: Hugh Blair-Smith $
. .
j
DATE: September 30, 1965, Revised July 1,' 1 9 6 6
SUBJECT: AGC4 MEMO # 9 - Block I1 Instructions

e
i.
..
'
i
I
I

.;I

i
4 &w

C
.. .

T A B LOEF COSTEKTS

Introduction . . . . . . . . . . . . . . . . . . . . . ... . . . . , . . . . . . . . . . 2

;\Iemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, 3

Basic Instructions . . . . . . . . . . . . . . . . . . . . , , . . . . . . . . . . . . 3

Extracode Instructions . . . . . . . . . . . . . . . . . . . . ,. . . . . . . . . . 11

Implied-Address Codes . . . .. . . . . . . . . . . . * , , . . . . . . . . . ... . 15

Unprogrammed Sequences . . . . . . . . . . . . . . . . . . . , .'. . . . . . . . 21

A d d r e s s Constant .Formats . , . . . . . . . . . . . . . . . . . . ,. . . . . . . .
. . 25

Control Pulse Definitions . :. . . . .. . . . . . . . . . . . . . . . . . . . . . . 27

Condensed List of 'Programm.able Instructions . . . . . . . . . . . . . . 34

,Pulse Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.

1
 Introduction
T h i s document supercedes all revisions of and appendices to
ACC4 Nemo /# 8 , "Block I1 Instructions, Revised". The format has
been changed to include more information for YUL-language program-
m e r s a n d to include the engineering details formerly re1egate.d to
appendices. A new descriptive section on unprogrammed sequences
has been added.
Some confusion has arisen about the nature of channel numbers
or addresses. Channel addresses should be used just like memory
addresses in programming, that is, regarding the channels as a third
category of memory, distinct from E and F. The fact that the numbers
used a s channel addresses coincide 'with s o m e of the numbers' used as
m e m o r y a d d r e s s e s shoul-d cause no eonfusion, because the addresses in
In/Out, instructions a r e always channel addresses,' and the addresses in'
' other instructions a r e alwaysmemoryaddresses, I n fact, thecoinci-
dence is put to good use: the L r e g i s t e r is accessible both at m e m o r y
a d d r e s s 0001 and at channel address 0 1.
In YUL'language, symbols may be equated to channel addresses
as well'as memory addresses. The only distinction made by the
a s s e m b l e r is that addresses of In/Out instructions have a theoretical
maximum of 777.

2
 . .
. . .

Memory
Block I1 differs significantly I in r e g i s t e r a n d memory
layoutand in addressing. The L P s been rena-med L because-
it is a lower accumulator in every sense. m e IN and OUT r e g i s t e r s no
longer
addresses
have i n memory, $?-bit
channel
with
a d d rseven
e s s e s b y the 10). Channel
assignments a r e given 2 5 4 , Revision A
(Sept. 7 , 1965). of a d d r e s s e s .
The erasable banks uselocaladdresses '14 7 7 7 . Thefixedbanksuse
localaddresses 2000-3777. Figure 3 explthebank-switchingand
editing registers.

Basic Instructions
Figure 4 shows therelationships a m heoperationcodes, with
alternatespellinginbrackets.Subscriptsrunningtimes,in hECT
-
EXTEND'tirne of 1' MCT is not includedintimes.
13.
..

Code 00. I: TC K Transfer Co 1 MCT

K # 3,4,6 .Set c(Q) = TC I + 1;

Take next
instruction
proceed
from
there.
Remarks:Alternatespelling is TCR, for Transfer
!"I
Control setting up Return. r.:
 e

. . ARRANGEMEKT OF ADDRESSES .. .

ICTAL PSEUDO- REGISTER

PDRESS N A ME R E MARKS TYPE
"- " -.
1
uouoo A . .

00001 L channel (also 01)

00002 Q channel (also 02)

00003 EB ERegister
r a s a b l e Bank Flip-flop

00004 FBRegister Bank Fixed registers

00005 2'
00006 BB Both Bank Registers '

00007 " Zeros

00010 ARUPT . x R U P T = Storage
for x
oooli ' . Inte,rrupt;
during
LRUPT
00012 QRUPT .' ZRUPT & BRUPT stored
(spare) auto'maticauy. ' '

ro13
00014. ' (spare)
00015 ZRUPT 2040 words
of Erasable
00016 BBRUPT
. .J
00017 BRUPT (RIP)
00020 CYR Cycle Right 1 Bit

00021 SR Shift Right 1 Bit

00022 'CYL Cycle Left 1 Bit

00023 EDOP (Polish)Edit Opcode
. .
00024-00057 Counters
00060-01377 Unswitched E r a s a b l e
01400-03777 5 E r a s a b l e Banks 6) 256 words (See F i g . 2)

rooo -up
Fixed (See Fig. 2) '.'
Fixed

4
 a .

Fixed and k:rasai-;le Bank-f;\vitshing

(Fig. 2)
Octal Pseudo- Memory S-R.eg.
Erasable
Ex-
Fixed
Fixed
Address TY PP Bank Reg. Bank
Reg.
tension
bit Value
(channel 7 1,
00000-01377 (Note 1) X : xx X 0000-1377
00000-00377 (Note 1) 0 - xx X 1400-1777
00400-00777 IJnswitched E 1 , xx X 1400-1777
01000-01377 Unswitched E 2 xx X 1400-1777
, .
01400-01777 Switched E 3 . . xx . .x 1400-1777
02000-02377 Switched' E 4 . xx X. . '1400-1777
02400-02777 Switrhed F 5 xx X 1400-1777
03000-03377 Switched E 6 xx X 1400-1777
03400-03777 Switched E 7 xx x. 1400-1777
-fixed Fixed
04000-07777 X xx X 4000-7777
10000-11777 fixed Common X 00 X 2000-3777'
12000-13777 Common fixed .. . x 01 x 2000-3777
04,000-05777 Fixed-fixed X. : 02 X 2000-3777
06000-'07777 Fixed -fixed X ' . 03 X 2000-3777
20000-21777 Common fixed X 04 X .2000-3777
22000-2'3777 Common fixed X 05 X 2000-3777
. .
-- and, s o on through:
64000-65777 fixed
Common X . .26 X 2000-3777
66000-67777 fixed
Common X :27 ~ X 2000-3777.
70000-71777 -bank%per 0 X 30 , I
0 2000-3777
72000-73777 Super-bank 0 X 31 0 2000-3777
- - and so on through:
106000-107777 Super-bankO X 37 ' 0 2000-3777
110000-111777 Super-bankl X .30 1 2000-3777'
112000-113777 Super-bank 1 X 31 1 2000-3777
114000-115777 Super-bank 1 ' X 32 1 2000-3777
116000-117777 Super-bank 1 X 33 1 2000-3777 .

. (Note 1) Flip-flopcentralregisters,counters, and unswitchederasable.Central '

and s p e c i a l - p J r p o s e r e g i s t e r s w i l l be accessed as E-bank 0 only under exceptional

1.
circumstances.

5
 B A N K - S I Y I T C H I N G A N D E D I T I N GR E G I S T E R S

Register
Octal . Access to Bank-Switching
Same Address Circuits

0003 I 0 0 0 OIEE
A E100 0 0 0 O O O l

0004 FB

(Actual Circuits)
_. -

0006 BB

Chan. 07 FEB 1000 0 0 0 o o ~ x ~ o o5 To i q

.-

>
-
A bank number written into EB o r F B
_.
is automatically available ,at BB.
-
.-
0 - Information
written
into BB is auto-
matically available at EB and FB.
. _

~~---------

.. .
...
-
EDITING REGISTER TRANSFORMATIONS

(bit positions 1 15 14 13 12 i l IO 09 0 8 07 06 05 04 03 02 01
0020 CYR 01 15 14 13 12 11 10 09 08 07 06 05 04 03 02
002 1 SR 15 15 14 13 12 1 1 10 09 08 07 06 05 04 03 02
002 2 CYL 14 13 12 11 10 09 08 07 06 05 04 03 02 01 15
0023 EDOP, . 14 13 12 1110 09 08

Fig. 3

6
 . .
. *

. .
P
0
E

I I i
CD
0

u
r) xm- Xa
In
0 i; n z
r)

X F - r L ,
W
C

w cv
cn
0
u

m
0

hl Cr)
0 cn

P I -
(v

d
.
0 F4
N
a

0
0

7
 . .
t .

Code 00. I: T C K (Special

Cases of 'I' 1 MCT
0 K E 3,4,or 6 Set indicator specified by K;
Take next instruction 'from I + 1. ; ' '

Rc:marjcs: TC 3 = RELIKT (allow i

TC 4 = INHINT (inhibit interrupt),
I
TC 6 = EXTEND (set extracode switch).

The extracode switch causes the next instruction to be an extracode.

(1 Any
i
extracode except INDEX r e s e t s the switch. Interrupt is inhibited while the
switch is on. . . '
, .

Code 01. I: CCS K Count, Compare a 2 MCT

QCO c(A)
Set = DABS [b(K) J ;
Set c(K) '= b(K), editing if K i s 0020-0023.
'I
Take next instruction from I + 1 i f b(K) > + 0;
' f r o m I + 2 if b(K) = + 0;
f r o m I + 3 'if b(K) < - 0;
f.rom I + 4 if b(K) = 0. -
Remarks: The Diminished .Absolute Value of an integer x
is:
1x1 -1 if 1x1 > 1
DABS(x) =
"0
Code 01. I : TCF K Transfer
Control
Fixed
to 1 MCT
QC1-3
Takenext
instruction
from K andproceed
from
there.
R e m a r k s : QC n denotes Quarter Code n, where n is bits
l i and 11 of
instruction
the word. i
I
Code 02. I.: DAS K Double Add
Storage
to 3 MCT
QC 0 Set c(K, K+1) = b(A, L) + b(K, K+l),editing if K o r K +1
is 0020-0023;
If K # 0, Set c(L) = .+ 0 and s e t c(A) = net overflow;
Take next instruction fromI + 1.
R e m a r k s : If positive (negative) overflow resulted from the
double precision addition as a whole, the net overflow is +. 1( -l), otherwise
it is +.O. Notice that DAS A doubles the contents of the double precision ac-
cumulator--impliedaddresscode DDOUBL assembles as DAS A. Since the

i 8
 .

a
jl

hardware must operate or: the l o w - c r d e r operan'ds first, consider DAS a s the
operation code 20001, to xtiich' the add.r?Ss E; is added to f o r m the instruction.

Code 02. I: LXCIH I< Exchange .L and K 2 hiCT

QCl Set c(L) = t . ~ l ( K ) ;
Set c(K) = b(L), editing if K i s 0020-0023;
Take next instruction from I t 1.
Remarks: The prime indicates overflow correction.
Code 02. I: INCR K Increment 2 MCT
QC2 Set
c(K) = b(K) + 1, editing if K is 0020-0023;
Take next instruction from I + 1.
Remarks: INCR and two other codes, AUG and DIM,
a r e slightly modified counter-increment sequences. Accordingly, if one of this
group overflows when addressing a counter for which overflow during involuntary
incrementing is suppor;ed to cause an interrupt, .the interrupt w i l l happen. This
is true also for chain-reaction increments like T2,which is incremented after
an overflow of Ti. It should be noted that all these three instructions, unlike the
. increment sequences, always operate in ones complement, even when addressing
CDU counters. - .

Code 02. 1: ADS K . Addstorage

to 2 MCT
QC3 Set c(A), c(K) = b(K) + b(A), editing if K = 0020-0023;
Take next instruction from I + 1.
Code 03. I: CA K Clear
and Add 2 MCT
Set c(A) = b(K);
Set c(K) = b(K), editing if K is 0020-0023;
Take next instruction from I + 1.
Remarks: Alternate spelling CAF is permitted when referring
to fixed memory; alternate spelling CAE is permitted when referring to erasable
c memory.
Code 04. I: CS K Clear
Subtract
and . 2 MCT
Set c(A) = -b(K);
Set c(K) = b(K), editing if K is 0020-0023;.
' Take next instructionfrom I + 1.
 , .

Code 05. I:' IKDEX K Index Sext Instruction 2 MCT

Set c ( K ) .= b(K), e g l t i n g if E: is 00?0-0023;
E$!

#
Use [ b(K) + c( I+l& a s the next instruction.
Renlarks: The pr-. e indicates overflow
correction.
,

.-.

' Code 05. I: If\;DEX001 7 ij

"

Resume InterruptedProgram 2 MCT

QCO Set C(Z) = c(001j)
K = 0017 Use ~(0017) as thc&ext instruction.
-2: . -.

Remarks: The iGplied-address code RESUME a s s e m b l e s a s

INDEX 17.
Code 05. 'I: DXCH K
4
$:

61
--Double
.- " Exchange 3 MCT
. .

QCl Set c(A, L) = b(K, 'K+'l);

.~
Set c(K, K+1) = b(A,
. . L), editingif Kor K+l is 0020-0023;

Take next instruction from I + 1.

Remarks: The final c(L) w i l l be overflow -corrected. The
a s 52001 (see DAS, page 8).
operation code should be treated -.
"
"

.. . .

The implied-addrgss C O ~ ~ S ' D T CF

(CXCH FB) and DTCB
(DXCH Z) are recognized. .The idea is t h a t a DXCH, by changing both
" z and
one of the bank registers, can be a. "d-ouble-.precision transfer control" that
0 .
.-
can j u m p banks and leave a D. P. r e t u r n a d d r e s s i nA and L.
"

Code 05. I: .TS K Storage

Transfer
to 2 MCT
QC2 . Set c(K) = b(A), editing .if K is 0020-0023;
-
If + overflow i n b(A), s e t c(A) = -
_.
+ 1 and take.next instruction
from I + 2; . ..
"

If no overflow in b(A), take next instruction from I + 1.

Remarks: TS A . ~guarantees c(A) = b(A) but skips t o I + 2 on
overflow.Implied-addresscode = OVSK.

Code 05. I:, XCH ' K Exchange A and K 2 MCT

QC3 Set c(A) = b(K);
Set c(K) = b(A), editing if K is' 00.20-0023; ~ .

Take next instruction from I + 1.

Code 06. ' I: AD K ADD 2 MCT

Set c(K) = b(K), editing if K is 0020-0023;

Take next instruction from I + 1.
Remarks: The OVCTR of Block I h a s been dropped.
 j %$
' z.y
_- JI -.
;g
t
4

". ..
; $f
3,

I -

'Code 07. I: 1IASK !i l l a s k A by K ; .$ 2 MCT

' $-!
1
.
Set c(A) x b( 1)A c(K); . .*-
-.
;e *f.
:;
"

Take m x t instruction f r o m I + 1:
. &
~-
Hemarks: .A denotes Boolean A S D . Truth t ~ 5 1 efor each bit
-.- . .
I .A
.;
8

position of b(A) a n d c ( W : :. L,..$;

: "2
A K AAK a;
_..*"
:

- . . &I
f i
;

0 0 0 --
..
. .
4". L

0 . 1 0 J i
, . .:.I. . ,
1 0 .o & i

.. . _.
1 1 1
MASK very carefully omits t o edit an argument from0020-0023, i n order to "

aid
the
interpreter and other
software. "

' 5-
p; , '

, ..~.
Extracode Instructions ,
~.-
- ~."

"

Code 10. I: RE'AD KC Channel,-KC

Read 2 MCT
PC0 Set c(A) = c(KC), wh'ere KC is a n.. i=n l o u t channel;
,

..

Take next instruction from I t 1. -.: I $7

Remarks: Code 10 is broken il0W.n into seven peripheral codes

, .
.(pcO-pCG). Each uses a 9-bit address to reference _. an input/ output channel KC. .

The L r e g i s t e r is channel 01, to facilitate fancy. .-logicin an arithmetic register,

. --..
The Q r e g i s t e r is channel 02 , ' f o r the' same reason. .

. .
$ 2:

Code 10. I: WRITE KC Write Channel:. KC .

. I
2 MCT
.. .-.
PC1 c(KC)
Set = c(A); i 'f;

Take next instruction I + l.-..-z

from .- "

Code 10. I: RAND KC Read

and Mask 2 MCT
-.
-~
i
*
PC2 c(A)
Set = b(A) A c(KC); r -

Take next instruction from I t 1. - -

Remarks: A denotesBoolean AND ( s e e MASK).

Code 10. I: WAND Write and Mask

KC .. 2 MCT
PC3 Setc(KC), c(A) = b(A) A b(KC);
Take next instruction fromI t 1; .:._
"
I_

Code 10. I: "ROR .KC Read

Superimpose
and 2 MCT
PC4 c(A).=
Set b(A) v C(KC);

11
. . - .
* ' I

Take next instruction from I + 1.

0 R e m a r k s : v denotes Boolean Lqclusive O R . ' Truth table for
each bit position of b(A) and c(KC).:
A KC AVKC
0 0 0
0 1 1
. .1.. . 0 - 1
1 1 . 1

Code 1.0. J: WOR KC Write and Superimpose 2 MCT

PC5
c(KC),
Set c(A) = b(A) v b(KC);
Take next instruction from I + 1.

Code 10. I: RXOR KC Invert

andRead 2 MCT
. .
c(A)
PC6
Set = b(A) + c(KC);.
. Take next instruction from I + 1.
Remarks:'- denotes Boolean Exclusive OR. Truth table for
each bit position of b(A) and c(KC):
. A KC A-KC
. .
. 0. .O 0
0 1 . 1
. .
1 . o 1
/'

1 1 0

Code 10. EDRU PT 3 MCT

PC7 machine
(For
checkout
only)
Code 11. I: DV K Divide . 6 MCT
QCO , Set
c(A) = b(A, L) c(K); +
Set c(L) = remainder;
c Take
next
instruction from I + 1.
Remarks: The signs of the double-length dividend
i n A and L need not agree. The net sign of the dividend is the. sign
ofb ( A ) unlsss b(A) = - + 0, in which case it is the sign Of b(L). The
r e m a i n d e r bears the net dividend sign, and the quotient sign is deter-
mined strictly be the divisor and net dividend si.gns, DV does riot
e disturb c ( Q ) , and does not edit a n argument from 0020-0023 because
t h e r e isn't enough time.

12
 .
- 8
I
. .

'i
Code 11 I: B Z F K~i Branch
Zero to Fixed 1 o r 2 MCT
0 QC 1 - 3 If C(A) =
,.

-+ 0,' take
:
A

. ne$ 'instruction f r o m K andproceedfrom

there (1 M C T ) ; . .. .

Otherwise, take next instruc'tion from I + 1 ( 2 N C T ) .

..

..
t2

Code 12. I: MSU K- Subtract

Ilodular 2 MCT
QCO Set (:(A} = b ( A ) 8 b ( K ) ;
Setc(K) b ( W , editing if E; is 0020-0023;
Take next instruction from I 1. -
R e m a r k s : "denotes modular subtraction, which forms a
signed one's complement difference of two unsigned ,(modular, o r periodic)
two's complement inputs. The methodis to form the two's complement differ-
ence, to decrement it if it is negative, and to take the overflow-uncorrected
...

sum as the result.

Code 12. I: QXCH K Exchange Q arld K 2 MCT
Set
QCl c(Q) = b(K);
Set-c(K) = b(Q), editing if K is 0020-0023;
Take next instruction from I + 1.

Code 12. I: AUG K: Augment. 2 MCT

QC2 If b(K) 2 f 0, set d K ) = b(K) + 1,editingif
Kis0020-0023;
If b(K) 5 - 4,
set. c(K) = b(K) - 1, editingif K i s 0020-0023;
Take next instruction from .I + 1.
-~
Code 12. I: DIM K Diminish 2 MCT
QC3 If b(K) > + 0, set c(K) = b(K) - I , editingifKis0020-0023;
If b(K) = -+ 0, s e t c(K) = b(K),editing if K is 0020-0023;
If b(K)< - 0,
,set c(K) = b(K) + 1, editing i f K i s 0020-0023;'
Take next instruction fromI + 1.
Remarks: DIM does not generate output pulses as DINC does.

Code 13. I: KDCA Double Clear

and Add 3 MCT
Set c(A, L) = b(K, K+1); .~.

Set c(K) = b(K), editing if K is 0020-0023;

Set c(K+1) = b ( K + l ) , editing if K+l is 0020-0023;
Take next instruction from 1 + 1.
Remarks: 'The final c(L) will be overflow-corrected. The
operation code should be treated a s 30001 (see DAS, page 8).

13
 Code 14.. I: DCS I< Double Clear and Subtract 3 MCT'
Set c ( A , L ) = -b(K, K+1);
0 . Set c(K) = b(K), editing. if K is, 0020,-0023;
Set c(K7 1) - b(K+l), editing if K+ 1 i s 0020-0023;
Take next instruction f r o m I + 1.
R.enlarks: DCS A succeeds i n complementingthedouble pre-
cision accumulator - implied-address code: DCOM. The final c(L) will be
overflow-corrected. The operation code should be treated as 40001 (sqe DAS
page 8 ).
Code 1 5 . I: INDEX K Index Extracode
Instruction 2 MCT
(See INDEX, page lo).
Remarks: This is the only extracode that does not reset the
extracode switch. The way to index a n extracode ( M P , say) is:
EXTEND
INDEX ADDRWD . '

MP 0
The extension (extracode switch) will stay in force during any n-level nesting
of extracode INDEXes. This INDEX w i l l never act 'as a RESUME.
0 Code 16. I: SU ' K Subtract 2 MCT
. QCO Set
c(A) = b(A) - b(K);
Set c(K) = b(K), editing if K is 0020-0023;
Take next instruction from I + 1.

Code is. I: BZMF K Branch

Zero or Minus to
Fixed' 1or 2 MCT
QC 1-3 If c(A) -
< + 0, takenextinstructionfrom K andproceedfrom
there (1 MCT);
Otherwise, take next instruction from I + 1 (2 MCTJ .
Code 17. ' 'I: M P K Multiply 3 MCT
Set c(A, L) =. b(A) X c(K);
'Take next instruction from I + 1.
R.emarks: The two words of the product agree in sign. A z e r o
-
r e s u l t is positive unless b(A) = + 0 and c(K) is non-zero with the opposite sign.
M P does not edit an argument from 0020-0023 because there isnit
enough,time.

0
14
 . .

Implied-Xddress
Codes , .

Some operations'are defined for only one address value, like RESUME;
others have unusual results when addressing ce'ntral registers, For conven-
ience in using these operation, the YUL S:ystern assembler recognizes
implied-address codes, written without an address, and fills i n the address.
These codes are shown i n Fig. 5 (alphaberieally) and Fig, 6 (by actual code).
Brief descriptions follow;

Code 00. I: XXALQ Extracode

Execute 2 MCT

K = 0000 Using A , L and Q

Assume that b(A) = 000006 and b ( L ) is an extracode
instruction;
Execute the EXTEND in A , the instruction in L, then
. r e t u r n t o I+ 1; leave. c(Q) = 000003.
Remarks: This is a marginally useful op,eration because
an extracode instruction built up in L could usually be executed betterby
the sequence:

EXTEND
INDEX L
0 0

Code 00. I: XLQ Execute

using L and Q 2 MCT

K = 0001 Assumethat
b(L) is a basic
instruction.
. Execute the instruction in L and, if it is not a successful
branch, return to I + 1;
c c(Q)Leave = 000003.
Remarks: Like XXALQ, thisoperation is marginal. '

The t i m e (2 MCT) f o r XXALQ and XLQ includes the. TC t o A o r L and the

r e t u r n TC f r o m Q, but not the time spent in executing C(A) Or C ( L ) .

Code 00. I: RETURN Return

from
Subroutine '
2 MCT

., K = 0002 Assume
that b(Q) = TC K';
 6
*
. .
.. . , .

Take the next instruction from K' a n d proceed

from there;
Leave c ( Q ) = 000003.

Code 00. I: RELXKT Release

(allow)
Interrupt 1 MCT
K = 0003 Allow interrupt
after this instruction
(subject
to the restriction that interrupt cannot occur.while thereis + over- -
flow in A 1;
Take next instruction from I + 1.

Code 00. I: INHINT Interrupt

Inhibit 1 MCT

K = 0004 Inhibit
interrupt
until a subsequent RELINT;
Take next instruction from I f 1.
Remarks: 'The inhibition set by I?JHI!.'lT and removed
by RELIST is entirely independent of the one set by interrupt and
removed by RESUME.

Code 00. I: EXTEXD Instruction

Extend
Next
1'MCT
K = 0006 Takethenextinstruction f r o m I +,1 andexecute .
it a s . a n e x t r a c o d e .
Remarks: If the next instruction is INDEX (full code 151,
the following instruction will be executed as an extracode too,

Code 01. I: NOOP No Operation

(Fixed) 1 MCT
QC1-3 Take
the
next
instruction
from I + 1.
K=I+1 Remarks:
This is how N O O P is assembled
when I
is in fixed memory. . .

Remarks: If b(A contains2 overflow, the results

0 are messy; i n particular, sgn [ c ( A ) ]
),

# sgn [ b(A)] . I
If b(A)l 2 1 / 2 ,
overflow w i l l be retained i n c(A).
-.

16
I . . .
 , . . . . .

. . .
IhIPLTZIC, ADDRESS .CODES .

Actual Implied- Register iV0r-d

Address Oper2.tion (If a p p l i - a s as-
Code Code cab1.e). . sembled NQTE

COM CS A 40000
DC OM DCS A .. .. 4000 1 x ,
DDOUBL DAS A 2000.1
DOLT BLE AD A 60000
DXCH DTCU z 52006 .

~ __ . .

DTCF DX CI-I FB . 52005

EXTEKD TC 00006 S.
INHINT TC 00004 S
NOOP TC F 1 (I+1) F
NOOP CA A 30000 E
__ 2

OVSK TS . A 54000
REUNT TC . -. 00003 S
RESUME INDEX BRU PT - 50017 R
RE TURN TC- Q - 00002
SQUARE 3 MP A 70000 x
---------------------

TCAA TS z - ..
54005
.-
XLQ TC L 00001
XXALQ TC A . - 00000
-

ZL LXCH 22007
ZQ QXCH 22007 X
~~i---~-------------------
. .

NOTE EXPLANATI0.N:
E Applies when I (location of instruction) i s in erasable memory.
F Applies
when I is fixed
in memory.
R Special RESUME hardware responds t o a d d r e s s 0017.
S Special
Indicator-setting
hardware
responds
addresses
to
- OO03j 0004, and 0006.
,e
-w

X

instruction.
~
Extracode
~ .
Fig, 5

17
~
 . .

0 I M P L I E D AD.DRESS C O D E S
(By Actual Code)

Actual , Register Word as Implied- . NOTE

Operation a s s (If
e mabpl e- d Address (See
Code plicable) Code Fig. 5)

TC A 00000 XXALQ
. TC L 0000 1 XLQ
TC Q 00002 RETURN
TC 00003 RELINT S.
TC 00004 INHINT S
TC 00006 EXTEND S.
~_~, --------------------

TCF 1 (I+1) NOOP F

DAS .A , 20001 DDBUBL

ZCH A
2 2007
30000
ZL
NOOP . E
cs . A , 40000 COM
INDEX BRU PT . . 50017 .RESUME R
~---------------
I .

DXCH .FB 52.005 DTCF

DXCH , z 52006 DTCB
Ts A 54000 OVSK
Ts z 54005 TCAA
AD A 60000 DOUBLE

~
,
~

~

QXCH 22007 ZQ X
DCS. A 40001, DCOM x
MI? A 70000 SQUARE X

Fig. 6

18
 . . .

Code 0 2 . I: Z L Zerp L 2 MCT

K = 0007 Takenestinstraction f r o m I + 1.
R e m a r k s : This code and its companion ZQ depend
on two properties of a d d r e s s 0007: no s t o r a g e is associated with it,
a n d r e f e r e n c e s to it (in Pact, to any of 0000-0007)a r e not checked
f o r good pnrity. A d d r e s s 0007 is t h e r e f o r e a g e n e r a l l y . u s a b l e s o u r c e
of z e r o s .

Code 0 3 I: NOOP No O p e r a t i o(nE r a s a b l e ) 2 MCT

K = 0000 Takenext instruction from I + 1.

R e m a r k s : T h i s is how N O O P is assembled when I
is i n e r a s a b l e m e m o r y .

Code 04. I: COIL1 Complement.c(A 1 2 MCT

iJ
K = 0000 Set'
c(A) = -b(A);
Take next ins,truction from I + 1.
R e m a r k s : A l l 16 bits a r e c o m p l e m e n t e d .
~.

Code 0 5 . I: RESUME R e s uI nmt e r r u pPtreodg r a m 2 MCT

QC 0 Set c(Z) = ~ ( 0 0 1 5 ) ;
K = 0017 U s ~e ( 0 0 1 7 ) a s the
next
instruction.

Code 0 5 . I: DTCF
Double Transfer
Control, 3 MCT

QC 1 Switching F bank
..
K = 0004 Set c ( A , L ) = b ( F B , Z ) ;
Set c(FB, 2) = b(A, L);
T a k e next instruction from I + 1.
R e m a r k s : A double-precision address constant
f o r m a t , 2 FCADR, is defined for use with DTCF.

19
 .. 1

. .

0. ,Code.05. I: DTCB
Double Transfer
Control . 3 "IT
Switching Both Banks

Set c ( A , L) = b(Z, BB); i

Set c(Z, BB) = b(X,L);
Take next instruction from I + 1.
Remarks: A double-precision address constan : t

f o r m a t , 2 BCADR, is defined for use with DTCB.. .

Code 05. I: OVSK Overflow

Skip . 2.MCT

QC 2 Dochange
not c(A);

Code 05. I: TCAA Transfer..Control

to 2 MCT

0 QC2 i nA d d r e s s A ' ~

K'=0005 ' + overflowinb(A),set

If - + 1.;
c ( A ) ' =-
. Takenextinstructionfrom the locationwhoseaddress is .

in bits 1 2 - 1 of b(A). . ,
Remarks: The perils associated with TCAA i n Mod
3C and Block I AGC do not exist in Block I1 AGC.

Code 06. I: DOUBLE Double c(A ) 2 MCT

Code 12. I: ZQ Zero Q 2 MCT

K = 0007 Take next instruction from I + 1.

Remarks: See under ZL.

20
 Code 14. I: DCOM Double Complement 3 MCT

Code 17. I: SQIJARE Squar e c(A) 3 MCT

K = 0000 Set c(A, L: = b(A) X b(A),
. f.r o m I + 1.
Take next in'struction
Remarks: Results are. messy if'b(A) contains -
+ ,

overflow.

. .
Unprogrammed Sequences,
Some of the actions performed by the computer are not programmed
but occur,in response to external events., The categories of these un-
. programmed'sequences are shown in. Fig, 7 . Interrupt is inhibited i f a n
interrupt has occurred after the latest RESUME, or an INHINT has occurred
. after thelatestRELINT,or c(A) contains -
+overflow;Otherwiseinterrupt '

may.occur before any basic (non-extracode) instruction except RELINT,

INHINT, or EXTEND.
RU PT Program
Interrupt 3 MCT

S e t ~ ( 0 0 1 5 )= b(Z);
S e t ~ ( 0 0 1)7 = the postponed instruction;
Take next instruction from the location whose address
is permanently associated with .the cause of the interrupt, and proceed
from there. Inhibit further interrupt until RESUME.
Remarks: See also remarks under INHINT.

Counter increments and decrements, serial-parallel conversion steps, .

and GSE interface transactions a r e lumped together under the name of
counter interrupts because they perform limited tasks by snatching one o r ,

two memory cycles and then let the'computer continue. They can occur
before.any instruction except RELINT,,INHINT o r EXTEND.

21
 UNPROGRAhILTED SEQUENCES

RU PT
Program Interrupt

PINC .
Counter IncrementlDecrement
. .
PCDC
, . MIN C
MCDU
DINC

SHINC
Serial-Parallel Conversion
(and vice-versa,) SHANC

INOTRD
Ground Suppact Interface

a . .
INOTLD
FETCH
STORE

GOJ
Manual Override
.TCSAJ

Fig. 7

' . 22
. .*

PINC Plus ent

1n.crem 1 NCT

Set c(C.TH) : b ( C T R ) + 1;
I f + overflow, set c ( C T R ) = + 0 and set UP

an interrupt if CTR = T3, TJ: o r T 5 o r set up a PINC for'T2

i f CTR = T1.
Remarks: ,This sequence and its priority..chain effects
: :
a r e s h a r e d by the. instructjnn I NCR. .
.!
!;
I

I .

s i
' ,
. PCDU Plus Increment (CDU) 1 MCT
'

Set c(CD1'CTR) = b(CDUCTR) + 1 in twds

complement modular notatlor).
Remarks: Incrementing in twds-complement modular
notation transforms 7 7 7 7 7 into 00000 and 3 7 7 7 7 inh'o 40000, and is other-
wise like one&-complement. INCR never acts like PCDU.. PCDU and
~ MCDU replace PINC and MIXC for counters 0032-0036.

IkiINC*Increment Minus 1 MCT "

' Set c(CTR) = b(CTR) - . 1;

-
If overflow, set c(CTR) = - 0.
r
MCDU Minus Incr.ement(CDU) 1 MCT

Set c(CDUCTR) = c(CDUCTR) - 1 in twos

complement modular notation.
R e m a r k s : T r a n s f o r m s 40000 into 37777 and 00000
into 77777. S e e r e m a r k s u n d e r PCDU.

DINC Increment
Diminishing . 1 MCT
e
If c(CTR) > + 0, set c(CTR) = b(CTR) - 1 and
,emit signal POUT (Plus Output);
If c(CTR) - 0, set c(CTR) = b(CTR) + 1 and
e m i t signal MOUT (Minus Output);
If c(CTR) = -
+ 0, leave c(CTR) unchanged and
emit signal ZOUT ( Z e r o Output & tu'rn'off.DINC request).

' .
 . .
' . . ' .
. .
i i
. .
I .

1 1

1 ,

Remarks: Used to generate output pulse trains

0 and to count down T6. Values to be counted downby DIKC might be
developed by the instruction-MSU .from a d e s i r e d a n d a n a c t u a l CDU
. ..,, .
angle. T h i s sequence is s h a r e d by the instruction D I N , but without
POUT, MOUT a n d ZOUT. . I

SHINC Incrcm
ent'
Shift 1 MCT
;
.
Set c(CTR) = b(CTR) + b(CTR); .
_ I

If + overflow, set the priority chain station

for this counter.
R e m a r k s : SHINC a n d SHANC a r e u s e d t o c o n v e r t
incoming serial b i t s t r e a m s i n t o w o r d s f o r p a r a l l e l a c c e s s , a n d t o
convert words to outgoing serial b i t s t r e a m s .
SHAKC and Shift, Add I n c r e m e n t 1MCT
' Set c(CTR) = b(CTR) + b(CTR) + 1;
If + overflow, set the priority chain station
for this counter.
0 . ' R e m a r k sS: eue n d e r SHINC.

GSE INOTRD
to Read In/Out 1 MCT
. .
Accept a c h a n n e l a d d r e s s f r o m the Ground
Support Equipment and place the contents of the addressed input/
output channel on the GSE data busses.

INOTLD In/Out Load from GSE 1 MCT

Accept a c h a n n e l a d d r e s s f r o m t h e G r o u n d
Support Equipment and write the contents of the GSE data busses
int.0 the addressed input/output channel.
c

FETCH F e t c h from M e m o r y to GSE 2 MCT

Accept f r o m the Ground Support Equipment a
setting for eith.er FB o r EB a n d a n a d d r e s s for the corresponding
memory, and place the contents of the address,es location on the
0 GSE d a t a b u s s e s . Do not edit if t h e a d d r e s s is 0020-0023.
Then restore b(BB).
a4.
 ' STORE 2 MCT

Accept f r o m the Ground Support Equipment

' a setting for EB and an a d d r e s s i n e r a s a b l e m e m o r y , a n d w r i t e
the contents of the G3E data busses into the addressed location.
. T h e n r e s t o r e . b ( B B ) , u n l e s s the location stored into is BB it'self.
The manual override instructions can occur at
. a n y t i m e b e c a u s e they a r e not obliged to p r e s e r v e t h e s t a t e of the
computer.

GOJ Go Jam 2 MCT

SGt c ( Q ) = b(2);.
Take next instruction from location 4000
f r o mp r o c e e d a n d there. !

TGSA J T r a n s e r . C o n t r o l to Specified 2 MCT .

A d d r e s sJ a m '

Take next instruction from' the location

w h o s e a d d r e s s is on the Ground Support Equipment data
b u s sapenrsd
o, c e e d from there. / .ii

?
!

Address Constant Formats

T h e a d d r e s s c o n s t a n t s available for Block II p r o g r a m m i n g are

.considerably different than for Block I. A s u m m a r y of them follows.
The EBANK= code is a l s o d i s c u s s e d .
c'

Address ADRES

REMADR Remote Address

GENADR General Address

25
 .. .

Each of t h e s e c o d e s c r e a t e s a single precision constant word

identical to the instruction w o r d that would have resulted
. . i f the opcode

.
' had been TC. ADRES requires the location a n d address values to be
-
. .

- -
i n the sarne F Bank if both a r e ir, F Banks a n d to be i n t h e s a m e
E - Bank both a r e in E - Banks.
if REXIADR requires the location
and address values to be in different F - Banks if both a r e i n F - Banks
.. and to be in different E - Banks i f both a r e in E - Banks, GENA,DR
doesn't care.

CXDR FCADR (Fixed) Complete Address

These codes are synonymous. The address value must be in an

-
F Bank. The resulting single precision constant word equals the pseudo-
address value minus octal 10000. Bits 15-11 equal the 3- - Bank number
and bits 10 - 1 equal the relative location of t h e a d d r e s s i n that hank.

Erasable -Complete A'ddress

0 :
"I'he a d d r e s s 'value must be erasable, 0000-3777 and the resulting
s i n g l e p r e c i s i o n word equals the the eleven bit pseudo-address. Bits
15-12 = 0.

EBANK= E r a s a b l e Bank Declaration

This code does not generate an AGC word. It informs the assembler
of which E-Bank the programmer intends subsequent E-Bank addresses
to be in. For basic instructions and interpretive address w o r d s t h e a s s e m -
bler c o m p l a i n s w h e r e v e r a n a d d r e s s is equivalent to' a location in a different
E-Bank. If the E B A N K = code is followed by* a BBCON, 2BCADR o r
ZCADR code, this EBANK= value is good only for 'that one subsequent code,
and then the previous EBANK= setting is r e s t o r e d , T h i s is called a
11
one-shot E B A N K = declaration".

4 "followed by" means with no instructions, interpretive opcode words,

'or address constants intervening.
I

. . 26
 BBCOX Rotti ,Bank Con

T h i s codegenerates a singleprecision co wordintended as

data to be placed i n t h e I313 c e n t r a i rtzister.' T r e s s valuemust
be a fixed rnernory location o r itmust be eyuiv a v a l i d F - Bank
number,(range 0 - 2 7 now, 0 - 4 3 l a t e r ) . Lits 1 the
resulting
word
equal the address'. bank rlumber (fixed fixed
.-

' Bits 10 - 4 a r e zc.rIos. Bita S - 1 equalthecu

ZCADR 2BCADH
a BBCOX
These
codes
are
synonymous. This co e d to be used as
.?
the operand of a DTCB (DXCH Z ) instruction. Two c o n s t a n t w o r d s a r e
generated by this code. The f i r s t w o r d is formed under the rules for
I
GENADR. T.f the address value is in fixed memory, the second word is
f o r m e d u n d e r t h e r u l e s f o r BBCON. For an erasable address the second

:g
r .-
word becomes OObOx where x = the address' octal code EBANK number
iri.the range 0 - 7.
,
;.I
:1

, '
'

BFCADR Double Complete Address Including an

FCADR

This c o d e ' s a d d r e s s v a l u e m u s t b e
1
in fixed memory. The code is
intended as an operand of a D T C F (DXCH FB) instruction. Two constant .

w o r d s a r e g e n e r a t e d by this code. The first word is formed under the

rules for FCADR, and second under the rules for GENADR. Exception:
both words are GENADRs i f a d d r e s s v a l u e is in fixed fixed.
' !

' Control Pulse Definitions

To understand the control pulses and the pulse sequences, it is n e c e s s a r y

to know the u n a d d r e s s a b l e c e n t r a l r e g i s t e r s : i
,: i
G Memory
Local
Register Bits 1 16-1
' -
In an MCT in which erasable mem0r.y is cycled,
the word f r o m m e m o r y a p p e a r s i n G by the 5th microsecond (time 5
of 12 times) of the MCT. If it is left .there through time 12, i t is
- -4 . .s;
. :
. ,27
 restored exactly as i t w a s r e a d out. If a new value is, n'ritten into G before
t i m e 10, that becomes the new value in the memory location. 1Vhen.fixed
m e m o r y is cycled, the w o r d a p p e a r s i n G by time 7 .

wL Write Lines o r B u s s e s . Bits 1 - 16

These a r e t h e n o r m a l m e d i u m of communication among
central registers, although some private lines exist.

B General
Buffer
Register
Bits 1 - 16
T h e B register always holds the instruction word at
the beginning of each instruction.
. .

C Complement
Output of B Bits 1 - .I6
Not a separate storage. Each bit of C is the opposite
. of the corresponding bit of B.

Y BitsInput
Primary,
Adder 1 - 16
Ha's conventional and doubling inputs.

X Bits
Secondary
Input
Adder 1 16 -
Fed by private line from A and from constant
generators.

s t o r a g e of i t s own.
. .

S Address
Selection
Register
Bits 1 - 12 .

Holds the address of a fixed memory location

f r o m t i m e 8 of the. preceding MCT through time 7 of the current MCT,
o r holds (in b i t s 1 - 10) t h e a d d r e s s of an erasable memory location
from t i m e 1 through time 7 of an MC.T.

28
 .
.. .

SQ Sequence Selection Register

. .

Holds the operation code during esecution of each

instruction. Bit 15 is the extracode bit. S Q is aided by a three-bit stage
counter and two branch flip-flops. A stag.? counter value of 2 s e l e c t s the
standard fetch-next-instluclion subiItstruction, regardless of the c(SQ)
and the branch bits. Sequence selection by S Q is suppressed
. .
during
counter i n t e r r u p t s by a signal called INKL.

29
d2x .
6lSX .

CI
CLXC

OVSl

EXT

.KPPl

L16

MONEY

MOUT

NEACOF

NEACnN

NIso

PIFL

PONEX SET B I T 1 OF X TO l r

PQllT

PTWOX '
0 .R 1 C
-R 6

RA

RAD

RB

RH1
Rf3 1 F

RB?

RB8K

wc
RCH

PG

PL

RLlORB
RQ
RRPA READ THE ADDRESS OF T H E HIGHEST P R I O R I T Y
I N T E R R l l P TR E O U k S T E D e

RSC READ TIJE C O N T E N T DF CEFjtRAL STORE DEFINED R Y

THF ADDRFSS C U R R E N T L Y I N S:
CENTRAL STORE B I T S 1-16 ARE COPIED To WLl'lbr

RSCT READ THE ADDRESS OF H I G H E S T PRIOA1,TY COUMTER REQIJEST.

.RSTHT

RSTSTG

RU ,

31
. .

RZ

ST?
STAGF

fL15
TMf

TOV

I TSGN

3"""'
TSCU .

k'A CLFAR A N P , h R l T E WLl-16 INTO A l - 1 6 ,

WALS * CLEAR ANf' b R I ITNET O A1114 FROM WL3-160 CLEAR AND
W R I T E l N T O L 1 3 * 1 4 FROM WL192. C L E A R AND'WRITE INTI]
A I 5 9 1 6 FROM G l b ( ' I F G l = O ) OF? FROM WLlb ( I F G l = l ) o

k u CLEAR ANI! M H I T E WL1-16 INTO P1-160

WCH CLFAR AbID W R T T E W L 1 = 1 4 * l b o P A R I T Y INTO CHANNEL B I T S
1 = 1 4 + . l 6 , D A R 1 T Y o CHANNELS 1 AElD 2 N Q I T E - 'AS W.L AluD iQO
THE CHANF'EL T O BE LOADFO IS SPECIFIED' R Y THE
CURRENT CONTFNT OF S o .

CLFAR A&iO W R I T E W t I = l bI N T O G1-16 FXCEPT

FOR ADDRFSSES O C T A L 2 0 1 2 3 , WHICH CAUSE EDITING,

32
 VOVR

t!Q

w S,
wsc

bI so

MY

WYl2

WYD

WZ

215 ' SET R I T 1 5 OF Z TO'lr !

. .
t

2 1.6 SET 311 16 OF Z T O 1.

ZAP

ZIP
Ll5 L2 Ll HEAD W R I T E C A R R Y
m WY
0 0 0 I)

0
0 0 1 .RP WY
,o 1 0' He WYD =
0
1
1
0
0
1 1
0
1
.
RC
Re.
RB
MY
WY
WYD
--
CI

e 1
1
1
1
0
1 -
RC WY
wy *
CI
L

zOUT

*
 I~!STRIICTIO~JS

a P CODE E X T 5016r16=10

' TC 0 OQO
ccs n 001 or
TCF o no1 0 1
TCF 0 001 l o
TCF 0 001 11
DAS 0 G I G ,Oc
LXCH 0' 010 01
INCH 0 010 10
ADS 0 ' 010 11
. CA r! @I1
cs 0 100
INDEX ( N D X ) n 101 00
DXCH d 101 0 1
TS 0 101 I d
XCH 0 101 11
AD 0 1.10
MASK (L'SK 1 0 111

' READ I cloo on o

WRITF 1 000 00 1
1 000 01 0
1 000 01 1
ROR 1 000 10 0
MOR 1 ' 0.00 10' 1
RXOR 1 000 11 0
EDRUPT 1 000 .11 1

1 001 00
1 001 01
1 001 10
1 001 11
1 010 O@
1 010 01
1 010 1@
1 010
11
1 011
1 100
1 101
1 110 00
1 110 01
1 110 16
t 110 I1
1 111

34
' .
 2r
B e

TCSA.13
. .
29 RSC VJG
8e Lis WZ S T 2

ccso
'
RI lbBP WS
H.S.C Ai,
R G WB TSGkI T Y Z T P 9 G
R 7 WY12
RI. WY 1 2 PO?.IFX
R7 W Y i 2 PTtvOX
' RZ W Y 1 2 PONFX PTWPX
RLI WZ lyS
R R WG
RP W Y 'tONFX CI S T ?
WY S t 2
RC WY HCINFX CI S T 7
RIJ WA

TCFO

35 ' ,
 .. .

A3X

WG fnv
RA WY ST1
WA k ' Y S T 1 PC??.+EX
RA W Y S T 1 EICI:;EX
RA WY S T 1

R I . 1 O B R WS
HSC &Cl
Rl! W A '

RC W Y A 2 X .
R l I WG WSC T O V
MA
MA R B I
wA R 1 C
WP
R t WS S T 2
RC f M t
NL
RI.! W A

LXCHO

1. R L l 0 5 f 3 WS
2. R S C UlC
30 R L . W8
50 R G WL
7. RR WSC WC
Bo R Z WS S T 2

I NCRO
' 1. RLlOBt! ws
2. ' R S C WG
50 RG WY TSGN T M Z TPZG
bo PWEX
7* RU WSC WG NQVR .
88 R7 WS S T 2

36
. .

RL LOBP. WS
RSC ~ ( i
RCI W Y A 2 X
R II kG T O v
WSC
.wP '

dA at31
. dJA SIC
wA
R t WS S T 2
t?c 7'147
RlI W.4

R S C d(i
86 WB
R t WS S T 2
. R P WG
RP WA

R S C WG
, RG WH
R2 WS S T 2
HB wG
RC 'WA

37
, ' .
. . . 1

HZ WY12 CT
RSC rruG hi1 SQ
RP WZ
R P WB
R7 WA
RU k ' l
R G WY A 2 X '
' RCI b!S .
HR NA
RII .WB .

0
W 1'5%S,
R-SC biC N I S Q
RG WZ
HP b!.G
RAD dip WS

HLlOBB WS WY12 MOF'EX CI

RSC biG
RL WB
RC WL
R e WSC WG
R U WS WR
ST 1

R L l O B P WS
R S C WG
RP Wt3
RG W A
RF! WSC WG
WZ WS ST2

38
' .
 PlJL.5F SFOUENCES

TSQ

ADO

RSC HIG
RG WB
RZ ws ST2
R R WG
RP WY A 2 X
RLI WA

R S C i4G
R A WB
RC WA
RC we
RZ WS . S T 2
e RC R A WY
RO WB
RC WA

3Y
 . .

PULSE SFOUFNCES

RLlClBR \r;S
RA WB
WY
RCH W P
RP W A
R A WB
R Z CIS ST.2

W L l O B R WS
R A WL3 WC
WY
R C t i WR
R.A WCH
R A WB
. R Z WS 5 7 2

R L l O B R w5
RA ,Wt3
R C WY
HCl4 WP
WC RLI I ~ A
RA W6
HC W A
R 2 WS S T 2

R1.1088 WS
Rh bi6
RC WY
RCH N R
RC RU. WA
RA WB
R C W A WCH
RZ ws ST2

- .
 ..
. . . I
. .

'. .
R L l C B R WS
R A lA*e
.RC R C H WY
RCH rtR
, R A R C WC
R G kB
R Z WS S T 2
RC WG
R l t WH
RC R G W A

R15 M S
RSC h G
RZ KG
ST 1

R1S RP2 Ws
RSC W G
RRPA wz
R 2 WS S T 2
RB k!G KRPT
DVO

lo '

2. @x
20 1x
3. .

DV 1
RI MY
I?[ \r!B T.SGFI
RP h'Y 0 1 5 X
R C b,'Y R 1 5 X Z16
R U WL TOV
RC. RSC AB TSGN
R A ' WY PONEX
R A WY,'
RP b!A
R C WA 215
RLJ W R
RL WYD
.RIJ WL
' LZGD PE! WYD A2X PIFL .
20 ox ,RG WL TSGlJDVST Ct XC
2 0 I X RG' WL TSGU DVST R P 1 F
30 R \ I WB STAGE

OV3

40 LZGD PI3 WYD A2X PTFL

5 0 ox R 6 \JL TSGlJ C L X C
50 1x RC NL T S G U RHlF
60 Rll WE3
70 L2GD RR WYD A2X PTFI..
Bo ox R C WL TSGU CLXC
8 0 1x RG WL T S G U Q U L F
90 RU WB
100 L2GD RR WYD A2X PIFL
Jlo ox RCI NL T S G U C'LXC
1 1 0 1x RC WL T S G U R B l F
120 Rl! WB
1. L?CD RF? WYD A2X PJFL
.20 ox RC WL TSGlJ D V S T C1.XC
20 IX RC WL T S G U OVST RRlF
30 R U WB STAGE
. .

L2GD RE! WYO A 2 X P l F L

RG WL TSGU C l . X C
RG WL 'TSGtJ R t 3 l F
RU WB
L3GD RF! WYD A Z X P I F I I
RG WL TSGU C L X C
RG WL TSGU R B l F
RlI Wt3
L 2 G D PR WYD A 2 X PTFL
RG WL TSGU C L X C
R G WL TSGU R B l F
RU WB
L Z G D R B WY3 A 2 X PIFl
RC WL TSGU OUST CLXC
RG W t TSGU D V S T RPlF
RlJ WB STAGE

R l l WB STAGE
LPGD R B WYO A 2 X PTFI
RG WB M A TSGU C L X C
RG WB WA TSGU R ~ W
R Z TOV
R C WA

RIJ W8 W L '
RC WL
 RZFO

H A WG TSGFJ TMZ , ,
TPZG
R S C nG
WP M Y 1 2 CI
R I ' WZ
Hi! WS S T 2
R A D wkR WS N I S O . .
, .

1. R L l O R R WS
2r RSC WC
5r R G WH
6r R C WY C I A 2 X
7, HlJS LUA TSGN
8, R7 WS S T 2
9. RE? WG .
101 1x Rh WY MQNEX
110 R U S dA

QXCHT,
@
le Rl.1OBP WS

.
'

2. R S C AG
,3 R O WB . .
5. RG WQ
7r HP WSC WG
8r H Z WS S T 2
AUGO

R I l O B E WS
RSC 4G
HC WY TSGN TMZ TPZC
POrJFX
FlQflF X
RU WSC WG WOVR
R Z b1S S T 2

DIM0
R L l O B R WS
RSC 4 6
RC WY TSGN T M Z TP7G
MONEX.
6r 10 . POkFX-
@ ' 7. RU WSC WG .WOVR
R? WS S f 2
A,

,+9
 OCA 1

DCSO

, oc s 1

e
 . .
I '

H Z WY13 CI
R S C dC1 NISO
HP wz
R A 1413
HZ WA
R t J WZ
K G WY A 2 X
R l ! WS
RP FA
RlJ WN EXT

SUO

.2 0 ' R S C NG
70 HC WH
80 RZ.WS ST2
9. RP WG ,
10. H C 'tJY A Z X
11. RU WA

RZMFO

R P WG TSGN TMZ
TPZG
H S C WG
R R lr!Y12 CI
HI! W Y l Z ' CI
R P W Y 1 2 CI
wu WZ
RII WZ
R U WZ
R t WS S T 2
R A D kP WS N l W
R A D WP WS N I S Q
RAD WP. WS N I S Q

I . . .
 PULSE S F W E N C S

MPCI

2. H5C HG
3. W P b'B TSGFJ
40 ox RR W
' L
4a 1x H C 'QL
7. R G 'JR TSCtJ2
e a R Z 'ks
90 00 HFi WY
90 01 R R b.'Y CI , . .
9. 10 H C WY CI . .
90 11 H C WY
10, RU WR TSGhI ST1 NEACOh
11. ox WA
11. 1x WA RH1 R 1 C I 1 6

MP1

l e ZIP
2. ZAP
30 ZIP
40 z AP
50 ZIP
6. ZAP

'
4.
'Io

9.
ZIP
ZAP
ZIP
10'. ZAP S T 1 S T 2 . ,
11. ZIP

. MP3

1. ZAP
2. ZIP NISO
3. ZAP
40 R S C kG
50 RZ WYl2 CI
be R l J WZ T L 1 5 ' N F A C O F
'Io' 1x RR WY A 2 X
80 RAD AB WS
9r RA
10. RL
l l r I X R U WA

STD2

l e R Z W Y l 2 CI
2e RSC kC1 N I S O
6.a - R l j WZ
8. RAD AB WS
 . .
PCDli . .

I. R S C T WS . .
2. RSC WG
5r H G WY TSGN TMZ T P 7 G
CI
4.
6.
70 H I J S WSC iriG WOVR
HF! ws
MINC
1 b '

2. .
5e
6.
7?
Bo

MCDU

l e
2.
5.
6.
7.
8r

DINC

HSCT WS
R S C WG
RC WY T S G N TMZ T P Z G
MONFX POUT
PONFX MOUT
Z@UT
RIJ WSC WG WOVR
RP WS

. .
J

PULSF SFQuEIvCES

SH I t4c

1, b:S *

20 ' rJscWG
50 RCH
80 RP WS .

49
0

*
 AGC BLOCK n MEMORY ORGANIZATION A N D ADDRESSING

2- Zoo0
WORDS"

ERASABLE
MEMORY
400 (OCTAL1 '
PSEUDO
LCADR
EB SREC
EB SREG'
PSEUDO
ECADR
EB SRFC
EB SREC'
PSEUDO
ECADR
EB S A Y :
ooooo.
x om
0 1400

X 04oO
1 1400
01
UOOO

a0 400
0 400

101w)
X 1 OOO
ooo
EB .SRFG'
" - 2 1400
'OR@'
BOX PER
, PSEUDO 01 400 PSEUDO PSLUDO ' 02400 Psmo 03W PSEUDO ' (
843
0'
A ECADR 1400 ECADR ECADR 2;Un ECADR 3 fXU ECADR 3m
EB SREG . 3 1400 EB SREG 4 1 EB SREC 5 1400 EB SREG 6 1400 E8 SRCG 7 IQ,
t .
1
10 da:I C PSEUDO @
(
X I
)I
wcR D 5" v
FIXED MLMORY
2 O o ( r (OCTAL) L X T ltl S R t C x xx 4 LXK)
WORDS PER
CXT f B SREC' X 02 2 OOO
BOX
__
ca PSEUDO
-D6m

.I.
"
U
6000
WORDS'"
EX1 F B SREG X XX 6oin)
. EXT FB SREP x m z an
. .
PSEUDO loBo0 PSEUDO 12DKJ PSEUDO PSEUDO 20 ooo PSEUDO am)
FCADR OOOOO FCADR @OM] ADDRESSES
FCADR 10 m FCADR %am
. FB SREG x 00 2 E X 1 FB SREC X 01 2 w O 14 OOO-17 777 E XF1B SREG x 04 2m ,
EX1 FB SREG X 27 2
NON-EXISTENT . .

FCADR . .
EXT FB SREG 0 ?O Zoo0 EX1 F E SREC 1 33 2Es1)

L "
"SUPIR BANK 0 '
J\
"SUPER DANK 1"
u .
" NOT P R l f F R R I D