ACPI Specification Changes for Legacy Free

September 20, 1999

This document describes the changes for legacy-free settings that have been approved for incorporation in
the next release of the ACPI specification, to be published on the ACPI web site at:
http://www.teleport.com/~acpi/
Contents

ACPI Specification Changes for Legacy Free ................................................................................................ 1

4.7.5 Reset Mechanism .......................................................................................................................... 2
5.9 Generic Register Address Structure .................................................................................................. 2
5.2.5 Fixed ACPI Description Table ...................................................................................................... 3
5.2.5.1 Fixed ACPI Description Table Boot Architecture Flags ............................................................ 3
5.2.11 Debug Port Table............................................................................................................................. 4

This information is provided to you FOR INFORMATIONAL PURPOSES ONLY.

This information should not be interpreted as a commitment on the part of Microsoft, and Microsoft cannot
guarantee the accuracy of any information presented.
MICROSOFT MAKE NO WARRANTIES, EXPRESS OR IMPLIED, IN THIS DOCUMENT.

1999 Microsoft Corporation. All rights reserved.

4.7.5 Reset Mechanism
The optional ACPI reset mechanism provides a standard mechanism for completely resetting a computer.
When implemented, this mechanism must completely reset the entire systemprocessors, core logic, all
buses, and all peripherals. It must be equivalent to power cycling the machine.
The Reset Mechanism is implemented through an 8-bit register described by RESET_REG in the FADT
(always accessed through the natural alignment and size described in RESET_REG). To reset the machine,
software will write a value (indicated in RESET_VALUE in FADT) to the reset register. The system must
reset the computer immediately on the write to this register (that is, software will assume that the processor
will not execute beyond the write instruction.) The RESET_REG field in the FADT indicates the location
of the reset register.
The reset register must only exist in I/O space or in PCI Configuration space on a function in bus 0.
Therefore, the Address_Space_ID value in RESET_REG must be set to either I/O space or PCI
Configuration space (with a bus number of 0). As the register is only 8 bits, Register_Bit_Width must be 8
and Register_Bit_Offset must be 0.

5.9 Generic Register Address Structure

The Generic Register Address Structure describes the location and access methods of a hardware register.

Table 5-100. Generic Register Address Structure

Field Byte Byte Description
length offset
Address_Space_ID 1 0 Describes which address space the given register can be
found. Defined values are:
0 System Memory
1 System I/O
2 PCI Configuration Space
3-255 Reserved
Register_Bit_Width 1 1 The size in bits of the given register.
Register_Bit_Offset 1 2 The bit offset of the given register at the given address.
Reserved 1 3 Must be 0.
Address 8 4 The address of the register in the given address space
(relative to the processor). See Table 5-101 for specific
formats.

Table 5-101. Address Space Format

Address space Format
0 System Memory The 64-bit physical memory address (relative to the processor) of the register. 32-bit platforms
must have the high DWORD set to 0.
1 System I/O The 64-bit I/O address (relative to the processor) of the register. 32-bit platforms must have the
high DWORD set to 0.
2 PCI Configuration PCI Configuration space addresses must be confined to devices on PCI bus 0. The format of
Space addresses is as follows:
WORD location Description
Highest WORD Reserved. Must be 0.
PCI Device number on bus 0.
PCI function number.
Lowest WORD Offset in the configuration space header.
For example: Offset 23h of Function 2 on device 7 on bus 0 would be represented as:
0x0000000700020023.

1999 Microsoft Corporation. All rights reserved.

5.2.5 Fixed ACPI Description Table
Table 5-5. Fixed ACPI Description Table Format
Field Byte Byte Description
length offset

Revision 1 8 2
BOOT_ARCH 2 109 Boot Architecture flags. See Table 5-99 for a description of this
field.
Reserved 1 111
Flags 4 112 Fixed feature flags. See Table 5-6 for a description of this field.
RESET_REG 12 116 The address of the reset register represented in Generic Register
Address Structure. (See section 4.7.5 for a description of the reset
mechanism.)
Only System Memory, I/O Space, and PCI Configuration Space
(bus #0) are valid for values for Address_Space_ID. Also,
Register_Bit_Width must be 8 and Register_Bit_Offset must be 0.
RESET_VALUE 1 128 Indicates the value to write to the RESET_REG port to reset the
system (See section 4.7.5 for a description of the reset
mechanism.)
Reserved 3 129 Must be 0.

Table 5-6. Fixed ACPI Description Table Fixed Feature Flags

FACP Flag Bit length Bit offset Description
RESET_REG_SUP 1 10 If set, indicates that the system supports system reset through the
RESET_REG Register as described in section 4.5.7.
Reserved 21 11 Must be 0.

5.2.5.1 Fixed ACPI Description Table Boot Architecture Flags

This set of flags is used by an operating system to guide the assumptions it can make in initializing hardware
on Intel Architecture (IA-PC) platforms. These flags are used by an operating system at boot time (before the
operating system is capable of providing an operating environment suitable for parsing the ACPI namespace)
to determine the code paths to take during boot.
In IA-PC platforms with reduced legacy hardware, the operating system can skip code paths for legacy
devices if none are present. For example, if there are no ISA devices, an operating system could skip code
that assumes the presence of these devices and their associated resources. These flags are used
independently of the ACPI namespace. The presence of other devices should be described in the ACPI
namespace as specified in Chapter 6 [of the ACPI specification].
These flags pertain only to IA-PC platforms. On other system architectures, the entire field should be set to
0.

1999 Microsoft Corporation. All rights reserved.

Table 5-99. Fixed ACPI Description Table Boot Architecture Flags
BOOT_ARCH Bit length Bit offset Description
LEGACY_DEVICES 1 0 If set, indicates that the system supports end user-visible
devices on the LPC or ISA buses. End user-visible devices
include devices that have end-user accessible connectors (e.g.,
LPT port), or devices for which the operating system should load
a device driver so that an end-user application can use a device.
If clear, the operating system may assume there are no such
devices and that all devices in the system can be detected
exclusively via industry standard device enumeration
mechanisms (including the ACPI namespace).
This bits definition is unassociated with legacy devices
connected to an 8042 micro-controller. The presence of an 8042
micro-controller and its associated devices is indicated by the
8042 flag bit.
8042 1 1 If set, indicates that the motherboard contains support for a port
60- and 64-based keyboard controller, usually implemented as
an 8042 or equivalent micro-controller.
Reserved 14 3 Must be 0.

5.2.11 Debug Port Table

This optional table specifies an independent Debug Port for debugging purposes. If not present, the
operating system should revert to existing debugging devices. Systems indicate the address of the debugger
port in the Debug Port Table. This table is located in system memory with other ACPI tables. It must be
referenced in the ACPI RSDT table.
The presence of the Debug Port Table indicates that the system includes a Debug Port. The contents
contain information about the configuration of the Debug Port.
Table 5-21. Debug Port Table Format
Field Byte Byte Description
length offset
Header
Signature 4 0 DBGP. Signature for the Debug Port Table.

Length 4 4 Length, in bytes, of the entire Debug Port Table.

Revision 1 8 1

Checksum 1 9 Entire table must sum to zero.

OEMID 6 10 OEM ID.

OEM Table ID 8 16 For the Debug Port Description Table, the table ID is the manufacturer
model ID.
OEM Revision 4 24 OEM revision of Debug Port Description Table for supplied OEM Table
ID.
Creator ID 4 28 Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT,
and PSDT tables, this is the ID for the ASL Compiler.
Creator Revision 4 32 Revision of utility that created the table. For the DSDT, RSDT, SSDT,
and PSDT tables, this is the revision for the ASL Compiler.
InterfaceType 1 36 Indicates the type of the register interface:

0 = full 16550 interface.

1 = 16550 subset interface compatible with Microsoft Debug Port
Specification.
2-255 = reserved.
Reserved 3 37 Must be 0.
BASE_ADDRESS 12 40 The base address of the Debug Port register set described using the
Generic Register Address Structure.

1999 Microsoft Corporation. All rights reserved.