American University of Beirut

Department of Electrical and Computer Engineering

EECE 311 Electronic Circuits

Spring 2016

DESIGN PROJECT

This project is to be done in groups of three students.

One project report should be submitted per group.
(version 2016031901)

Design Specifications

You are to design an integrated circuit CMOS operational amplifier that has a
differential input and single-ended output, and that meets the following specifications:

Process CMOS 0.35 micron

Supply voltage (VDD) 3V
(+/ VDD/2 =
+/ 1.5V)
Differential gain (Ad) 85 dB
Common-Mode Rejection Ratio (CMRR) 100 dB
Load resistor (RL) 1000
Offset Voltage < 0.25 mV
VOV for all MOSFETs 0.2 V
Input common-mode range (ICMR) 1.5 V
Peak-to-peak output voltage (Vo,p-p) 1.5 V
Supply power dissipation (PS) Minimize
Area (see Area Calculation below) Minimize
The design specifications should be met under a variation of the supply voltages of
10% (10% higher or 10% lower than the nominal voltage).

You should use a positive +VDD/2 supply and a negative VDD/2 supply only.

There should be no offset voltage: Zero input voltages (at vin+ and vin) should result
in a zero output voltage. However, you can apply a DC offset at the input to zero the
output voltage. This differential DC offset at the input should not exceed 0.25 mV.

The input common-mode range is the range of common-mode DC input voltages vCM
(applied to both vin+ and vin) for which all MOSFETs are in saturation.

The available components are: NMOS transistors, PMOS transistors, and resistors.
Ideal sources can only be used to generate the supply voltages, not bias currents.

 








 















 















  
 




 







Area Calculation

Calculate the area by adding up the gate areas (WL) of all the transistors and the area
of the resistors. For the transistors, the minimum gate length L is 0.4 m and the
minimum gate width W is 0.6 m. W and L should be multiples of 0.01 m. For the
resistors, the minimum W and L are 1 m. Note that the resistance is given by
R = Rsheet number of squares = Rsheet (L/W), where Rsheet is the sheet resistance
and is equal to 300 Ohms/square.

Device Models

The device models are encapsulated in PSPICE sub-circuits; use:

x1 d g s b nmos params: W=1u L=0.4u

x2 d g s b pmos params: W=1u L=0.4u

to instantiate an NMOS and a PMOS transistor, respectively (you have to use the
prefix x instead of m) with a width of 1 um and a length of 0.4 um. The reason for
using a sub-circuit is to allow to decrease with increasing transistor length. Since the
transistor output resistance ro is proportional to 1/, the output resistance increases
with increasing L.
The sub-circuit definitions are as follows:

.subckt nmos d g s b params: w=1u l=0.4u

m0 d g s b nmos_internal w={w} l={l}
.model nmos_internal
+ nmos level=1 kp=150u vto=0.7
+ lambda={0.025*exp(0.4u/{l})/exp(1)}
.ends

.subckt pmos d g s b params: w=1u l=0.4u

m0 d g s b pmos_internal w={w} l={l}
.model pmos_internal
+ pmos level=1 kp=80u vto=-0.8
+ lambda={0.035*exp(0.4u/{l})/exp(1)}
.ends

For the NMOS transistors, the device parameters at minimum L are:

2 1
kn = 150 A/V , Vtn = 0.7 V, and n = 0.025 V .

For the PMOS transistors, the device parameters at minimum L are:

2 1
kp = 80 A/V , Vtp = 0.8 V, and |p|= 0.035 V .

The body terminal (b) of the NMOS transistors should be connected to the VDD/2
supply. The body terminal (b) of the PMOS transistors should be connected to the
+VDD/2 supply.

Grading

100 points total:

10 points for conciseness and clarity of the report

40 points for meeting the specifications (VOV, Ad, CMRR, ICMR, and offset)
20 points for how well the area is minimized
20 points for how well power is minimized
10 points for originality and creativity of the design

Due Dates

Wednesday/Thursday March 23/24, 2016: Group form signed and submitted

in hard copy in class.

Thursday April 28, 2016: Final report with results and SPICE files submitted
electronically on Moodle by 11:55 pm.