DE2 UserManual - En.vi

Board DE2 Altera
DE2 y ban Pht trin v Gio dc
Hng dn s dng
phin bn 1.4 Bn quyn 2006 Cng ty C phn Altera

Board DE2 Altera
NI DUNG
Chng 1 DE2 Gi .............................................. .................................................. ..................... 1
1.1 Ni dung ng gi ................................................ .................................................. ............... 1
1.2 Ban hi DE2 .............................................. .................................................. .... 2

1.3 Bt Tr gip ............................................... .................................................. ........................ 3
Chng 2 Altera DE2 Ban ............................................. .................................................. ..............4
2.1 Giao din v thnh phn ............................................... .................................................. .....4
2.2 S khi ca Ban DE2 ........................................... ............................................. 5

2.3 Power-up Ban DE2 ............................................ .................................................. ....... 9
Chng 3 DE2 Control Panel ............................................. .................................................. .......... 10
3.1 Control Panel ci t .............................................. .................................................. ........... 11
3.2 Kim sot n LED, Mn hnh 7-Segment v LCD hin th ...................................... ... 13
3.3 SDRAM khin SRAM / v Programmer ............................................ ........................ 14
3.4 Flash Memory Programmer ............................................... ................................................ 16
3.5 Cu trc chung ca DE2 Control Panel .......................................... ............................ 17

3.6 CNG C - Multi-Port SRAM / SDRAM / Flash khin ....................................... ............ 19
3.7 VGA Display Control .............................................. .................................................. ......... 20
Chng 4 S dng Ban DE2 ............................................ .................................................. ....... 24
4.1 Cu hnh FPGA Cyclone II ............................................ ......................................... 24

4.2 S dng n LED v chuyn mch ............................................ ................................................ 26
4.3 S dng Mn hnh 7-segment ........................................... ................................................. 30
4.4 Clock u vo ............................................... .................................................. ...................... 32
4.5 S dng cc module LCD ............................................. .................................................. ....... 33
4.6 S dng Header m rng ............................................. ................................................. 35

4.7 S dng VGA ............................................... .................................................. ....................... 37
4.8 S dng 24-bit Audio CODEC .......................................... .............................................. 41

4.9 RS-232 Serial Port ............................................ .................................................. ............... 42
4.10 PS / 2 Serial Port ............................................ .................................................. .................... 42
4.11 Fast Ethernet iu khin Mng ............................................. ......................................... 43

4.12 TV Decoder ............................................... .................................................. ....................... 44
4.13 Thc hin mt b m ha truyn hnh .............................................. ................................................ 46
4.14 S dng USB Host v thit b ............................................ .................................................. 46
4.15 S dng IrDA ............................................... .................................................. ........................ 48
4.16 S dng SDRAM / SRAM / Flash ........................................... .................................................. 49
Chng 5 V d v cc cuc biu tnh nng cao ............................................ .......................... 54
5.1 Nh my Cu hnh DE2 .............................................. .................................................. 54
ii
Board DE2 Altera
5.2 TV Box din ............................................... .................................................. ..... 55

5.3 USB Paintbrush ............................................... .................................................. ................. 57
5.4 USB Device ............................................... .................................................. ....................... 59
5,5 Mt my Karaoke .............................................. .................................................. ........... 61

5,6 Gi Ethernet Gi / Nhn ............................................. ...................................... 62
5,7 SD Card Music Player .............................................. .................................................. ........ 64
5.8 m nhc tng hp trnh din .............................................. ....................................... 66
iii
DE2 Hng dn s dng
Chng 1
gi DE2
Cc gi phn mm DE2 cha tt c cc thnh phn cn thit s dng bng DE2 kt hp vi mt my tnh chy phn
mm Microsoft Windows.
1.1 Ni dung ng gi
Hnh 1.1 cho thy mt bc nh ca gi DE2.
Hnh 1.1. Cc DE2 ni dung gi.
1
DE2 Hng dn s dng
Cc gi phn mm DE2 bao gm:
DE2 bng
Cp USB cho FPGA lp trnh v kim sot
CD-ROM cha cc ti liu DE2 v ti liu h tr, bao gm hng dn s dng, tin ch Control Panel, thit k tham
kho v cc cuc biu tnh, Datasheets thit b, hng dn, v mt tp hp cc bi tp trong phng th nghim
CD-ROM cha Quartus Altera II Web Edition v Nios II Embedded Thit k Suit phn mm nh gi
Edition.
Ti gm su cao su (silicon) bao gm cho hin trn khn i board DE2. Ti cng cha mt s chn m rng, c th c s
dng to iu kin d dng hn thm d vi cc thit b kim tra cc tiu m rng I / O ca hi ng qun tr
ba nha r rng cho hi ng qun tr
9V DC treo tng cung cp in
1.2 Ban hi DE2

lp rp hin trn khn i bao gm cho hi ng qun tr DE2:
Lp rp mt cao su (silicon) ba, nh th hin trong hnh 1.2, cho mi trong s su ng ng trn bng DE2
Ba nha r rng cung cp thm s bo v, v c gn kt thng qua u hi ng qun tr bng cch s dng vit tt b
sung v inh vt
Hnh 1.2. Chn trong hi ng qun tr DE2.
2
DE2 Hng dn s dng
1.3 Tm s gip
Di y l cc a ch m bn c th nhn c s gip nu bn gp vn :
Altera Cng ty C phn 101
Innovation
San Jose, California, 95134 USA Email: university@altera.com
Terasic Technologies s 356, Sec. 1, keo E. Rd. Thnh
ph Jhubei, Hsinchu County, i Loan, 302 Email: support@terasic.com
Web: DE2.terasic.com
Arches Computing Unit 708-222 Spadina Ave
Toronto, Ontario, Canada M5T3A2 Email: DE2support@archescomputing.com
Web: DE2.archescomputing.com
Mt din n BBS (Bulletin Board System) cho hi ng qun tr DE2 c to theo a ch di y. Din n ny c ngha
l phc v nh l mt kho lu tr thng tin v bng DE2, v cung cp mt ngun lc thng qua ngi dng c th t
cu hi v chia s nhng v d thit k.
BBS din n: http://www.terasic.com/english/discuss.htm
3
DE2 Hng dn s dng
chng 2
Board DE2 Altera

Chng ny trnh by cc tnh nng v c im thit k ca Ban DE2.
2.1 Giao din v Linh kin

Mt bc nh ca hi ng qun tr DE2 c th hin trong hnh 2.1. N m t cch b tr ca hi ng qun tr v ch ra v tr ca
u ni v cc thnh phn ch cht.
Hnh 2.1. Cc DE2 bng.
Ban DE2 c nhiu tnh nng cho php ngi s dng thc hin mt lot cc mch thit k, t mch n gin cho cc
d n a phng tin khc nhau.
Cc phn cng sau y c cung cp trn bng DE2:
Altera Cyclone thit b II 2C35 FPGA
Altera thit b Cu hnh Serial - EPCS16

Blaster USB (trn tu) cho lp trnh v ngi s dng API kim sot; c hai JTAG v Active Serial (AS) ch lp
trnh c h tr
512-Kbyte SRAM
8 Mbyte SDRAM
4
DE2 Hng dn s dng
4 Mbyte b nh Flash (1 Mbyte trn mt s hi ng)
cm SD Card
4 cng tc nt nhn
18 cn gt
18 n LED s dng mu
9 n LED s dng mu xanh l cy
50-MHz dao ng v 27-MHz dao ng cho ngun ng h
24-bit audio CD-cht lng CODEC vi line-in, line-out, v micro-in jack cm

VGA DAC (10-bit tc cao gp ba ln DACs) vi u ni VGA-out
TV Decoder (NTSC / PAL) v kt ni TV-in

10/100 Ethernet Controller vi mt u ni
USB Host / Slave Controller vi USB loi A v u ni loi B
RS-232 thu pht v kt ni 9-pin
PS / 2 chut ni / bn phm
IrDA thu pht
Hai Headers 40-pin m rng vi bo v diode
Ngoi cc tnh nng phn cng, Ban DE2 c phn mm h tr cho cc giao din I / O tiu chun v mt c s bng iu khin
truy cp vo cc thnh phn khc nhau. Ngoi ra, phn mm c cung cp cho mt s cuc biu tnh minh ha cho kh
nng tin tin ca hi ng qun tr DE2.
s dng bng DE2, ngi dng phi lm quen vi phn mm Quartus II. Cc kin thc cn thit c th c
mua bng cch c cc hng dn Bt u vi DE2 Ban Altera v Quartus II Gii thiu ( m tn ti trong ba phin
bn da trn phng php nhp thit k s dng, c th l Verilog, VHDL hoc nhp s ). Nhng hng dn
c cung cp trong th mc
DE2_tutorials trn DE2 H thng CD-ROM i km vi hi ng qun tr DE2 v cng c th c tm thy trn cc trang web DE2
Altera.
2.2 S khi ca Ban DE2

Hnh 2.2 a ra s khi ca hi ng qun tr DE2. cung cp s linh hot ti a cho ngi s dng, tt c cc kt ni c thc
hin thng qua cc thit b Cyclone II FPGA. Do , ngi dng c th cu hnh FPGA thc hin bt k thit k h thng.
5
DE2 Hng dn s dng
Hnh 2.2. s khi ca hi ng qun tr DE2.
Sau y l thng tin chi tit hn v cc khi trong hnh 2.2:
Cyclone II 2C35 FPGA

33.216 Les
105 M4K RAM khi

483.840 tng s bit RAM
35 nhn nhng
4 PLLs
475 ngi s dng I / O pins
FineLine BGA gi 672-pin
thit b cu hnh ni tip v mch Blaster USB

thit b ni tip Cu hnh EPCS16 Altera
On-board Blaster USB lp trnh v ngi s dng API kim sot
JTAG v AS ch lp trnh c h tr
6
DE2 Hng dn s dng
SRAM
chip b nh 512-Kbyte Static RAM
T chc nh 256K x 16 bit
B nh b nh cho b vi x l Nios II v bi DE2 Control Panel
SDRAM
8 Mbyte chip b nh Rate c d liu ng b Dynamic RAM
T chc nh 1M x 16 bit x 4 ngn hng
B nh flash
4 Mbyte NOR b nh Flash (1 Mbyte trn mt s hi ng)
8-bit bus d liu
cm th SD
Cung cp ch SPI truy cp th nh SD
B nh nh cho b vi x l Nios II vi driver DE2 SD Card
cng tc nt nhn
4 cng tc nt nhn
Debounced bi mt mch trigger Schmitt
Thng thng cao; to ra mt xung hot ng thp khi chuyn i c nhn
cn gt
18 Toggle chuyn cho cc u vo ngi s dng
Mt chuyn i gy ra logic 0 khi trong XUNG (gn ra ca hi ng qun tr DE2) v tr v logic 1 khi v
tr UP
u vo ng h
50-MHz dao ng
27-MHz dao ng
SMA u vo ng h bn ngoi
7
DE2 Hng dn s dng
Audio codec
Wolfson WM8731 24-bit sigma-delta CODEC m thanh
u vo dng cp, sn lng dng cp, v microphone u vo
tn s ly mu: 8-96 KHz

ng dng cho my nghe nhc MP3 v my ghi, PDA, in thoi thng minh, my ghi m, vv
u ra VGA
S dng ADV7123 240-MHz ba 10-bit tc cao video DAC
Vi mt cao kt ni D-sub 15-pin
H tr ln n 1600 x 1200 100-Hz refresh rate
C th c s dng vi FPGA Cyclone II thc hin mt truyn m ha hiu sut cao
NTSC / PAL mch gii m truyn hnh
S dng ADV7181B a nh dng SDTV Video Decoder
H tr NTSC- (M, J, 4,43), PAL- (B / D / G / H / I / M / N), SECAM
Tch hp ba ADCs 54-MHz 9-bit

Xung nhp t mt a n 27-MHz dao ng u vo
H tr Composite Video (CVBS) jack RCA u vo.
H tr cc nh dng u ra k thut s (8-bit / 16-bit): ITU-R BT.656 YCrCb 4: 2: 2 u ra + HS, VS, v LNH VC
ng dng: ghi DVD, LCD TV, hp set-top, truyn hnh k thut s, thit b video xch tay
iu khin 10/100 Ethernet

MAC tch hp v PHY vi mt giao din x l chung
H tr cc ng dng 100Base-T v 10Base-T
H tr hot ng full-duplex lc 10 Mb / s v 100 Mb / s, vi tnh nng t ng MDIX
Hon ton ph hp vi 802.3u c im k thut IEEE
H tr IP / TCP / UDP checksum th h v kim tra

H tr ch back-pressure kim sot ch dng chy half-duplex
USB Host / Slave iu khin

Tun th y vi Universal Serial Bus Specification Rev. 2.0
H tr truyn d liu tc y v tc thp
H tr c USB v thit b
Hai cng USB (mt loi A cho mt my ch v mt loi B cho mt thit b)
Cung cp mt tc cao giao din song song vi hu ht cc b vi x l c sn; h tr Nios II vi mt trnh iu khin Terasic
s 8
DE2 Hng dn s dng
H tr Programmed I / O (PIO) v Direct Memory Access (DMA)
cng ni tip
Mt cng RS-232
Mt cng PS / 2
DB-9 ni ni tip cho cng RS-232

PS / 2 kt ni kt ni mt con chut PS2 hoc bn phm cho Ban DE2
IrDA thu pht

Cha 115,2 kb / s thu pht hng ngoi
32 mA LED li xe hin hnh
Tch hp EMI shield

IEC825-1 Class 1 mt an ton
u vo pht hin cnh
Hai tiu m rng 40-pin

72 Cyclone II I / O pins, cng nh 8 in v ng dy ni t, c a ra hai kt ni m rng 40-pin
tiu 40-pin c thit k chp nhn mt ribbon cp 40-pin chun c s dng cho cc a cng IDE
Diode v bo v in tr c cung cp
2.3 Power-up Ban DE2

Ban DE2 i km vi mt dng cu hnh bit ci t sn chng minh mt s tnh nng ca hi ng qun tr. dng bit ny cng cho php
ngi dng xem mt cch nhanh chng nu hi ng qun tr ang lm vic ng cch. Quyn lc-up hi ng qun tr thc hin cc bc
sau:
1. Kt ni cp USB c cung cp t my ch kt ni USB Blaster trn

cc DE2 bng. i vi thng tin lin lc gia cc my ch v hi ng qun tr DE2, n l cn thit ci t cc
phn mm Altera trnh iu khin USB Blaster. Nu trnh iu khin ny cha c ci t trn my ch, n c th
c ci t nh c gii thch trong hng dn Bt u vi DE2 Ban Altera. Hng dn ny c sn trn DE2 H
thng CD-ROM v t cc trang web Altera DE2.
2. Kt ni adapter 9V cho Ban DE2

3. Kt ni mt mn hnh VGA vo cng VGA trn bng DE2
4. Kt ni tai nghe vo cng audio Line-out trn bng DE2
5. Bt cng tc RUN / PROG trn cnh tri ca hi ng qun tr DE2 CHY v tr; cc
v tr PROG ch c s dng cho cc lp trnh AS Ch
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DE2 Hng dn s dng
6. Tt ngun bng cch nhn cng tc ON / OFF trn bng DE2
Ti thi im ny, bn nn quan st nh sau:
Tt c cc n LED dng ang nhp nhy
Tt c mn hnh 7-segment ang vng qua mt s t 0 n F
Cc chng trnh hin th LCD Cho mng bn n DE2 Altera Ban
Mn hnh VGA hin th hnh nh th hin trong hnh 2.3.

t SW17 cng tc bt tt n v tr XUNG; bn s nghe thy mt m thanh 1 kHz
t SW17 nt chuyn i n v tr UP v kt ni u ra ca mt my nghe nhc m thanh kt ni cng Line-in
trn bng DE2; trn tai nghe ca bn, bn nn nghe nhc chi t my nghe nhc m thanh (MP3, PC, iPod, hoc
tng t)
Bn cng c th kt ni mt micro vo Microphone-in kt ni trn bng DE2; ging ni ca bn s c trn ln vi m
nhc c chi t my nghe nhc m thanh
Hnh 2.3. Kt qu m hnh VGA mc nh.
Chng 3
10
DE2 Hng dn s dng
DE2 Control Panel

Ban DE2 i km vi mt c s Control Panel cho php ngi dng truy cp cc thnh phn khc nhau trn bng thng
qua kt ni USB t mt my ch. Chng ny u tin trnh by mt s chc nng c bn ca Control Panel, sau m
t cu trc ca n dng s khi, v cui cng m t kh nng ca mnh.
3.1 Ci t Control Panel
chy cc ng dng Control Panel, n l u tin cn thit cu hnh mt mch tng ng trong Cyclone II
FPGA. Ny c thc hin bng cch ti v cc tp tin cu hnh DE2_USB_API.sof vo FPGA. Th tc ti c m t
trong Phn 4.1.
Ngoi cc DE2_USB_API.sof tp tin, n l cn thit thc thi trn my ch chng trnh DE2_control_panel.exe. C
hai file c sn trn DE2 H thng CD-ROM
i km vi hi ng qun tr DE2, trong th mc DE2_control_panel. Tt nhin, nhng tp tin ny c th c ci t vo
mt s v tr khc trn h thng my tnh ca bn.
kch hot Control Panel, thc hin cc bc sau:

1. Kt ni cp USB km theo cng Blaster USB, kt ni ngun in 9V,
v bt cng tc ngun ON
2. t cng tc RUN / PROG n v tr RUN
3. Khi ng phn mm Quartus II
4. La chn Cng c> Lp trnh vin t c ca s trong hnh 3.1. Bm vo Thm tp tin v trong
ca s pop-up xut hin, chn cc DE2_USB_API.sof tp tin. Tip theo, nhn vo

Chng trnh / Configure hp m kt qu trong hnh nh hin th trong hnh. By gi, nhp
Khi u ti v cc tp tin cu hnh vo FPGA.

5. Bt u thc thi DE2_control_panel.exe trn my ch. Ngi dng Control Panel
giao din th hin trong hnh 3.2 s xut hin.
6. M cng USB bng cch nhn M> Open Port 0 USB. Cc DE2 Control Panel
ng dng s lit k tt c cc cng USB kt ni vi bo mch DE2. Cc DE2 Control Panel c th kim sot ln n 4
DE2 bng bng cch s dng cc lin kt USB. Control Panel s chim cng USB cho n khi bn ng m cng; bn
khng th s dng Quartus II ti v mt tp tin cu hnh vo FPGA cho n khi bn ng cng USB.
7. Control Panel gi y sn sng s dng; th nghim bng cch thit lp gi tr ca mt s 7-segment
hin th v quan st kt qu trn bng DE2.
11
DE2 Hng dn s dng
Hnh 3.1. Quartus II Programmer ca s.
Hnh 3.2. Cc DE2 Control Panel.
Khi nim v DE2 Control Panel c minh ha trong hnh 3.3. IP thc hin chc nng kim sot c thc hin
trong cc thit b FPGA. N giao tip vi ca s Control Panel, m ang hot ng trn my ch, thng qua cc
lin kt USB Blaster. Giao din ha c s dng ra lnh cho mch iu khin. IP cung cp x l tt c cc
yu cu v thc hin truyn d liu gia my tnh v bng DE2.
12
DE2 Hng dn s dng
Hnh 3.3. Khi nim DE2 Control Panel.
Cc DE2 Control Panel c th c s dng thay i cc gi tr hin th trn LED 7 on, sng ln n LED, ni chuyn vi cc
bn phm PS / 2, c / vit SRAM, b nh Flash v SDRAM, ti mt mu hnh nh hin th nh u ra VGA , ti nhc vo b
nh v pht nhc qua DAC m thanh. Tnh nng c / vit mt byte hoc ton b tp tin t / ti b nh flash cho php ngi s
dng pht trin cc ng dng a phng tin (Flash Audio Player, Flash Picture Viewer) m khng cn lo lng v vic lm th
no xy dng mt b nh Flash Programmer.
3.2 Kim sot n LED, Mn hnh 7-Segment v Mn hnh LCD
Mt chc nng n gin ca Control Panel l cho php thit lp cc gi tr hin th trn n LED, LED 7 on, v cc k
t hin th LCD.
Trong ca s hin trong hnh 3.2, cc gi tr c hin th bng cc LED 7 on (c t tn HEX 7-0) c th
c nhp vo cc tng ng v hin th bng cch nhn B
nt. Mt bn phm kt ni vi cng PS / 2 c th c s dng g vn bn s c hin th trn mn hnh LCD.
chn LED & LCD tab dn n ca s trong hnh 3.4. y, bn c th tt n LED c nhn trn bng cch chn
chng v nhn vo B nt. Vn bn c th c ghi vo mn hnh LCD bng cch g n trong hp LCD v nhn
tng ng B nt.
Kh nng thit lp cc gi tr ty vo cc thit b hin th n gin l khng cn thit trong hot ng thit k in hnh. Tuy nhin, n
mang li cho ngi s dng mt c ch n gin xc minh rng nhng thit b ny ang hot ng mt cch chnh xc trong trng hp
s c b nghi ng. Do , n c th c s dng cho mc ch g ri.
13
DE2 Hng dn s dng
Hnh 3.4. iu khin n LED v mn hnh LCD.
3.3 SDRAM Controller / SRAM v Lp trnh vin
Control Panel c th c s dng vit / c d liu n / t cc chip SDRAM v SRAM trn bng DE2. Chng ti s m t cch
cc SDRAM c th c truy cp; phng php tng t c s dng truy cp vo SRAM. Nhp vo tab SDRAM t c
ca s trong hnh 3.5.
Hnh 3.5. Truy cp vo SDRAM.
14
DE2 Hng dn s dng
Mt t 16-bit c th c vit vo SDRAM bng cch nhp a ch ca v tr mong mun, xc nh d liu c

ghi, v nhn vit nt. Ni dung ca a im c th c c bng cch nhn c nt. Hnh 3.5 m t kt qu ca
vn bn cho 6CA gi tr thp lc phn vo v tr 200, tip theo l c cng mt v tr.
Write chc nng tun t ca Control Panel c s dng ghi cc ni dung ca mt tp tin vo SDRAM nh sau:
1. Xc nh a ch bt u trong a ch nh ci hp.
2. Xc nh s lng byte c vit trong Chiu di ci hp. Nu ton b tp tin l c

np, sau mt du kim c th c t trong tp tin di hp thay v a ra s byte.
3. bt u ghi d liu, bm vo Vit mt File SDRAM nt.

4. Khi Control Panel p ng vi cc tiu chun ca Windows hp thoi yu cu cc
tp tin ngun, xc nh cc tp tin mong mun theo cch thng thng.
Control Panel cng h tr ti cc tp tin vi mt. hex s m rng. File vi a. hex phn m rng l cc tp tin vn bn ASCII m
xc nh gi tr b nh s dng cc k t ASCII i din cho cc gi tr thp lc phn. V d, mt file cha cc dng
0123456789ABCDEF
nh ngha bn gi tr 16-bit: 0123, 4567, 89AB, CDEF. Nhng gi tr ny s c np lin tip vo b nh.
Cc tun t c chc nng c s dng c cc ni dung ca SDRAM v t chng vo mt tp tin nh sau:
1. Xc nh a ch bt u trong a ch nh ci hp.
2. Xc nh s lng byte c sao chp vo tp tin trong Chiu di ci hp. Nu ton b

ni dung ca SDRAM ang c sao chp (trong bao gm tt c 8 Mbytes), sau t mt du kim trong ton b
SDRAM ci hp.
3. nhn Ti SDRAM ni dung cho mt tp tin nt.

tp tin ch, ch nh cc tp tin mong mun theo cch thng thng.
15
DE2 Hng dn s dng
3.4 Flash Memory Programmer
Control Panel c th c s dng vit / c d liu n / t cc chip b nh flash trn bng DE2. N c th c s dng :
Xa ton b b nh flash
Vit mt byte vo b nh
c mt byte t b nh
Vit mt tp tin nh phn vo b nh
Ti cc ni dung ca b nh flash vo mt tp tin
Lu cc c im sau y ca b nh Flash:
Chip b nh flash c t chc nh 4 M (hoc 1 M trn mt s hi ng) x 8 bit.
Bn phi xa ton b b nh Flash trc khi bn c th vit vo . (Hy nhn bit rng s ln mt b nh Flash c
th c xo hon ton b hn ch.)
Thi gian cn thit xa ton b b nh Flash l khong 20 giy. ng ng DE2 Control Panel gia
cc hot ng.
m ca s iu khin b nh Flash, th hin trong hnh 3.6, chn tab FLASH trong Control Panel.
Hnh 3.6. Flash ca s iu khin b nh.
Mt byte d liu c th c ghi vo mt v tr ngu nhin trn chip Flash bng cch sau:
1. Click vo Chip Erase nt. Nt v tiu khung ca s s nhc bn

ch cho n khi hot ng kt thc, mt khong 20 giy.
16
DE2 Hng dn s dng
2. Nhp a ch mong mun vo a ch nh hp v cc d liu byte vo wDATA ci hp.
Sau , bm vo vit nt.
c mt byte d liu t mt v tr ngu nhin, nhp a ch ca a im v nhn vo

c nt. Cc rdata hp s hin th d liu c li t a ch c th.
Write chc nng tun t c s dng ti mt tp tin vo chip Flash bng cch sau:
1. Xc nh a ch bt u v di ca d liu (tnh theo byte) c ghi vo Flash

k c. Bn c th click vo tp tin di hp kim cho bit rng bn mun ti ton b tp tin.
2. Click vo Vit mt tp tin sang Flash nt kch hot qu trnh vit.

tp tin ngun, xc nh cc tp tin mong mun theo cch thng thng.
Cc tun t c chc nng c s dng c d liu c lu tr trong b nh flash v ghi d liu ny vo mt tp tin nh sau:
1. Xc nh a ch bt u v di ca d liu (tnh theo byte) c c t Flash

k c. Bn c th click vo ton b flash hp kim cho bit rng bn mun sao chp ton b ni dung ca b
nh flash vo mt tp tin c th.
2. Click vo Ti flash ni dung cho mt tp tin nt kch hot qu trnh c.

tp tin ch, ch nh cc tp tin mong mun theo cch thng thng.
3.5 Cu trc tng th ca DE2 Control Panel

C s DE2 Control Panel giao tip vi mt mch c thuyt minh trong Cyclone II FPGA. mch ny c quy nh ti
Verilog m, m lm cho n c th cho mt ngi s dng c kin thc thay i cc chc nng ca Control Panel.
M ny c t bn trong DE2_demonstrations
th mc trn DE2 H thng CD-ROM.
chy Control Panel, ngi s dng u tin phi thit lp n nh c gii thch trong Phn 3.1. Hnh 3.7 m t cu trc
ca Control Panel. Mi thit b u vo / u ra c iu khin bi mt b iu khin khi to trong chip FPGA. Cc giao
tip vi my tnh c thc hin thng qua cc lin kt USB Blaster. Mt mch lnh iu khin thng dch cc lnh nhn
c t my tnh v thc hin cc hnh ng thch hp. Cc SDRAM, SRAM, b iu khin v Flash Memory c ba cng
khng ng b s dng c th la chn ngoi cc cng my ch cung cp mt lin kt vi cc b iu khin Command.
Mi lin h gia cc VGA DAC Controller v nh FPGA cho php hin th cc hnh nh mc nh hin th trn bn tri ca
hnh, m c lu tr trong mt khi M4K trong Cyclone
17
DE2 Hng dn s dng
Chip II. Mi lin h gia cc m thanh DAC iu khin v mt bng tra cu trong FPGA c s dng to ra mt tn hiu kim tra m
thanh ca 1 kHz.
cho php ngi dng thc hin v kim tra li IP ca h (vit bng Verilog) m khng yu cu h thc hin phc tp phn mm
iu khin API / My ch v b nh (SRAM / SDRAM / Flash) iu khin, chng ti cung cp mt mi trng kim sot tch hp bao
gm mt b iu khin phn mm trong C ++, mt b iu khin lnh USB, v mt a cng iu khin SRAM / SDRAM / flash.
Hnh 3.7. S khi DE2 Control Panel.
Ngi dng c th kt ni mch ca thit k ring ca h mt trong nhng cng ti khon ca / SDRAM / b iu khin flash SRAM.
Sau , h c th ti d liu nh phn vo SRAM / SDRAM / Flash. Mt khi cc d liu s c ti v vi SDRAM / Flash, ngi dng
c th cu hnh cc b iu khin b nh mch ca h c th c / ghi SDRAM / Flash thng qua cng kt ni ti khon.
18
DE2 Hng dn s dng
3.6 CNG C - Multi-Port SRAM / SDRAM / Flash khin

Cc trang cng c ca Control Panel GUI cho php la chn cc cng dng. Chng ti s minh ha mt qu trnh in hnh
bng cch thc hin mt Flash Music Player. Cc d liu m nhc c np vo b nh Flash. S dng Cng 1 trong Controller
Flash c s dng gi d liu nhc vi m thanh DAC iu khin v do vi jack m thanh u ra. Bn c th thc hin
ng dng ny nh sau:
1. Xa b nh Flash (nh gii thch trong Phn 3.4). Sau , vit mt tp tin nhc vo
B nh flash. Bn c th s dng cc tp tin music.wav trong th mc DE2_demonstrations \ music
trn DE2 H thng CD-ROM.

2. Trong DE2 Control Panel, chn tab c t c ca s trong hnh 3.8.
Hnh 3.8. CNG C ca s ca DE2 Control Panel.
3. Chn cng khng ng b 1 cho Flash Multiplexer v sau nhp vo cu hnh

nt kch hot cc cng. Bn cn phi bm vo nt Configure cho php cc kt ni t b nh Flash
Cng Asynchronous 1 ca Controller Flash (ch ra trong hnh 3.7).
4. t Toggle tc SW1 v SW0 OFF (DOWN v tr) v ON (v tr UP),

tng ng.
5. Cm tai nghe hoc loa vo jack m thanh u ra v bn nn nghe nhc
chi t cc mch m thanh DAC.
6. Lu rng khng ng b Cng 1 c kt ni vi phn m thanh DAC, nh th hin trong hnh
3.7. Khi bn chn ng b Cng 1 v nhp vo nt Configure, Audio DAC iu khin s giao tip vi b
nh flash trc tip. Trong v d ca chng ti,
19
DE2 Hng dn s dng
AUDIO_DAC Verilog m-un nh ngha mt mch m c ni dung ca b nh Flash v gi n n chip m

thanh bn ngoi.
3.7 Display Control VGA
Control Panel cung cp mt cng c vi cc IP c lin quan cho php ngi dng hin th mt hnh nh thng qua cng u ra VGA. minh
ha cho tnh nng ny, chng ta s thy lm th no mt hnh nh c th c hin th trn mt mn hnh VGA. Thc hin cc bc sau hin
th mt hnh nh mc nh:
Chn tab VGA trong Control Panel t c ca s trong hnh 3.9.
Hnh 3.9. hnh nh hin th v con tr iu khin bi cc thanh cun
Hy chc chn rng cc hp kim hnh nh mc nh v con tr Enable c kim tra.
Kt ni mt mn hnh VGA cho Ban DE2 v bn s thy trn mn hnh hnh nh mc nh th hin trong hnh 3.9.
Hnh nh bao gm mt con tr c th c kim sot bng phng tin ca X / Y-trc cc thanh cun trn DE2
Control Panel.
Nhng hnh nh trong hnh 3.9 c lu tr trong mt khi b nh M4K trong Cyclone II FPGA. N c np vo khi M4K theo nh
dng MIF / Hex (Intel) trong giai on cu hnh dng bit mc nh. Chng ti s tip theo m t lm th no bn c th hin th hnh
nh khc v s dng hnh nh ca ring bn to ra cc m hnh d liu nh phn c th c hin th trn mn hnh VGA.
hnh nh khc c cung cp trong tp tin picture.dat trong th mc DE2_demonstrations \ hnh nh trn
DE2 H thng CD-ROM. Bn c th hin th hnh nh ny nh sau:
chn SRAM trang ca Control Panel v ti cc tp tin picture.dat vo SRAM.

20
DE2 Hng dn s dng
chn CNG C trang v chn khng ng b 1 cho SRAM multiplexer cng nh trong hnh 3.10. Click
vo cu hnh nt kch hot cc thit lp a cng.
Hnh 3.10. S dng ng b Cng 1 truy cp d liu hnh nh trong SRAM.
FPGA hin nay c cu hnh nh c ch ra trong hnh 3.11.
chn VGA trang v b chn hp kim Hnh nh mc nh.

Mn hnh VGA s hin th picture.dat hnh nh t SRAM, nh m t trong hnh 3.12. Bn c th tt con tr
bng cch b chn con tr Enable hp kim.
Hnh 3.11. Multi-Cng iu khin cu hnh hin th mt hnh nh t SRAM.
21
DE2 Hng dn s dng
Hnh 3.12. Mt hnh nh hin th.
Bn c th hin th bt k file nh bng cch ti n vo chip SRAM hoc vo mt khi b nh M4K trong chip Cyclone II. iu ny i
hi to ra mt tp tin bitmap, trong c th c thc hin nh sau:
1. Ti hnh nh mong mun tr thnh mt cng c x l hnh nh, chng hn nh Corel PhotoPaint.
2. Resample nh gc c phn gii 640 x 480. Lu hnh nh sa i trong

cc nh dng Windows Bitmap.
3. Thi hnh DE2_control_panel \ ImgConv.exe, mt cng c chuyn i hnh nh pht trin cho
DE2 bng, t c ca s trong hnh 3.13.
4. Click vo m Bitmap nt v chn 640 x 480 Grayscale nh cho

chuyn i.
5. Khi x l cc tp tin hon tt, nhn vo Lu d liu th nt v mt tp tin

tn Raw_Data_Gray.dat s c to ra v lu tr trong cng th mc vi file nh gc. Bn c th thay
i tin t tn file t D liu th tn khc bng cch thay i lnh vc File Name trong ca s hin th.
6. Raw_Data_Gray.dat l d liu th c th c ti trc tip vo SRAM trn

DE2 bng v hin th trn mn hnh VGA s dng IP iu khin VGA c m t trong DE2_USB_API d
n.
7. Cc ImgConv cng c cng s to ra Raw_Data_BW.dat ( v n tng ng TXT
nh dng) cho phin bn mu en v trng ca hnh nh - ngng nh gi mc mu en hoc trng c xc
nh trong Threshold BW.
22
DE2 Hng dn s dng
Hnh 3.13. Ca s chuyn i hnh nh.
Ngun hnh nh R / G / B band B&W sn lng Kt qu
Lc Threshold (640x480)
Lc
Mu Hnh R / G / B N/A Raw_Data_Gray
Mu Hnh R / G / B BW Threshold Raw_Data_BW +

(khng bt buc) Raw_Data_BW.txt
grayscale N/A N/A Raw_Data_Gray
nh
grayscale N/A BW Threshold Raw_Data_BW +
nh Raw_Data_BW.txt
Lu : Raw_Data_BW.txt c s dng in vo cc nh dng MIF / Intel Hex cho M4K SRAM
23
DE2 Hng dn s dng
Chng 4
S dng Ban DE2

Chng ny a ra cc hng dn cho vic s dng bng DE2 v m t tng loi thit b I / O ca n.
4.1 Cu hnh FPGA Cyclone II

Th tc ti v mt mch t mt my ch cho Ban DE2 c m t trong hng dn Quartus II Gii thiu. Hng dn ny
c tm thy trong cc DE2_tutorials th mc trn DE2 H thng CD-ROM, v n cng c sn trn cc trang web Altera
DE2. Ngi dng c khuyn khch c cc hng dn u tin, v iu tr cc thng tin di y tham kho
ngn.
Ban DE2 cha mt chip EEPROM ni tip lu tr d liu cu hnh cho ng c Cyclone II FPGA. d liu cu hnh ny
c t ng np t chip EEPROM vo FPGA mi sc mnh thi gian c p dng cho hi ng qun tr. S dng
phn mm Quartus II, ngi ta c th lp trnh li FPGA bt c lc no, v n cng c th thay i d liu non-volatile
c lu tr trong chip EEPROM ni tip. C hai loi phng php lp trnh c m t di y.
1. JTAG lp trnh: Trong phng php ny ca chng trnh, c t tn theo cc tiu chun IEEE Chung
Test Action Group, dng cu hnh bit c ti v trc tip vo Cyclone II FPGA. FPGA s gi li cu hnh
ny cng lu cng in c p dng cho hi ng qun tr; cu hnh b mt khi ngun c tt.
2. NH lp trnh: Trong phng php ny, c gi l hot ng ni tip lp trnh, cc bit cu hnh
lung c ti xung vo chip EEPROM ni tip Altera EPCS16. N cung cp lu tr non-volatile ca

dng bit, do thng tin c gi li ngay c khi vic cp in cho hi ng qun tr DE2 b tt. Khi
quyn lc ca hi ng qun tr c bt, d liu cu hnh trong thit b EPCS16 c t ng np vo
Cyclone II FPGA.
Cc phn di y m t cc bc s dng thc hin c hai JTAG v AS lp trnh. i vi c hai phng php
bng DE2 c kt ni vi mt my ch thng qua mt cp USB. S dng kt ni ny, hi ng qun tr s c
xc nh bi cc my ch nh mt Altera Blaster USB thit b. Qu trnh ci t trn my ch iu khin thit b phn
mm cn thit giao tip vi cc Blaster USB c m t trong ti liu ny Bt u vi DE2 Ban Altera. Hng dn
ny c sn trn DE2 H thng CD-ROM v t cc trang web Altera DE2.
24
DE2 Hng dn s dng
Cu hnh FPGA trong JTAG Ch
Hnh 4.1 minh ha cc thit lp cu hnh JTAG. ti v mt dng cu hnh cht vo Cyclone II FPGA, thc hin
cc bc sau:
m bo in c p dng cho hi ng qun tr DE2
Kt ni cp USB km vi cng USB Blaster trn bng DE2 (xem Hnh 2.1)
Cu hnh cc mch lp trnh JTAG bng cch thit lp chuyn i RUN / PROG ( pha bn tri ca hi ng qun tr) n
v tr RUN.
FPGA by gi c th c lp trnh bng cch s dng cc m-un Quartus II Programmer chn mt tp tin cu hnh
dng cht vi. sof phn m rng tn tp tin
Hnh 4.1. n cu hnh JTAG.
Cu hnh EPCS16 trong ch AS
Hnh 4.2 m t cu hnh AS thit lp. ti v mt dng cu hnh cht vo thit b EPCS16 serial EEPROM, thc
hin cc bc sau:
m bo in c p dng cho hi ng qun tr DE2
Kt ni cp USB km vi cng USB Blaster trn bng DE2 (xem Hnh 2.1)
Cu hnh cc mch lp trnh JTAG bng cch thit lp chuyn i RUN / PROG ( pha bn tri ca hi ng qun tr) n
v tr PROG.
Chip EPCS16 by gi c th c lp trnh bng cch s dng cc m-un Quartus II Programmer chn mt tp tin cu
hnh dng cht vi. pof phn m rng tn tp tin
Mt khi cc hot ng lp trnh xong, t cng tc RUN / PROG tr li v tr RUN v sau thit lp li hi
ng qun tr bng cch xoay in tt v tr li; hnh ng ny gy ra cc d liu cu hnh mi trong thit
b EPCS16 c np vo chip FPGA.
25
DE2 Hng dn s dng
Hnh 4.2. n cu hnh AS.
Ngoi vic s dng n cho JTAG v lp trnh AS, cng USB Blaster trn bng DE2 cng c th c s dng kim sot mt
s tnh nng ca hi ng qun tr t xa t mt my ch. Thng tin chi tit m t phng php ny s dng cng USB Blaster
c nu trong Chng 3.
4.2 S dng n LED v chuyn mch
Ban DE2 cung cp bn cng tc nt nhn. Mi mt cng tc c debounced s dng mt mch Schmitt Trigger, nh
c ch ra trong hnh 4.3. Bn u ra gi KEY0, ..., KEY3 ca thit b Schmitt trigger c kt ni trc tip n Cyclone II
FPGA. Mi switch cung cp mt mc logic cao (3,3 volt) khi n khng c nhn, v cung cp mt mc logic thp (0 volt)
khi chn nn. K t khi cng tc nt nhn c debounced, chng thch hp s dng nh ng h hoc thit lp li cc
u vo trong mt mch.
Hnh 4.3. Chuyn debouncing.
Ngoi ra cn c cng tc bt tt 18 (thanh trt) trn bng DE2. Nhng cng tc khng debounced, v nhm mc ch
s dng nh u vo d liu cp nhy cm vi mt mch. Mi switch c kt ni trc tip n mt pin trn Cyclone II
FPGA. Khi mt cng tc v tr XUNG (gn ra ca hi ng qun tr) n cung cp mt mc logic thp (0 volt) cho FPGA,
v khi chuyn i l v tr UP n cung cp mt mc logic cao (3,3 volt) .
26
DE2 Hng dn s dng
C 27 n LED s dng iu khin trn bng DE2. Mi tm n LED c t pha trn 18 cn gt, v tm
n LED mu xanh l cy c tm thy trn thit b chuyn mch pushbutton (9 th xanh LED l gia ca mn hnh
7-segment). Mi LED c iu khin trc tip bi mt pin trn FPGA Cyclone II; li xe pin lin quan n mt mc
logic cao ln lt cc LED trn, v li xe pin thp bin n i. Mt s cho thy pushbutton v bt tt cng tc c
a ra trong hnh 4.4. Mt s cho thy cc mch LED xut hin trong hnh 4.5.
Mt danh sch cc tn pin trn FPGA Cyclone II c kt ni vi cn gt c a ra trong Bng 4.1. Tng t nh vy, cc chn
s dng kt ni vi thit b chuyn mch pushbutton v n LED c hin th trong bng 4.2 v 4.3, tng ng.
Hnh 4.4. S ca cc pushbutton v bt tt cng tc.
27
DE2 Hng dn s dng
Hnh 4.5. S ca cc n LED.
Tn tn hiu FPGA Pin s S miu t
SW [0] PIN_N25 Chuyn i Chuyn [0]
SW [2] PIN_P25 Chuyn i Chuyn [2]
SW [3] PIN_AE14 Chuyn i Chuyn [3]
SW [4] PIN_AF14 Chuyn i Chuyn [4]
SW [5] PIN_AD13 Chuyn i Chuyn [5]
SW [6] PIN_AC13 Chuyn i Chuyn [6]
SW [7] PIN_C13 Chuyn i Chuyn [7]
SW [8] PIN_B13 Chuyn i Chuyn [8]
SW [9] PIN_A13 Chuyn i Chuyn [9]
SW [13] PIN_T7 Chuyn i Chuyn [13]
SW [14] PIN_U3 Chuyn i Chuyn [14]
SW [15] PIN_U4 Chuyn i Chuyn [15]
SW [16] PIN_V1 Chuyn i Chuyn [16]
SW [17] PIN_V2 Chuyn i Chuyn [17]
Bng 4.1. bi tp pin cho cn gt.

28
DE2 Hng dn s dng
KEY [0] PIN_G26 Nt [0]
KEY [1] PIN_N23 Nt [1]
KEY [2] PIN_P23 Nt [2]
KEY [3] PIN_W26 Nt [3]
Bng 4.2. bi tp pin cho thit b chuyn mch pushbutton.
LEDR [0] PIN_AE23 LED [0]
LEDR [1] PIN_AF23 LED [1]
LEDR [2] PIN_AB21 LED [2]
LEDR [3] PIN_AC22 LED [3]
LEDR [4] PIN_AD22 LED [4]
LEDR [8] PIN_AA14 LED [8]
LEDR [9] PIN_Y13 LED [9]
LEDR [10] PIN_AA13 LED [10]
LEDR [14] PIN_AF13 LED [14]
LEDG [0] PIN_AE22 LED mu xanh l cy [0]
LEDG [1] PIN_AF22 LED mu xanh l cy [1]
LEDG [2] PIN_W19 LED mu xanh l cy [2]
LEDG [3] PIN_V18 LED mu xanh l cy [3]
LEDG [4] PIN_U18 LED mu xanh l cy [4]
LEDG [5] PIN_U17 LED mu xanh l cy [5]
LEDG [6] PIN_AA20 LED mu xanh l cy [6]
LEDG [7] PIN_Y18 LED mu xanh l cy [7]
LEDG [8] PIN_Y12 LED mu xanh l cy [8]
Bng 4.3. bi tp pin cho n LED.
29
DE2 Hng dn s dng
4.3 S dng Mn hnh 7-segment
Ban DE2 c tm LED 7 on. Nhng mn hnh c b tr thnh hai cp v mt nhm gm bn ngi, vi mc
ch hin th s kch c khc nhau. Nh nu trong s hnh 4.6, by on c kt ni vi cc chn trn
Cyclone II FPGA. p dng mt mc logic thp cho mt b phn lm cho n sng ln, v p dng mt mc logic
cao bin n i.
Mi on trong mt mn hnh c xc nh bi mt ch s 0-6, vi cc v tr c a ra trong Hnh
4.7. Lu rng cc du chm trong mi mn hnh l khng c lin quan v khng th c s dng. Bng 4.4 cho thy s phn cng ca
FPGA pins hin th 7-segment.
Hnh 4.6. S ca cc LED 7 on.
Hnh 4.7. V tr v ch s ca tng phn on trong mt mn hnh 7-segment.
30
DE2 Hng dn s dng
HEX0 [0] PIN_AF10 By Segment Digit 0 [0]
HEX0 [1] PIN_AB12 By Segment Digit 0 [1]
HEX0 [2] PIN_AC12 By Segment Digit 0 [2]
HEX0 [3] PIN_AD11 By Segment Digit 0 [3]
HEX0 [4] PIN_AE11 By Segment Digit 0 [4]
HEX0 [5] PIN_V14 By Segment Digit 0 [5]
Hex1 [0] PIN_V20 By Segment Digit 1 [0]
Hex1 [1] PIN_V21 By Segment Digit 1 [1]
Hex1 [2] PIN_W21 By Segment Digit 1 [2]
Hex1 [3] PIN_Y22 By Segment Digit 1 [3]
Hex1 [4] PIN_AA24 By Segment Digit 1 [4]
Hex1 [6] PIN_AB24 By Segment Digit 1 [6]
HEX2 [6] PIN_Y24 By Segment Digit 2 [6]
Hex3 [5] PIN_U22 By Segment Digit 3 [5]
Hex3 [6] PIN_W24 By Segment Digit 3 [6]
HEX4 [0] PIN_U9 By Segment Digit 4 [0]
HEX4 [3] PIN_T4 By Segment Digit 4 [3]
HEX4 [4] PIN_R7 By Segment Digit 4 [4]
31
DE2 Hng dn s dng
HEX5 [1] PIN_P6 By Segment Digit 5 [1]
HEX6 [3] PIN_M2 By Segment Digit 6 [3]
HEX7 [0] PIN_L3 By Segment Digit 7 [0]
HEX7 [6] PIN_N9 By Segment Digit 7 [6]
Bng 4.4. bi tp pin cho LED 7 on.
4.4 ng h u vo
Ban DE2 bao gm hai dao ng sn xut 27 MHz v 50 MHz tn hiu ng h. Hi ng qun tr cng bao gm mt u ni SMA
c th c s dng kt ni mt ngun ng h bn ngoi hi ng qun tr. Cc s ca mch ng h c hin th
trong hnh 4.8, v cc bi tp lin quan n pin xut hin trong Bng 4.5.
32
DE2 Hng dn s dng
Hnh 4.8. S ca mch ng h.
CLOCK_27 PIN_D13 27 MHz u vo ng h
CLOCK_50 PIN_N2 50 MHz u vo ng h
EXT_CLOCK PIN_P26 Bn ngoi (SMA) u vo ng h
Bng 4.5. bi tp pin cho cc u vo ng h.
4.5 S dng cc module LCD
Cc module LCD sn cc phng ch v c th c dng hin th vn bn bng cch gi lnh thch hp vi b iu
khin mn hnh, c gi l HD44780. Thng tin chi tit cho vic s dng mn hnh c sn trong datasheet ca n, c th
c tm thy trn trang web ca nh sn xut, v t Bng dliu th mc trn DE2 H thng CD-ROM. Mt s ca cc
module LCD hin th cc kt ni n Cyclone II FPGA c a ra trong hnh 4.9. Cc bi tp lin quan n pin xut hin
trong Bng 4.6.
33
DE2 Hng dn s dng
Hnh 4.9. S ca cc m-un mn hnh LCD.
LCD_DATA [0] PIN_J1 D liu LCD [0]
LCD_DATA [2] PIN_H1 D liu LCD [2]
LCD_RW PIN_K4 LCD c / Vit Chn, 0 = Write, 1 = c
LCD_EN PIN_K3 LCD Kch hot
LCD_RS PIN_K1 LCD Command / d liu Chn, 0 = Command, 1 = D liu
LCD_ON PIN_L4 LCD Power ON / OFF
LCD_BLON PIN_K2 LCD Tr li Light ON / OFF
Bng 4.6. Pin bi tp cho cc m-un mn hnh LCD.
34
DE2 Hng dn s dng
4.6 S dng Header m rng

Ban DE2 cung cp hai tiu m rng 40-pin. Mi tiu kt ni trc tip n 36 chn trn Cyclone II FPGA, v cng
cung cp DC + 5V (VCC5), DC + 3.3V (VCC33), v hai chn GND. Hnh 4.10 cho thy s c lin quan. Mi pin trn
cc tiu m rng l kt ni vi hai it v mt in tr m cung cp bo v t in p cao v thp. Con s ny cho
thy cc mch bo v ch c bn chn trn mi tiu cho, nhng mch ny c bao gm cho tt c 72 chn d
liu. Bng 4.7 cung cp cho cc bi tp pin.
Hnh 4.10. S ca cc tiu m rng.
GPIO_0 [0] PIN_D25 GPIO kt ni 0 [0]
GPIO_0 [1] PIN_J22 GPIO kt ni 0 [1]
GPIO_0 [2] PIN_E26 GPIO kt ni 0 [2]
GPIO_0 [3] PIN_E25 GPIO kt ni 0 [3]
GPIO_0 [4] PIN_F24 GPIO kt ni 0 [4]
35
DE2 Hng dn s dng
GPIO_0 [10] PIN_N18 GPIO kt ni 0 [10]
GPIO_0 [11] PIN_P18 GPIO kt ni 0 [11]
GPIO_0 [12] PIN_G23 GPIO kt ni 0 [12]
GPIO_0 [14] PIN_K22 GPIO kt ni 0 [14]
GPIO_0 [16] PIN_H23 GPIO kt ni 0 [16]
GPIO_0 [28] PIN_L21 GPIO kt ni 0 [28]
GPIO_1 [0] PIN_K25 GPIO Connection 1 [0]
GPIO_1 [1] PIN_K26 GPIO Connection 1 [1]
GPIO_1 [2] PIN_M22 GPIO Connection 1 [2]
GPIO_1 [6] PIN_N20 GPIO Connection 1 [6]
GPIO_1 [10] PIN_N24 GPIO Connection 1 [10]
36
DE2 Hng dn s dng
GPIO_1 [11] PIN_P24 GPIO Connection 1 [11]
GPIO_1 [12] PIN_R25 GPIO Connection 1 [12]
GPIO_1 [15] PIN_T22 GPIO Connection 1 [15]
GPIO_1 [22] PIN_U26 GPIO Connection 1 [22]
GPIO_1 [30] PIN_V26 GPIO Connection 1 [30]
GPIO_1 [34] PIN_W25 GPIO Connection 1 [34]
GPIO_1 [35] PIN_W23 GPIO Connection 1 [35]
Bng 4.7. bi tp pin cho cc tiu m rng.
4.7 S dng VGA
Ban DE2 bao gm mt kt ni D-SUB 16 pin cho u ra VGA. Cc tn hiu ng b VGA c cung cp trc tip t
Cyclone II FPGA, v Analog Devices ADV7123 ba 10-bit tc cao video DAC c s dng sn xut cc tn hiu d
liu analog (, xanh l cy, v mu xanh). Cc s lin quan c a ra trong hnh 4.11 v c th h tr phn gii
ln n 1600 x 1200 pixel, mc 100 MHz.
37
DE2 Hng dn s dng
Hnh 4.11. VGA mch s .
Cc c im k thut thi gian ng b ha VGA v RGB (, xanh l cy, xanh dng) d liu c th c tm thy trn
cc trang web gio dc khc nhau (v d, tm kim cho thi gian tn hiu VGA). Hnh 4.12 minh ha cc yu cu thi gian c
bn cho mi hng (ngang) s c hin th trn mt mn hnh VGA. Mt xung hot ng thp ca thi gian c th (thi gian mt
trong hnh v) c p dng cho ng b ngang ( hsync) u vo ca mn hnh, m biu th kt thc mt dng d liu v bt
u tip theo. Cc d liu (RGB) u vo trn mn hnh phi c tt (a ti 0 V) cho mt khong thi gian gi l cng sau
(b) sau hsync xung xy ra, tip theo l khong thi gian hin th ( c).
Trong khong thi gian hin th d liu d liu RGB a mi pixel ln lt qua hng c hin th. Cui cng, c mt
khong thi gian gi l trc hin nh (d) ni cc tn hiu RGB mt ln na phi c tt trc khi tip theo hsync xung c
th xy ra. Thi im thc hin ng b dc ( vsync)
cng ging nh th hin trong hnh 4.12, ngoi tr mt m vsync xung ngha cui mt khung hnh v bt u tip theo, v cc d
liu lin quan n cc thit lp ca cc hng trong khung (thi gian ngang). Hnh 4.13 v 4.14 cho thy, i vi phn gii khc
nhau, thi lng ca khong thi gian mt, b, c, v d cho c thi gian ngang v dc.
Thng tin chi tit cho vic s dng video ADV7123 DAC c sn trong datasheet ca n, c th c tm thy trn trang web
ca nh sn xut, v t Bng dliu th mc trn DE2 H thng CD-ROM.
Cc bi tp pin gia II FPGA Cyclone v ADV7123 c lit k trong Bng 4.8. Mt v d v m m a mt mn

hnh VGA c m t trong mc 5.2 v 5.3.
38
DE2 Hng dn s dng
Hnh 4.12. VGA thi gian ngang c im k thut.
ch VGA Thi gian Spec ngang
Cu hnh Ngh quyt (HxV) mt (chng ti) xe but) c (chng ti) d (chng ti) Pixel ng h (Mhz)
VGA (60Hz) 640x480 3.8 1.9 25,4 0.6 25 (640 / c)
VGA (85Hz) 640x480 1.6 2.2 17,8 1.6 36 (640 / c)
SVGA (60Hz) 800x600 3.2 2.2 20 1 40 (800 / c)
SVGA (75Hz) 800x600 1.6 3.2 16,2 0.3 49 (800 / c)
SVGA (85Hz) 800x600 1.1 2,7 14,2 0.6 56 (800 / c)
XGA (60Hz) 1024x768 2.1 2,5 15.8 0.4 65 (1024 / c)
XGA (70Hz) 1024x768 1.8 1.9 13,7 0.3 75 (1024 / c)
XGA (85Hz) 1024x768 1.0 2.2 10,8 0,5 95 (1024 / c)
1280x1024 (60Hz) 1280x1024 1.0 2.3 11,9 0,4 108 (1280 / c)
Hnh 4.13. VGA thi gian ngang c im k thut.
ch VGA Dc Timing Spec
Cu hnh Ngh quyt (HxV) mt (lines) b (lines) c (lines) d (lines)
VGA (60Hz) 640x480 2 33 480 10
VGA (85Hz) 640x480 3 25 480 1
SVGA (60Hz) 800x600 4 23 600 1
SVGA (75Hz) 800x600 3 21 600 1
SVGA (85Hz) 800x600 3 27 600 1
XGA (60Hz) 1024x768 6 29 768 3
XGA (70Hz) 1024x768 6 29 768 3
XGA (85Hz) 1024x768 3 36 768 1
1280x1024 (60Hz) 1280x1024 3 38 1024 1
Hnh 4.14. VGA thi gian dc c im k thut.
39
DE2 Hng dn s dng
VGA_R [0] PIN_C8 VGA Red [0]
VGA_R [1] PIN_F10 VGA Red [1]
VGA_R [2] PIN_G10 VGA Red [2]
VGA_R [3] PIN_D9 VGA Red [3]
VGA_R [4] PIN_C9 VGA Red [4]
VGA_R [5] PIN_A8 VGA Red [5]
VGA_R [6] PIN_H11 VGA Red [6]
VGA_R [7] PIN_H12 VGA Red [7]
VGA_R [8] PIN_F11 VGA Red [8]
VGA_R [9] PIN_E10 VGA Red [9]
VGA_G [0] PIN_B9 VGA Xanh [0]
VGA_G [1] PIN_A9 VGA xanh [1]
VGA_G [2] PIN_C10 VGA xanh [2]
VGA_G [3] PIN_D10 VGA Xanh [3]
VGA_G [4] PIN_B10 VGA Xanh [4]
VGA_G [5] PIN_A10 VGA Xanh [5]
VGA_G [6] PIN_G11 VGA Xanh [6]
VGA_G [8] PIN_E12 VGA Xanh [8]
VGA_B [0] PIN_J13 VGA Blue [0]
VGA_B [1] PIN_J14 VGA xanh [1]
VGA_B [2] PIN_F12 VGA xanh [2]
VGA_B [3] PIN_G12 VGA Blue [3]
VGA_B [6] PIN_C11 VGA Blue [6]
VGA_B [7] PIN_B11 VGA Blue [7]
VGA_B [8] PIN_C12 VGA Blue [8]
VGA_B [9] PIN_B12 VGA Blue [9]
VGA_CLK PIN_B8 VGA Clock
VGA_BLANK PIN_D6 BLANK VGA
VGA_HS PIN_A7 VGA H_SYNC
VGA_VS PIN_D8 VGA V_SYNC
VGA_SYNC PIN_B7 VGA SYNC
Bng 4.8. ADV7123 tp pin.
40
DE2 Hng dn s dng
4.8 S dng 24-bit Audio CODEC

Ban DE2 cung cp cht lng cao m thanh 24-bit qua Wolfson WM8731 audio CODEC (encoder / decoder). Chip ny
h tr microphone-in, line-in, v cng line-out, vi mt t l mu c th iu chnh t 8 kHz n 96 kHz. Cc WM8731
c iu khin bi mt giao din bus I2C ni tip, c kt ni vi cc chn trn Cyclone II FPGA. Mt s ca mch
m thanh c th hin trong hnh 4.15, v cc bi tp FPGA pin c lit k trong Bng 4.9. Thng tin chi tit cho vic
s dng cc codec WM8731 c sn trong datasheet ca n, c th c tm thy trn trang web ca nh sn xut, v t Bng
dliu th mc trn DE2 H thng CD-ROM.
Hnh 4.15. Audio CODEC s .
AUD_ADCLRCK PIN_C5 Audio CODEC ADC LR Clock
AUD_ADCDAT PIN_B5 m thanh ADC liu CODEC
AUD_DACLRCK PIN_C6 Audio CODEC DAC LR Clock
AUD_DACDAT PIN_A4 Audio CODEC DAC d liu
AUD_XCK PIN_A5 Audio CODEC Chip Clock
AUD_BCLK PIN_B4 Audio CODEC Bit-Stream Clock
I2C_SCLK PIN_A6 I2C d liu
I2C_SDAT PIN_B6 I2C Clock
Bng 4.9. Audio CODEC tp pin.
41
DE2 Hng dn s dng
4.9 RS-232 Serial Port
Ban DE2 s dng chip thu pht MAX232 v mt kt ni D-SUB 9-pin cho RS-232 thng tin lin lc. bit thng
tin chi tit v cch s dng b thu pht tham kho datasheet, trong c sn trn trang web ca nh sn xut, v
t Bng dliu th mc trn DE2 H thng CD-ROM. Hnh 4.16 cho thy s c lin quan, v Bng 4.10 lit k
cc bi tp pin Cyclone II FPGA.
Hnh 4.16. MAX232 (RS-232) chip .
UART_RXD PIN_C25 UART Receiver
UART_TXD PIN_B25 UART Transmitter
Bng 4.10. RS-232 pin cc bi tp.
4.10 PS / 2 Serial Port
Ban DE2 bao gm mt giao din tiu chun PS / 2 v mt kt ni cho mt / 2 bn phm PS hoc chut. Hnh 4.17 cho thy s
ca mch PS / 2. Hng dn s dng mt PS / 2 chut hoc bn phm c th c tm thy bng cch thc hin mt tm
kim thch hp trn cc trang web gio dc khc nhau. Cc bi tp pin cho giao din lin quan c th hin trong Bng 4.11.
Hnh 4.17. PS / 2 s .
42
DE2 Hng dn s dng
PS2_CLK PIN_D26 PS / 2 Clock
PS2_DAT PIN_C24 PS / 2 d liu
Bng 4.11. bi tp PS / 2 pin.
4.11 Fast Ethernet iu khin mng

Ban DE2 cung cp h tr Ethernet qua kiu Davicom DM9000A Fast Ethernet chip iu khin. Cc DM9000A bao gm mt
giao din chung b x l, 16 Kbytes SRAM, mt n v iu khin truy cp phng tin truyn thng (MAC), v / 100M PHY
thu pht 10. Hnh 4.18 cho thy s mch cho giao din Fast Ethernet, v cc bi tp lin quan n pin c lit k trong
Bng 4.12. bit thng tin chi tit v cch s dng DM9000A tham kho bng d liu v ng dng ca n lu , trong c
sn trn trang web ca nh sn xut, v t Bng dliu th mc trn DE2 H thng CD-ROM.
Hnh 4.18. Nhanh chng s Ethernet.
ENET_DATA [0] PIN_D17 DM9000A D LIU [0]
ENET_DATA [1] PIN_C17 DM9000A D LIU [1]
ENET_DATA [2] PIN_B18 DM9000A D LIU [2]
ENET_DATA [3] PIN_A18 DM9000A D LIU [3]
43
DE2 Hng dn s dng
ENET_DATA [10] PIN_C19 DM9000A D LIU [10]
ENET_DATA [14] PIN_E18 DM9000A D LIU [14]
ENET_CLK PIN_B24 DM9000A Clock 25 MHz
ENET_CMD PIN_A21 DM9000A Command / d liu Chn, 0 = Command, 1 = D liu
ENET_CS_N PIN_A23 DM9000A Chip Chn
ENET_INT PIN_B21 DM9000A Interrupt
ENET_RD_N PIN_A22 DM9000A c
ENET_WR_N PIN_B22 DM9000A Vit
ENET_RST_N PIN_B23 DM9000A t li
Bng 4.12. Nhanh bi tp pin Ethernet.
4.12 TV Decoder
Ban DE2 c trang b mt chip gii m Analog Devices ADV7181 TV. Cc ADV7181 l mt b gii m video tch
hp t ng pht hin v chuyn i tn hiu truyn hnh analog baseband chun (NTSC, PAL, SECAM) thnh 4: 2:
2 thnh phn d liu video tng thch vi 16-bit / 8-bit CCIR601 / CCIR656. Cc ADV7181 l tng thch vi mt
lot cc thit b video, bao gm u a DVD, ngun bng c tr s, ngun pht sng, v camera an ninh / gim st.
Cc thanh ghi trong b gii m truyn hnh c th c lp trnh bi mt chic xe but I2C ni tip, m c kt ni vi Cyclone
II FPGA nh c ch ra trong hnh 4.19. Cc bi tp pin c lit k trong Bng 4.13. Thng tin chi tit trn ADV7181 c sn
trn trang web ca nh sn xut, v t Bng dliu
th mc trn DE2 H thng CD-ROM.
44
DE2 Hng dn s dng
Hnh 4.19. TV Decoder s .
TD_DATA [0] PIN_J9 TV Decoder d liu [0]
TD_DATA [1] PIN_E8 TV Decoder d liu [1]
TD_DATA [2] PIN_H8 TV Decoder d liu [2]
TD_DATA [3] PIN_H10 TV Decoder d liu [3]
TD_DATA [4] PIN_G9 TV Decoder d liu [4]
TD_DATA [5] PIN_F9 TV Decoder d liu [5]
TD_DATA [6] PIN_D7 TV Decoder d liu [6]
TD_DATA [7] PIN_C7 TV Decoder d liu [7]
TD_HS PIN_D5 TV Decoder H_SYNC
TD_VS PIN_K9 TV Decoder V_SYNC
TD_CLK27 PIN_C16 TV Decoder Clock Input.
TD_RESET PIN_C4 TV Decoder t li
I2C_SCLK PIN_A6 I2C d liu
I2C_SDAT PIN_B6 I2C Clock
Bng 4.13. TV Decoder tp pin.
45
DE2 Hng dn s dng
4.13 Thc hin mt b m ha truyn hnh
Mc d hi ng qun tr DE2 khng bao gm mt chip encoder TV, ADV7123 (10-bit tc cao ADCs ba) c th c s dng
thc hin mt b m ha truyn hnh cht lng chuyn nghip vi phn x l k thut s thc hin trong Cyclone II FPGA. Hnh
4.20 cho thy mt s khi ca mt b m ha truyn hnh c thc hin theo cch ny.
Hnh 4.20. Mt m ha truyn hnh m s dng II FPGA Cyclone v ADV7123.
4.14 S dng USB Host v thit b
Ban DE2 cung cp c my ch USB v giao din thit b s dng n chip iu khin USB Philips ISP1362. Ngi
dn chng trnh v thit b iu khin l ph hp vi Universal Serial Bus Specification Rev. 2.0, h tr truyn d
liu tc y (12 Mbit / s) v tc thp (1,5 Mbit / s). Hnh 4.21 m t s ca mch USB; cc bi tp
pin cho giao din lin quan c lit k trong Bng 4.14.
Thng tin chi tit cho vic s dng cc thit b ISP1362 c sn trong bng d liu v lp trnh hng dn ca n; c hai vn bn c
th c tm thy trn trang web ca nh sn xut, v t Bng dliu th mc trn DE2 H thng CD-ROM. Phn kh khn nht
ca mt ng dng USB l trong vic thit k trnh iu khin phn mm cn thit. Hai v d hon chnh ca trnh iu khin USB,
cho c my ch v thit b ng dng, c th c tm thy ti mc 5.3 v 5.4. Nhng cuc biu tnh cung cp v d v cc trnh
iu khin phn mm cho cc b vi x l Nios II.
46
DE2 Hng dn s dng
Hnh 4.21. USB (ISP1362) my ch v thit b s .
OTG_ADDR [0] PIN_K7 ISP1362 a ch [0]
OTG_ADDR [1] PIN_F2 ISP1362 a ch [1]
OTG_DATA [0] PIN_F4 ISP1362 d liu [0]
OTG_DATA [1] PIN_D2 ISP1362 d liu [1]
OTG_DATA [2] PIN_D1 ISP1362 d liu [2]
OTG_DATA [3] PIN_F7 ISP1362 d liu [3]
OTG_DATA [4] PIN_J5 ISP1362 d liu [4]
OTG_DATA [7] PIN_H6 ISP1362 d liu [7]
OTG_DATA [8] PIN_E2 ISP1362 d liu [8]
OTG_DATA [9] PIN_E1 ISP1362 d liu [9]
OTG_DATA [10] PIN_K6 ISP1362 d liu [10]
OTG_DATA [12] PIN_G4 ISP1362 d liu [12]
OTG_DATA [13] PIN_G3 ISP1362 d liu [13]
OTG_CS_N PIN_F1 ISP1362 Chip Chn
OTG_RD_N PIN_G2 ISP1362 c
47
DE2 Hng dn s dng
OTG_WR_N PIN_G1 ISP1362 Vit
OTG_RST_N PIN_G5 ISP1362 t li
OTG_INT0 PIN_B3 ISP1362 Interrupt 0
OTG_INT1 PIN_C3 ISP1362 Interrupt 1
OTG_DACK0_N PIN_C2 ISP1362 DMA Tha nhn 0
OTG_DACK1_N PIN_B2 ISP1362 DMA Tha nhn 1
OTG_DREQ0 PIN_F6 ISP1362 DMA Request 0
OTG_DREQ1 PIN_E5 ISP1362 DMA Request 1
OTG_FSPEED PIN_F3 USB Full Speed, 0 = Enable, Z = Tt
OTG_LSPEED PIN_G6 USB tc thp, 0 = Enable, Z = Tt
Bng 4.14. bi tp USB (ISP1362) pin.
4.15 S dng IrDA
Ban DE2 cung cp mt phng tin truyn thng khng dy n gin bng cch s dng Agilent HSDL-3201 cng sut thp thu
pht hng ngoi. Datasheet cho thit b ny c cung cp trong Datasheet \ IrDA
th mc trn DE2 H thng CD-ROM. Lu rng tc truyn ti cao nht c h tr l 115,2 Kbit / s v c hai bn
TX v RX phi s dng tc truyn ti tng t. Hnh 4.22 cho thy s ca cc lin kt truyn thng IrDA. Vui
lng tham kho trang web sau y bit thng tin chi tit
trn lm sao n gi v nhn c d liu s dng cc IrDA lin kt:
http://techtrain.microchip.com/webseminars/documents/IrDA_BW.pdf . Vic chuyn nhng pin
ca giao din c lin quan c lit k trong Bng 4.15.
Hnh 4.22. IrDA s .
IRDA_TXD PIN_AE24 IRDA Transmitter
IRDA_RXD PIN_AE25 IRDA Receiver
Bng 4.15. IrDA tp pin.
48
DE2 Hng dn s dng
4.16 S dng SDRAM / SRAM / Flash
Ban DE2 cung cp 8 Mbyte SDRAM, 512-Kbyte SRAM, v 4 Mbyte (1 Mbyte trn mt s hi ng) b nh Flash.
Hnh 4,23, 4,24 v 4,25 cho thy s ca cc chip b nh. Cc bi tp pin cho mi thit b c lit k trong bng
4.16, 4.17, v 4.18. Datasheets cho cc chip b nh c cung cp trong Bng dliu th mc trn DE2 H thng
CD-ROM.
Hnh 4.23. SDRAM s .
Hnh 4,24. SRAM s .
49
DE2 Hng dn s dng
Hnh 4.25. Flash s .
DRAM_ADDR [0] PIN_T6 SDRAM a ch [0]
DRAM_ADDR [1] PIN_V4 SDRAM a ch [1]
DRAM_ADDR [3] PIN_W2 SDRAM a ch [3]
DRAM_ADDR [5] PIN_U6 SDRAM a ch [5]
DRAM_ADDR [10] PIN_Y1 SDRAM a ch [10]
DRAM_DQ [0] PIN_V6 SDRAM d liu [0]
DRAM_DQ [1] PIN_AA2 SDRAM d liu [1]
DRAM_DQ [3] PIN_Y3 SDRAM d liu [3]
DRAM_DQ [4] PIN_Y4 SDRAM d liu [4]
DRAM_DQ [5] PIN_R8 SDRAM d liu [5]
DRAM_DQ [6] PIN_T8 SDRAM d liu [6]
DRAM_DQ [7] PIN_V7 SDRAM d liu [7]
DRAM_DQ [8] PIN_W6 SDRAM d liu [8]
50
DE2 Hng dn s dng
DRAM_DQ [9] PIN_AB2 SDRAM d liu [9]
DRAM_DQ [10] PIN_AB1 SDRAM d liu [10]
DRAM_DQ [13] PIN_AC2 SDRAM d liu [13]
DRAM_DQ [14] PIN_AC1 SDRAM d liu [14]
DRAM_BA_0 PIN_AE2 SDRAM a ch ngn hng [0]
DRAM_BA_1 PIN_AE3 SDRAM a ch ngn hng [1]
DRAM_LDQM PIN_AD2 SDRAM Low-byte d liu Mask
DRAM_UDQM PIN_Y5 SDRAM cao byte d liu Mask
DRAM_RAS_N PIN_AB4 SDRAM Row Address Strobe
DRAM_CAS_N PIN_AB3 SDRAM Column Address Strobe
DRAM_CKE PIN_AA6 SDRAM Clock Enable
DRAM_CLK PIN_AA7 SDRAM Clock
DRAM_WE_N PIN_AD3 SDRAM Vit Enable
DRAM_CS_N PIN_AC3 SDRAM Chip Chn
Bng 4.16. bi tp SDRAM pin.
SRAM_ADDR [0] PIN_AE4 SRAM a ch [0]
SRAM_ADDR [1] PIN_AF4 SRAM a ch [1]
SRAM_ADDR [2] PIN_AC5 SRAM a ch [2]
SRAM_ADDR [4] PIN_AD4 SRAM a ch [4]
SRAM_ADDR [6] PIN_AE5 SRAM a ch [6]
SRAM_ADDR [7] PIN_AF5 SRAM a ch [7]
SRAM_ADDR [10] PIN_V10 SRAM a ch [10]
SRAM_ADDR [11] PIN_V9 SRAM a ch [11]
SRAM_ADDR [13] PIN_W8 SRAM a ch [13]
SRAM_ADDR [14] PIN_W10 SRAM a ch [14]
SRAM_ADDR [15] PIN_Y10 SRAM a ch [15]
51
DE2 Hng dn s dng
SRAM_ADDR [16] PIN_AB8 SRAM a ch [16]
SRAM_DQ [0] PIN_AD8 SRAM D liu [0]
SRAM_DQ [1] PIN_AE6 SRAM D liu [1]
SRAM_DQ [2] PIN_AF6 SRAM D liu [2]
SRAM_DQ [3] PIN_AA9 SRAM d liu [3]
SRAM_DQ [4] PIN_AA10 SRAM D liu [4]
SRAM_DQ [5] PIN_AB10 SRAM D liu [5]
SRAM_DQ [6] PIN_AA11 SRAM D liu [6]
SRAM_DQ [7] PIN_Y11 SRAM D liu [7]
SRAM_DQ [12] PIN_W11 SRAM D liu [12]
SRAM_DQ [13] PIN_W12 SRAM D liu [13]
SRAM_DQ [14] PIN_AC9 SRAM D liu [14]
SRAM_DQ [15] PIN_AC10 SRAM D liu [15]
SRAM_WE_N PIN_AE10 SRAM Vit Enable
SRAM_OE_N PIN_AD10 SRAM Output Enable
SRAM_UB_N PIN_AF9 SRAM cao byte d liu Mask
SRAM_LB_N PIN_AE9 SRAM Low-byte d liu Mask
SRAM_CE_N PIN_AC11 SRAM Chip Enable
Bng 4.17. bi tp SRAM pin.
FL_ADDR [0] PIN_AC18 FLASH a ch [0]
FL_ADDR [1] PIN_AB18 FLASH a ch [1]
FL_ADDR [2] PIN_AE19 FLASH a ch [2]
FL_ADDR [3] PIN_AF19 FLASH a ch [3]
FL_ADDR [6] PIN_Y16 FLASH a ch [6]
FL_ADDR [7] PIN_AA16 FLASH a ch [7]
FL_ADDR [8] PIN_AD17 FLASH a ch [8]
52
DE2 Hng dn s dng
FL_ADDR [12] PIN_W16 FLASH a ch [12]
FL_ADDR [13] PIN_W15 FLASH a ch [13]
FL_ADDR [15] PIN_AD16 FLASH a ch [15]
FL_ADDR [18] PIN_AB15 FLASH a ch [18]
FL_ADDR [19] PIN_AA15 FLASH a ch [19]
FL_DQ [0] PIN_AD19 FLASH d liu [0]
FL_DQ [1] PIN_AC19 FLASH d liu [1]
FL_DQ [2] PIN_AF20 FLASH d liu [2]
FL_DQ [3] PIN_AE20 FLASH d liu [3]
FL_DQ [4] PIN_AB20 FLASH d liu [4]
FL_DQ [5] PIN_AC20 FLASH d liu [5]
FL_DQ [6] PIN_AF21 FLASH d liu [6]
FL_DQ [7] PIN_AE21 FLASH d liu [7]
FL_CE_N PIN_V17 FLASH Chip Enable
FL_OE_N PIN_W17 FLASH Output Enable
FL_RST_N PIN_AA18 FLASH Thit lp li
FL_WE_N PIN_AA17 FLASH Write Enable
Bng 4.18. bi tp flash pin.
53
DE2 Hng dn s dng
Chng 5
V d v cc cuc biu tnh nng cao

Chng ny cung cp mt s v d v mch tin tin thc hin trn bng DE2. Nhng mch cho cc cuc biu tnh
ca cc tnh nng chnh trn din n, chng hn nh m thanh v kh nng video, v USB v kt ni Ethernet. i
vi mi cuc biu tnh Cyclone II FPGA (hoc serial EPCS16 EEPROM) tp tin cu hnh c cung cp, cng nh
ton b m ngun trong m Verilog HDL. Tt c cc file c lin quan c th c tm thy trong DE2_demonstrations th
mc t DE2 H thng CD-ROM. i vi mi cuc biu tnh c m t trong cc phn sau, chng ti cung cp cho
cc tn ca th mc d n cho cc tp tin ca n, l th mc con ca
DE2_demonstrations th mc.
Ci t cuc biu tnh
ci t cc cuc biu tnh trn my tnh ca bn, hy thc hin nh sau
1. Sao chp th mc DE2_demonstrations vo mt th mc a phng ca s la chn ca bn. N l
quan trng m bo rng ng dn n th mc a phng khng cha khong trng - nu khng, phn mm Nios II s khng
hot ng.
2. Trong th mc DE2_demonstrations, i n th mc con fixpaths.

3. Chy DE2_fixpaths.bat tp tin thc thi. Trong hp thoi bt ln, chn th mc
DE2_demonstrations trong th mc a phng ca bn, ni bn sao chp cc tp tin vo. Nhp OK.
4. Khi no fixpaths xong, nhn phm bt k hon tt qu trnh.
5.1 Cu hnh my DE2

Ban DE2 c vn chuyn t nh my vi cu hnh mc nh th hin mt s tnh nng c bn ca hi ng qun tr.
Cc thit lp cn thit cho cuc biu tnh ny, v v tr cc tp tin ca n c hin th di y.
Trnh din ci t, File Locations, v Hng dn
th mc d n: DE2_Default
dng bit c s dng: DE2_Default.sof hoc l DE2_Default.pof
54
DE2 Hng dn s dng
Sc mnh trn bng DE2, bng cp USB kt ni vi cng USB Blaster. Nu cn thit (c ngha l, nu cu hnh
mc nh ca hi ng qun tr DE2 hin khng lu tr trong thit b EPCS16), ti dng bit hi ng qun tr
bng cch s dng mt trong hai JTAG hoc AS lp trnh
By gi bn c th quan st rng cc mn hnh 7-segment ang hin th mt chui cc k t, v cc n LED mu v
mu xanh l cy ang nhp nhy. Cng th, Cho mng bn n DE2 Altera Ban c hin th trn mn hnh LCD
Ty chn kt ni mn hnh VGA kt ni VGA D-SUB. Khi kt ni, mn hnh VGA s hin th mt m
hnh ca mu sc.
Ty chn kt ni mt chic loa vi jack audio-out stereo
t Toggle chuyn SW17 v tr UP nghe 1 kHz ngn nga m thanh t cng audio-out. Ngoi ra, nu cng
tc SW17 l DOWN, micro-in cng c th c kt ni vi mt micro nghe ging ni m thanh, hoc line-in
cng c th c s dng chi m thanh t mt ngun m thanh ph hp.
M ngun Verilog cho cuc biu tnh ny c cung cp trong DE2_Default th mc, bao gm c cc tp tin cn thit cho vic
tng ng d n Quartus II. Cc cp cao nht Verilog tp tin, gi DE2_Default.v, c th c s dng nh l mt khun mu cho
cc d n khc, bi v n xc nh cc cng tng ng vi tt c cc ngi dng c th truy cp ghim trn Cyclone II FPGA.
5.2 Thuyt minh TV Box

cuc biu tnh ny ng video v m thanh u vo t mt u DVD bng cch s dng u ra VGA v gii m m
thanh trn bng DE2. Hnh 5.1 cho thy s khi ca thit k. C hai khi ln trong mch, gi l I2C_AV_Config v TV_to_VGA.
Cc TV_to_VGA khi bao gm cc ITU-R 656 Decoder, SDRAM Khung m, YUV422 YUV444, YCrCb RGB, v VGA
Controller. Con s ny cng cho thy TV Decoder (ADV7181) v VGA DAC (ADV7123) chip c s dng.
Ngay sau khi dng bit c ti v vo FPGA, cc gi tr ng k ca chip TV Decoder c s dng cu hnh
cc b gii m TV qua I2C_AV_Config khi, trong s dng giao thc I2C giao tip vi chip TV Decoder. Sau
chui power-on, chip TV Decoder s khng n nh cho mt khong thi gian; cc Kha Detector c trch nhim
pht hin bt n ny.
Cc ITU-R 656 Decoder chit xut khi YCrCb 4: 2: 2 (YUV 4: 2: 2) tn hiu video t ITU-R 656
lung d liu c gi t Decoder TV. N cng to ra mt d liu tn hiu iu khin hp l cho thy giai on hp l ca d liu
u ra. Bi v cc tn hiu video t TV Decoder l interlaced, chng ta cn phi thc hin de-interlacing trn ngun d liu. Chng
ti s dng SDRAM Khung m v multiplexer la chn lnh vc ( MUX) c iu khin bi iu khin VGA thc hin cc hot
ng de-interlacing.
55
DE2 Hng dn s dng
Bn trong, cc VGA iu khin to ra yu cu d liu v l / tn hiu thm ch chn vo SDRAM Khung m v multiplexer
la chn np ( MUX). Cc YUV422 YUV444 khi chuyn i la chn YCrCb 4: 2 2 (YUV 4 2: 2) d liu video n YCrCb
4: 4: 4 (YUV 4: 4: 4) nh dng d liu video.
Cui cng, YCrCb_to_RGB khi chuyn i YCrCb d liu vo u ra RGB. Cc VGA iu khin
khi to tn hiu ng b VGA tiu chun VGA_HS v VGA_VS cho php mn hnh hin th trn mt mn hnh VGA.
Hnh 5.1. s khi ca cc cuc biu tnh hp TV.
th mc d n: DE2_TV
dng bit c s dng: DE2_TV.sof hoc l DE2_TV.pof
Kt ni u ra composite video mt u DVD ca (mu vng cm) Video-in RCA jack ca Ban DE2. My nghe
nhc DVD phi c cu hnh cung cp
o u ra NTSC
o tc lm ti 60 Hz
o t l 3 kha cnh: 4
video khng tin b

Kt ni u ra VGA ca Ban DE2 vi mn hnh VGA (c hai mn hnh LCD v CRT loi mn hnh nn lm vic)
56
DE2 Hng dn s dng
Kt ni u ra m thanh ca my nghe nhc DVD vo line-in cng ca Ban DE2 v kt ni mt loa vo cng line-out.
Nu gic cm u ra m thanh t cc my nghe nhc DVD l kiu RCA, sau l mt b chuyn i s l cn thit
chuyn i cm mini-stereo h tr trn bng DE2; y l cng mt loi cm c h tr trn hu ht cc my
tnh
Ti dng bit vo FPGA. Nhn KEY0 trn bng DE2 thit lp li cc mch
Hnh 5.2 minh ha cc thit lp cho cuc biu tnh ny.
Hnh 5.2. Cc thit lp cho cc cuc biu tnh hp TV.
5.3 Paintbrush USB
USB l mt phng php truyn thng ph bin c s dng trong nhiu sn phm a phng tin. Ban DE2 cung cp gii php USB y
cho c hai my ch v thit b ng dng. Trong cuc biu tnh ny, chng ti thc hin mt ng dng Paintbrush bng cch s dng mt
con chut USB nh thit b u vo.
cuc biu tnh ny s dng cng thit b ca chip Philips ISP1362 v b vi x l Nios II thc hin mt my d chuyn
ng chut USB. Chng ti cng thc hin mt b m khung hnh vi mt b iu khin VGA thc hin vic lu tr
hnh nh theo thi gian thc v hin th. Hnh 5.3 cho thy s khi ca mch in, cho php ngi dng v ng
trn mn hnh hin th VGA s dng chut USB. Cc VGA iu khin khi c tch hp vo xe but Altera Avalon n c
th c iu khin bi b vi x l Nios II.
Sau khi chng trnh chy trn b vi x l Nios II c khi ng, n s pht hin s tn ti ca con chut USB kt ni vi
DE2 bng. Khi chut c di chuyn, b vi x l Nios II c kh nng theo di cc phong tro v ghi li n trong mt b
nh m khung. Cc VGA iu khin s chng ln

57
DE2 Hng dn s dng
d liu c lu tr trong b m khung vi mt mu hnh nh mc nh v hin th hnh nh chng cho trn mn hnh VGA.
Hnh 5.3. s khi ca cc cuc biu tnh USB c.
th mc d n: DE2_NIOS_HOST_MOUSE_VGA
dng bit c s dng: DE2_NIOS_HOST_MOUSE_VGA.sof
Nios II Workspace: DE2_NIOS_HOST_MOUSE_VGA
Kt ni chut USB Connector USB My ch (loi A) ca Ban DE2

Ti dng bit vo FPGA

Chy Nios II v chn DE2_NIOS_HOST_MOUSE_VGA nh khng gian lm vic. Click vo bin son v Chy nt
By gi bn c th quan st mt nn mu xanh vi logo Altera trn mn hnh VGA
Di chuyn con chut USB v quan st s chuyn ng tng ng ca con tr trn mn hnh
Nhp chut tri chut v cc chm trng / dng v nhp chut phi chut v chm xanh / dng trn mn hnh.
58
DE2 Hng dn s dng
Hnh 5.4. Cc thit lp cho cc cuc biu tnh USB c.
5.4 thit b USB
Hu ht cc ng dng USB v cc sn phm hot ng nh cc thit b USB, ch khng phi l host USB. Trong cuc biu tnh ny,
chng ta thy lm th no hi ng qun tr DE2 c th hot ng nh mt thit b USB c th c kt ni vi mt my ch. Nh nu
trong s khi trong hnh 5.5, b vi x l Nios II c s dng giao tip vi my ch thng qua cng lu tr trn thit b Philips
ISP1362 hi ng qun tr ca DE2.
Sau khi kt ni bng DE2 ti mt cng USB trn my ch, mt chng trnh phn mm phi c thc thi trn b vi x l
Nios II khi to chip Philips ISP1362. Sau khi chng trnh phn mm c thc hin thnh cng, cc my ch s xc
nh cc thit b mi trong danh sch thit b USB ca mnh v yu cu ngi li xe lin quan; thit b s c xc nh l
mt Philips PDIUSBD12 SMART Hi ng nh gi. Sau khi hon thnh qu trnh ci t driver trn my ch, bc tip
theo l chy mt chng trnh phn mm trn my ch gi ISP1362DcUsb.exe; Chng trnh ny lin lc vi hi ng
qun tr DE2.
bn trong ISP1362DcUsb chng trnh, nhp vo Thm vo nt trong bng iu khin ca s ca phn mm lm cho my ch gi
mt gi d liu USB c bit cho Ban DE2; cc gi d liu s c nhn bi b vi x l Nios II v s tng gi tr ca mt b m
phn cng. Gi tr ca b m s c hin th trn mt trong nhng mn hnh 7-segment ca hi ng qun tr, v cng trn n
LED mu xanh l cy. Nu ngi dng nhp vo Trong sng nt trong bng iu khin ca s ca trnh iu khin phn mm, my
ch s gi mt gi d liu USB khc nhau hi ng qun tr, gy ra cc b x l Nios II xa b m phn cng khng.
59
DE2 Hng dn s dng
Hnh 5.5. s khi ca cc cuc biu tnh thit b USB.
th mc d n: DE2_NIOS_DEVICE_LED \ HW
dng bit c s dng: DE2_NIOS_DEVICE_LED.sof
Nios II Workspace: DE2_NIOS_DEVICE_LED \ HW
Trnh iu khin Borland BC ++ phn mm: DE2_NIOS_DEVICE_LED \ SW
Ti dng bit vo FPGA

Chy Nios II IDE vi HW nh khng gian lm vic. Bm vo bin son v Chy
Ni kt ni thit b USB ca hi ng qun tr DE2 n my ch bng cp USB (loi A B). Mt thit b

phn cng USB mi s c pht hin
Xc nh v tr ca ngi li xe nh DE2_NIOS_DEVICE_LED \ D12test.inf (Philips PDIUSBD12 SMART Hi
ng nh gi). B qua bt k thng ip cnh bo c sn xut trong khi ci t
Cc my ch nn bo co rng mt SMART Board nh gi Philips PDIUSBD12 hin ang c ci t
Thc hin cc phn mm: DE2_NIOS_DEVICE_LED \ SW \ ISP1362DcUsb.exe trn my ch. Sau , th

nghim vi phn mm bng cch nhp vo Thanh v cc nt r rng
60
DE2 Hng dn s dng
Hnh 5.6. Cc thit lp cho cc cuc biu tnh USB c.
5,5 Mt my Karaoke
cuc biu tnh ny s dng cng micro-in, line-in, v line-out trn bng DE2 to ra mt ng dng my Karaoke.
CODEC m thanh Wolfson WM8731 c cu hnh ch thc s, ni m cc CODEC m thanh to ra AD / DA ng
h ni tip bit (BCK) v tri / phi ng h knh (LRCK) t ng. Nh nu trong Hnh 5.7, giao din I2C c s
dng cu hnh cc m thanh CODEC. T l mu v t c ca cc CODEC c thit lp theo cch ny, v cc
u vo d liu t line-in cng sau c trn vi micro-in cng v kt qu s c gi n cng line-out.
i vi cuc biu tnh ny t l mu c thit lp n 48 kHz. Nhn pushbutton KEY0 b tr li s khuych i ca CODEC m thanh
thng qua bus I2C, i xe p qua mt trong mi li nhun c xc nh trc (mc m lng) c cung cp bi cc thit b.
Hnh 5.7. s khi ca my trnh din Karaoke.
61
DE2 Hng dn s dng
th mc d n: DE2_i2sound
dng bit c s dng: DE2_i2sound.sof hoc DE2_i2sound.pof
Kt ni micr vi micro-in cng (mu hng) trn bng DE2

Kt ni u ra m thanh ca mt nhc ngi chi, chng hn nh mt my nghe nhc MP3 hoc my tnh, vo line-in cng (mu
xanh) trn bng DE2
Kt ni tai nghe / loa vo cng line-out (mu xanh) trn bng DE2
Ti dng bit vo FPGA
Bn s c th nghe mt hn hp ca m thanh micro v m thanh t my nghe nhc
nhn KEY0 iu chnh m lng; n chu k gia cc cp khi lng 0-9
Hnh 5.8. Qu trnh ci t cho sn phm My Karaoke.
5,6 Gi Ethernet gi / nhn

Trong cuc biu tnh ny, chng ta s thy lm th no gi v nhn cc gi Ethernet s dng b iu khin Fast Ethernet
trn DE2 bng. Nh c minh ha trong hnh 5.9, chng ti s dng b vi x l Nios II gi v nhn cc gi Ethernet s
dng PHY DM9000A Ethernet / MAC Controller. Cc cuc biu tnh c th c thit lp s dng hoc kt ni vng lp li
t mt bng vi chnh n, hoc hai bng DE2 kt ni vi nhau.
62
DE2 Hng dn s dng
V pha truyn, b vi x l Nios II gi 64 byte gi mi 0,5 giy cc DM9000A. Sau khi nhn c gi tin, cc
DM9000A gn thm mt checksum bn byte cc gi d liu v gi n vo cng Ethernet.
V pha tip nhn, kim tra DM9000A mi gi tin nhn c xem a ch MAC ch trong gi l trng vi a ch
MAC ca hi ng qun tr DE2. Nu gi d liu nhn c khng c a ch MAC ging nhau hay l mt gi tin qung
b, cc DM9000A s chp nhn cc gi tin v gi mt ngt b vi x l Nios II. B x l sau s hin th ni dung gi
tin trong giao din iu khin ca s Nios II IDE.
Hnh 5.9. Gi gi v nhn bng cch s dng b vi x l Nios II.
th mc d n: DE2_NET
dng bit c s dng: DE2_NET.sof
Nios II Workspace: DE2_NET
Cm cp CAT5 lp li vo u ni Ethernet ca DE2

Ti dng bit vo FPGA
Chy IDE Nios II di workspace DE2_NET
Click vo bin son v Chy nt
By gi bn c th quan st cc ni dung ca gi tin nhn c (gi 64 byte gi i, cc gi d liu
68-byte nhn c v checksum thm byte)
Hnh 5.10 minh ha vic thit lp cho cuc biu tnh ny.
63
DE2 Hng dn s dng
Hnh 5.10. Cc thit lp cho cc cuc biu tnh Ethernet.
5,7 SD Card Music Player
Nhiu thng mi media / my nghe nhc s dng mt thit b lu tr bn ngoi ln, chng hn nh th SD hoc th CF,
lu tr nhc hoc file video. chi nh vy cng c th bao gm cc thit b DAC-cht lng cao do cht lng m thanh tt
c sn xut. Ban DE2 cung cp phn cng v phn mm cn thit truy cp th SD v hiu sut m thanh chuyn nghip
c th thit k sn phm a phng tin tin tin s dng bng DE2.
Trong cuc biu tnh ny, chng ta thy lm th no thc hin mt SD Card Music Player trn bng DE2, trong cc tp tin nhc c
lu tr trong th SD v hi ng qun tr c th chi cc file nhc qua a CD cht lng mch m thanh DAC ca n. Chng ti s dng
b vi x l Nios II c d liu m nhc c lu tr trong th nh SD v s dng b gii m m thanh Wolfson WM8731 chi nhc.
CODEC m thanh c cu hnh ch n l, ni m mch in bn ngoi phi cung cp cho ADC / DAC ng h bit ni tip ( BCK)
v tri / phi ng h knh ( LRCK) vi m thanh CODEC. Nh trnh by trong hnh 5.11, chng ti cung cp mt m thanh DAC
iu khin t c cc th h ng h v kim sot lung d liu. Cc m thanh DAC iu khin c tch hp vo kin trc
bus Avalon, do b vi x l Nios II c th kim sot cc ng dng.
64
DE2 Hng dn s dng
Trong hot ng ca b vi x l Nios II s kim tra xem b nh FIFO ca m thanh DAC iu khin
tr nn y . Nu FIFO l khng y , b vi x l s c mt ngnh 512-byte v gi d liu vo FIFO ca m thanh
DAC iu khin qua xe but Avalon. Cc m thanh DAC iu khin s dng mt t l mu 48 kHz gi d liu v tn hiu
ng h m thanh CODEC. Thit k ny cng pha trn d liu t micro-in vi line-in cho cc hiu ng Karaoke kiu.
Hnh 5.11. s khi ca cc cuc biu tnh nghe nhc SD.
th mc d n: DE2_SD_Card_Audio
dng bit c s dng: DE2_SD_Card_Audio.sof
Nios II Workspace: DE2_SD_Card_Audio
nh dng th SD ca bn vo FAT16 nh dng
pht mt tp tin m nhc vi cuc biu tnh ny, tp tin phi s dng t l mu 48KHz v
phn gii mu 16-bit nh dng WAV. Sao chp mt hoc nhiu file WAV vo SD Card FAT16 nh dng.
Do mt hn ch trong phn mm s dng cho cuc biu tnh ny, n l cn thit nh dng li th nh SD
ton b nu bt k tp tin WAV c sao chp vo th cn sau ny c ly ra t th SD
Ti dng bit vo FPGA

Chy IDE Nios II di workspace DE2_SD_Card_Audio
Kt ni tai nghe hoc loa cho Ban DE2 v bn s c th nghe nhc chi t SD Card
65
DE2 Hng dn s dng
Hnh 5.12. Cc thit lp cho cc cuc biu tnh nghe nhc SD.
5,8 Trnh din m nhc tng hp

trnh din iu ny cho thy lm th no thc hin mt Multi-tone Bn phm in t s dng DE2 tu vi mt PS / 2 Keyboard
v mt loa.
PS / 2 Keyboard c s dng nh bn phm n piano cho u vo. FPGA Cyclone II trn bng DE2 phc v nh Music
Synthesizer SOC to ra m nhc v nhc. Cc VGA kt ni vi hi ng qun tr DE2 c s dng hin th nhng phm
c nhn trong chi ca m nhc.
Hnh 5.13 cho thy s ca khi thit k ca Music Synthesizer. C bn khi ln trong mch: DEMO_SOUND, PS2_KEYBOA
NHN VIN, v TONE_GENERATOR. Cc
DEMO_SOUND khi lu tr mt m thanh gii thiu cho ngi dng chi; PS2_KEYBOARD x l u vo ca ngi dng t
PS / 2 bn phm; Cc CN B khi v s bn phm tng ng trn mn hnh VGA khi cha kha (s) c p. Cc TONE_GENERATOR
l ct li ca b tng hp m nhc SOC.
Ngi dng c th chuyn i cc ngun nhc hoc t PS2_KEYBOAD hoc l DEMO_SOUND chn bng cch s SW9. lp li m thanh
demo, ngi dng c th nhn key1.
Cc TONE_GENERATOR c hai tng mu: (1) String. (2) Brass, c th c iu khin bi SW0. Codec m thanh c s
dng trn cc board DE2 c hai knh, c th c bt ON / OFF bng SW1 v SW2.
66
DE2 Hng dn s dng
Hnh 5.13. s khi ca thit k m nhc tng hp
th mc d n: DE2_Synthesizer
dng bit c s dng: DE2_Synthesizer.sof hoc l DE2_Synthesizer.pof
Kt ni PS / 2 Keyboard cho Ban DE2.

Ni lineout ca Ban DE2 mt loa.

Ti dng bit vo FPGA.
Hy chc chn rng tt c cc thit b chuyn mch (SW [9: 0]) c thit lp 0 (Down Chc v)
Thng co bo key1 trn bng DE2 bt u bn demo nhc
Nhn KEY0 trn bng DE2 thit lp li cc mch
Bng 5.1 v 5.2 minh ha vic s dng thit b chuyn mch, nt bm (phm), PS / 2 Keyboard.
67
DE2 Hng dn s dng
Cng tc v nt bm
Tn tn hiu S miu t
KEY [0] t li Circuit
KEY [1] Lp li Demo m nhc
SW [0] OFF: BRASS, ON: STRING
SW [9] OFF: DEMO, ON: KEYBOARD PS2
SW [1] Knh-1 ON / OFF
SW [2] Knh-2 ON / OFF
Bng 5.1. S dng thit b chuyn mch, nt bm (phm).
PS / 2 Keyboard
Tn tn hiu S miu t
Q -# 4
Mt -5
W -# 5
S -6
E -# 6
D -7
F 1
T #1
G 2
Y #2
H 3
J 4
ti #4
K 5
O #5
L 6
P #6
: 7
+1
Bng 5.2. S dng cc phm PS / 2 Keyboard ca.
68
DE2 Hng dn s dng
Hnh 5.14. Setup ca din m nhc tng hp.
Bn quyn 2005 Cng ty C phn Altera. Tt c quyn c bo lu. Altera, Cng ty lp trnh Solutions, logo cch iu
Altera, nh danh thit b c th, v tt c cc t v logo khc c xc nh l cc nhn hiu v / hoc nhn hiu dch v
c, tr khi c ghi ch khc, cc thng hiu v nhn hiu dch v ca Tp on Altera M v cc nc khc. Tt c
cc tn sn phm hoc dch v khc l ti sn ca ch s hu tng ng ca h. sn phm Altera c bo v theo
nhiu
M v bng sng ch nc ngoi v cc ng dng ch gii quyt, mt n quyn lm vic, v bn quyn. Altera bo m thc hin cc
sn phm bn dn ca mnh thng s k thut hin ti ph hp vi tiu chun bo hnh Altera, nhng c quyn thc hin thay i i
vi bt k sn phm v dch v bt c lc no m khng cn thng bo trc. Altera khng chu trch nhim hoc trch nhim php l
pht sinh t vic ng dng hoc s dng bt k thng tin, sn phm hoc dch v c m t trong ti liu ny tr khi c ng
bng vn bn ca Cng ty C phn Altera. khch hng Altera c khuyn c c phin bn mi nht ca thng s k thut thit
b trc khi da vo bt k thng tin cng b v trc khi t hng cc sn phm hoc dch v.
Ti liu ny ang c cung cp trn c nh n vn c c s v l mt ch v do tt c cc bo m, c quan i
din hoc bo m ca bt c loi no (d r rng, ng hay theo lut nh), bao gm, nhng khng gii hn, bo m v
kh nng bn, khng vi phm, hoc ph hp cho mt mc ch c th, c ph nhn c bit.
69

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Board DE2 Altera

DE2 y ban Pht trin v Gio dc

phin bn 1.4 Bn quyn 2006 Cng ty C phn Altera

Chng 1 DE2 Gi .............................................. .................................................. ..................... 1

1.1 Ni dung ng gi ................................................ .................................................. ............... 1

1.2 Ban hi DE2 .............................................. .................................................. .... 2

Chng 2 Altera DE2 Ban ............................................. .................................................. ..............4

2.1 Giao din v thnh phn ............................................... .................................................. .....4

2.2 S khi ca Ban DE2 ........................................... ............................................. 5

Chng 3 DE2 Control Panel ............................................. .................................................. .......... 10

3.1 Control Panel ci t .............................................. .................................................. ........... 11

3.5 Cu trc chung ca DE2 Control Panel .......................................... ............................ 17

3.7 VGA Display Control .............................................. .................................................. ......... 20

Chng 4 S dng Ban DE2 ............................................ .................................................. ....... 24

4.1 Cu hnh FPGA Cyclone II ............................................ ......................................... 24

4.3 S dng Mn hnh 7-segment ........................................... ................................................. 30

4.4 Clock u vo ............................................... .................................................. ...................... 32

4.5 S dng cc module LCD ............................................. .................................................. ....... 33

4.6 S dng Header m rng ............................................. ................................................. 35

4.8 S dng 24-bit Audio CODEC .......................................... .............................................. 41

4.10 PS / 2 Serial Port ............................................ .................................................. .................... 42

4.11 Fast Ethernet iu khin Mng ............................................. ......................................... 43

4.13 Thc hin mt b m ha truyn hnh .............................................. ................................................ 46

4.14 S dng USB Host v thit b ............................................ .................................................. 46

4.15 S dng IrDA ............................................... .................................................. ........................ 48

4.16 S dng SDRAM / SRAM / Flash ........................................... .................................................. 49

Chng 5 V d v cc cuc biu tnh nng cao ............................................ .......................... 54

5.1 Nh my Cu hnh DE2 .............................................. .................................................. 54

5.2 TV Box din ............................................... .................................................. ..... 55

5.4 USB Device ............................................... .................................................. ....................... 59

5,5 Mt my Karaoke .............................................. .................................................. ........... 61

5.8 m nhc tng hp trnh din .............................................. ....................................... 66

Hnh 1.1 cho thy mt bc nh ca gi DE2.

Hnh 1.1. Cc DE2 ni dung gi.

Cc gi phn mm DE2 bao gm:

ba nha r rng cho hi ng qun tr

9V DC treo tng cung cp in

1.2 Ban hi DE2

Hnh 1.2. Chn trong hi ng qun tr DE2.

Altera Cng ty C phn 101

San Jose, California, 95134 USA Email: university@altera.com

Terasic Technologies s 356, Sec. 1, keo E. Rd. Thnh

ph Jhubei, Hsinchu County, i Loan, 302 Email: support@terasic.com

Arches Computing Unit 708-222 Spadina Ave

Toronto, Ontario, Canada M5T3A2 Email: DE2support@archescomputing.com

cu hi v chia s nhng v d thit k.

BBS din n: http://www.terasic.com/english/discuss.htm

Board DE2 Altera

2.1 Giao din v Linh kin

u ni v cc thnh phn ch cht.

Hnh 2.1. Cc DE2 bng.

Cc phn cng sau y c cung cp trn bng DE2:

Altera Cyclone thit b II 2C35 FPGA

Altera thit b Cu hnh Serial - EPCS16

4 Mbyte b nh Flash (1 Mbyte trn mt s hi ng)

9 n LED s dng mu xanh l cy

50-MHz dao ng v 27-MHz dao ng cho ngun ng h

24-bit audio CD-cht lng CODEC vi line-in, line-out, v micro-in jack cm

TV Decoder (NTSC / PAL) v kt ni TV-in

nng tin tin ca hi ng qun tr DE2.

2.2 S khi ca Ban DE2

Hnh 2.2. s khi ca hi ng qun tr DE2.

Sau y l thng tin chi tit hn v cc khi trong hnh 2.2: