Lab Manual

Digital Logic Design

CEL 120

Department of Computer Engineering

BAHRIA UNIVERSITY ISALMABAD

CEL-120 Digital Logic Design Lab Page 1

CEL-120 Digital Logic Design Lab Page 2
 LIST OF EXPERIMENTS

Exp No. Title Page No.

1 Implementation of AND, OR, NAND, NOR and NOT Gates 1

2 Implementation of a Circuit from Given Expressions 4

3 Implementation of Basic Gates using Universal Gates 6

4 Implementation of 3-Bit Parity Generator & Checker 10

5 Implementation of a Half Adder and a Full Adder using Gates

Implementation of 4-bit Adder and Subtractor using IC 74LS83 13

6 Implementation of a 4 to 1 MUX using Gates and using IC 74LS153 16

7 Implementation of a 2 to 4 Decoder 19

8 Implementation of SR Latches with and without Control Bit 21

9 Implementation of a D Latch and D Flipflop 23

10 Implementation of JK Flipflop and State Space 25

11 Verification of Functionality of AND, OR, NAND, NOR

and NOT Gate using Verilog with Test Bench 28

12 Implementation of a Half Adder and a Full Adder in Verilog 40

13 Implementation of an Up-Down Counter in Verilog 42

14 Implementation of an Odd Up/Down Counter using State Machine in Verilog 43

CEL-120 Digital Logic Design Lab

CEL-120 Digital Logic Design Lab
 EXPERIMENT 01
Implementation of AND, OR, NAND, NOR and NOT Gates
Objectives:
Demonstrate the operations of basic logic gates.
Use the following gates and draw their truth table.
7408 Quad 2-Input AND Gate
7432 Quad 2-Input OR Gate
7400 Quad 2-Input NAND Gate
7402 Quad 2-Input NOR Gate
7404 Hex Single-Input NOT Gate
Equipment /Tool:
Trainer, IC 7404, 7400, 7432, 7408, 7402
Background:
A logic gate is a circuit which has one or more inputs and single output. A logic gate is an
elementary building block of a digital circuit. Most logic gates have two inputs and one output.
At any given moment, every terminal is in one of the two binary conditions low (0) or high (1),
represented by different voltage levels. The logic state of a terminal can, and generally does,
change often, as the circuit processes data. In most logic gates, the low state is approximately
zero volts (0 V), while the high state is approximately five volts positive (+5 V).
For TTL 0 - 0.8V corresponds to 0 logic level and 2 5V corresponds to 1 logic level.
Procedure:
Connect the circuit according to the pin configuration of the ICs as mentioned in the datasheets
and check the truth tables.
Symbols:
Following are the symbols of the basic logic gates:

Lab Tasks
1) Verify the truth tables of all the ICs specified:

CEL-120 Digital Logic Design Lab Page 1

 74LS08 ( AND Gate ):
Y=A.B

Input Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
74LS32 ( OR Gate ):
Y=A+B

Input Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
74LS04 ( NOT Gate ):

Y=

74LS00 ( NAND Gate ):

Y=.

CEL-120 Digital Logic Design Lab Page 2

 74LS02( NOR Gate ):

Y= +

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 EXPERIMENT 02
Implementation of a Circuit from Given Expressions
Objective:
To implement a circuit from given expression, make its truth table, find its minterms. Now
Implement the circuit from the minterms again and verify the results with the initial given
expression.
F=X+.Y

Equipment /Tool:
Trainer, 74LS32 (OR), 74LS08 (AND), 74LS04 (NOT).

Figure 2. OR Gate IC 7432

Figure 1. AND Gate 7408

Figure 3. NOT Gate IC 7404

Procedure:
From the Expression given make the circuit on the trainer using ICs mentioned and fill in the
truth table.

X Y
. F

Now find the minterms of this expression and write it on the following blank
F= .

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Implement the above expression on the trainer and fill the following table:
X Y F
0 0
0 1
1 0
1 1

Now verify the results of both the tables. Are they both the same or not? And why?

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 EXPERIMENT 03
Implementation of Basic Gates using Universal Gates

Objectives:
Using two input NAND and NOR gates, construct the following
1. NOT
2. AND
3. OR
After doing this, implement the given expression on the trainer board.

Equipment /Tool:
Trainer, IC 74LS00, 74LS02.
Theory:
NAND and NOR gates are called universal gates because we can make any basic gate from
them by using the following circuits.
1) Implementation of Gates using NAND Gate only:
i) NOT Gate Behavior:

Input output
0 1
1 0

ii) AND Gate Behavior:

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 Input Output
A B Q
0 0 0
0 1 0
1 0 0
1 1 1

iii) OR Gate Behavior:

Input Output
X Y F
0 0 0
0 1 1
1 0 1
1 1 1

2) Implementation of Gates using NOR Gate Only:

Verify all the truth tables for all the gates.
i) NOT Gate Behavior:

A A
0 1
1 0

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 ii) AND Gate Behavior:

A B Q
0 0 0
0 1 0
1 0 0
1 1 1

iii) OR Gate Behavior:

A B F
0 0 0
0 0 1
1 0 1
1 1 1

Exercise in Lab:
1) Implement following expression using NOR Gate only.
2) Implement following expression using NAND Gate only.
F= + .

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Circuit diagram

Truth Table:
Input Output
X Y Z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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 EXPERIMENT 04
Implementation of 3-Bit Parity Generator & Checker
Objectives:
Implementation of 3-bit parity generator & checker.
Equipment/Tool:
Trainer, IC 74LS86, 74LS32, 74LS08, 74LS04.
Background:
A parity bit, or check bit, is a bit added to the end of a string of binary code that indicates
whether the number of bits in the string with the value one is even or odd. Parity bits are used
as the simplest form of error detecting code.
There are two variants of parity bits: even parity bit and odd parity bit. In case of even parity,
the parity bit is set to 1 if the count of ones in a given set of bits (not including the parity bit)
is odd, making the count of ones in the entire set of bits (including the parity bit) even. If the
count of ones in a given set of bits is already even, it is set to a 0. When using odd parity, the
parity bit is set to 1 if the count of ones in a given set of bits (not including the parity bit) is
even, making the count of ones in the entire set of bits (including the parity bit) odd. When the
count of set bits is odd, then the odd parity bit is set to 0.
Lab Tasks:
Using AND, OR, NOT gate ICs, implement 3-bit parity generator fill in the truth table
and make the corresponding circuit.
After this implement 3-bit parity generator and checker using XOR gate only (74LS86)

Pin Configuration of XOR (74LS86):

X Y F
0 0 0
0 0 1
1 0 1
1 1 0

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Exercise in Lab:
Fill the following truth table for even parity generator
X Y Z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Now from the table find the minterms and write the corresponding expression in the following
blank
P= .
From the expression make the corresponding circuit and implement it on the trainer board:

Now make the following circuit on the trainer and verify the following truth table:

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 X0 X1 X2 P
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Now implement the following circuit of even parity generator and fill the truth table:

X Y Z P C
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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 EXPERIMENT 05:
Implementation of a Half Adder and a Full Adder using gates. Implementation of 4-bit
Adder and Subtractor using 74LS83 & 74LS86.
Objectives:
To implement a half adder and a full adder using gates and implementing 4-bit adder and
subtractor using 74LS83 & 74LS86.
Equipment/Tool:
Trainer, IC XOR, IC-OR, IC-AND, IC74LS83 (4-bit adder), 74LS86(XOR).
Background theory:
A half adder is a combinational circuit that adds two binary inputs. It gives two outputs, S as
the sum and C as the carry of the inputs.
A full adder is a combinational circuit that adds three binary inputs X, Y and Z. The input Z is
the carry input from another addition. It gives two outputs, S as the sum and C as the carry of
the inputs.
The circuit for the adder/subtractor shown in figure 5.3 is used to do binary additions and
subtractions. If Cin=0, addition is performed and if Cin=1, subtraction is performed.

Tasks:
Write a truth table for a half adder, design a simplified circuit for it. Implement it on
trainer and verify the results.
Write a truth table for a full adder, design a simplified circuit for it. Implement it on
trainer and verify the results.
Fill in the truth table.
Design the complete circuit on the trainer and verify the results.
Procedure
Task 1 & 2
Fill in the following truth table of half adder and full adder and draw the circuit from them.

Table for Full Adder Table for Half Adder

A B C Sum Carry A B Sum Carry
0 0 0
0 0
0 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0
1 0 1 1 1
1 1 0
1 1 1

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Circuit Diagram:
i) Circuit diagram for Half Adder

Figure 5.1. Half Adder

ii) Circuit diagram for Full Adder

Figure 5.2. Full Adder

Task 3 & 4:
Following is the circuit diagram. Implement it on the trainer and verify the results:

Figure 5.3. Circuit for 4-bit Adder and Subractor

This is a 4-bit adder/subtractor circuit. FA is full adder. The operation depends upon Cin. If
Cin=0, addition is performed and if Cin=1, subtraction is performed.

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Pin Configuration of 74LS83:

Exercise in Lab:
Fill in the following truth table and verify your results and show it to the instructor:-
1)
A3 A2 A1 A0

B3 B2 B1 B0

S3 S2 S1 S0

2)
A3 A2 A1 A0

B3 B2 B1 B0

S3 S2 S1 S0

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 EXPERIMENT 06
Implementation of a 4 to 1 MUX using Gates and using IC 74LS153.
Objective:
To familiarize student with basic working of multiplexer and implementation of 4x1 mux.
Equipment / Tool:
Trainer, IC 74LS04 (NOT), 74LS32 (OR), 74LS08 (AND), 74LS153 (4 TO 1 MUX).
Background Theory:
A MUX is a combinational circuit that can be used to select data and produce it at the output.
They can be 2 to 1, 4 to 1, 8 to 1, 16 to 1, etc. It has a lot of applications. There are many
scenarios in which we have to select a particular data and produce it at the output.
Lab Tasks:
Write the truth table for a 2 to 1 MUX, design a circuit from it, implement it on the
trainer and verify the results.
Write down the truth table for a 4 to 1 MUX, draw the circuit, implement it on the
trainer and verify the results.
Use the IC 74LS153 (4 to 1 MUX) and verify the results.
Procedure
Following is the circuit for 2 to 1 MUX and truth table:

S B A Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1

Circuit Diagrams:
Draw the diagram of 4 to 1 MUX as follows:

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Fill in the following Truth Table:
S1 S0 X3 X2 X1 X0 Y
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

Implementing using 74LS153:

Following is the pin configuration extracted from the datasheet.
DUAL-IN-LINE Package

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 Function Table:

Select Inputs Data Inputs Strobe Output

B A C C1 C2 C3 G Y
0
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H

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 EXPERIMENT 07
Implementation of a 2 to 4 Decoder
Objectives:
Implementation of a 2 to 4 decoder using basic gates.
Equipment use:
Trainer, IC74LS04 (NOT),74LS11(Three input AND gate).
Background Theory:
A decoder is a combinational circuit that converts binary information from n codes to
2n (two raised to the power n) unique outputs. They can be 2 to 4, 3 to 8, 4 to 16 etc. It
has a lot of applications. There are many scenarios in which we must use such devices.
Lab Tasks:
Write truth table for a 2 to 4 decoder with enable bit in it.
Draw the gate diagram of a 2 to 4 decoder.
Implementation of a 2 to 4 decoder on trainer using three input AND gate with enable
bit as active low and verify with truth table.
For three input AND gate use 74LS11.
Procedure:
Fill in the truth table for a 2 to 4 decoder with an active low enable bit:
E S1 S0 D3 D2 D1 D0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
1 X X X X X X

Pin configuration of 74LS11:

Following is the pin diagram of three input AND gate IC:

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Following is the truth table for three input AND gate IC:

INPUTS OUTPUTS
A B C Y
X X L L
X L X L
L X X L
H H H H

H=HIGH Logic level

L=LOW Logic level
X=Either LOW or HIGH Logic level

CIRCUIT DIAGRAM:
Draw a 2 to 4 decoder with active low pin:

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 EXPERIMENT 08
Implementation of SR Latches with and without Control Bit
Objectives:
Implementation of SR latches.
Equipment/Tool:
Trainer, IC 74LS02 (NOR Gate), 74LS00 (NAND Gate).
Background Theory:
The SR latch is a circuit constructed from two cross-coupled NOR or NAND gates. It
is derived from the single-loop storage element. The latch has two inputs labeled as S for set
and R for reset. When Q=1 and =0, it is said to be in the set state. When Q=0 and =1, it is
said to be in the reset state.
The operation of a basic NOR and NAND latches can be modified by providing an addition
control bit that determines when the state of the latch can be changed.
Lab Tasks:
Draw the circuit of SR latches with NAND and NOR gates both. Implement the circuits
and verify the results.
Implementation of SR latches with control bit.
Procedure
Fill in the following truth tables of SR latches for both NAND and NOR
implementation and draw the circuits from them:

Implementation with NOR

S R Q QBAR
1 0 1 0
0 0 Latch(Previous) Latch(Previous)

0 1 0 1
0 0 Latch(Previous) Latch(Previous)
1 1 Undefined Undefined

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 Implementation with NAND Gates
S R Q QBAR
0 1 1 0
1 1 Latch(Previous) Latch(Previous)

1 0 0 1
1 1 Latch(Previous) Latch(Previous)

0 0 Undefined Undefined

Implementation of SR Latches with Control Bit

Fill in the following truth tables of SR latches with a control bit.

Implementation with NAND AND CONTROL BIT

C S R Q QBAR
0 X X Latch Latch
1 0 0 Latch Latch
1 0 1 0 1
1 1 0 1 0
1 1 1 unstable Unstable

Circuit Diagram:
Draw the circuit diagram for SR latch with a control bit with only NAND gates.

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 EXPERIMENT 09
Implementation of a D Latch and D Flipflop
Objective:
Implementation & Verification of the functionality of a D Latch and D Flipflop
Tasks:
Write The truth table for a D Latch.
Design and implement the D Latch on the trainer.
Verify the results with the truth table.
Write the truth table for D Flipflop
Design and implement the D Flipflop on the trainer.
Verify the results with the truth table.

Equipment Used:
Trainer, NAND gates (74LS00), NOT Gate (74LS04), 7474 (D-Flipflop)
Background Theory:
In order to eliminate the undesired state in the SR Latch is to ensure that inputs S & R are never
equal to 1 at the same time. This is done in the D Latch. This latch has only two inputs: D
(Data) & C (Control), the D Latch receives its designation from its ability to hold data in its
internal storage.
Exercise in Lab:
Truth Table for D latch:
E or C D Q Q
0 X Latch
1 0 1 0
1 1 1 1

Circuit Diagram:
Draw the circuit for D Latch.

Figure 9.1. D Latch with Enable (control)

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Implementation of D Flipflop

Figure 9.2. D-Flipflop IC 7474

Theory:
The D flipflop is almost the same as the SR flipflop but with a difference that it has only two
input, D (data) and C (clock).
Exercise in Lab:
Fill in the truth table for D Flipflop.
D Next Sate of Q
0
1
Circuit Diagram:
Draw the circuit for D Flipflop

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 EXPERIMENT 10
Implementation of JK Flipflop
Objective:
Implementation & Verification of state machine using JK Flipflop
Equipment Used:
Trainer, 74LS76 (JK flipflop), basic gates.
Background Theory:
The basic concept in the implementation if the state machine is that we should know about the
truth table, excitation table of the JK flipflop and transition table. This lab contains almost all
the concepts that have been taught during the DLD course.
Tasks:
Write the truth table for JK Flipflop
Write the excitation table for 2 bit JK Flipflop
Write the Transition table.
Write the K-Map for all flipflops
Write the equation from the table
Design the circuit

Procedure:
Following is the state machine that must be implemented.

Truth Table for JK flip flop:

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Fill in the following table for the JK Flipflop
J K Next Sate of Q
0 0
0 1
1 0
1 1

Excitation Table:
Fill in the following excitation table according to the truth table for JK Flipflops
Q(t) Q(t+1) J K
0 0
0 1
1 0
1 1

Transition Table:
Fill in the following transition table
P.State Input=x N.State JB KB JA KA Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

K-Maps:
Fill in the following K-Maps for the following outputs
JB:
00 01 11 10
X 0
X 1

KB:
00 01 11 10
X 0
X 1

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JA:
00 01 11 10
X 0
X 1

KA:
00 01 11 10
X 0
X 1

OUTPUT:
00 01 11 10
X 0
X 1

Equations:
Write the equations derived from the K-Maps. Fill in the following Blanks.

JB: .

KB: .

JA: .

KA: .

Output: .
Circuit Diagram:
Draw the resulting circuit diagram from the equation give above:

CEL-120 Digital Logic Design Lab Page 27

 EXPERIMENT 11:
Verification of Functionality of AND, OR, NAND, NOR and NOT gate using Verilog
with Test Bench
Objective:
Understand Basics of Verilog.
Verification of functionality of AND, OR, NAND, NOR and NOT gate using Verilog with test
bench on Xilinx ISE synthesizer.
Equipment/Tool:
ISE-Xilinx (Integrated Synthesis Environment)
Lab Tasks:
Implementation of AND, OR, NAND, NOR and NOT gates on Xilinx ISE synthesizer
using gate.
Background:
Verilog is a Hardware Description Language (HDL) which is used to model electronic systems.
It provides the designer entry into the world of large, complex digital systems design. The
Verilog language provides the digital system designer with a means of describing a digital
system at a wide range of levels of abstraction, and, at the same time, provides access to
computer-aided design tools to aid in the design process at these levels. It also fulfils the need
for verifying the design for functionality and timing constraints like propagation delay setup
and hold times. The components of the target design can be described at different levels with
the help of constructs in Verilog.
1. Circuit Level: MOS switch is the basic element which can be used to build basic circuits like
inverters, logic gates, 1-bit dynamic and static memories.
2. Gate Level or structural level: Design is carried out in terms of basic gates. All basic gates
are available as ready modules called primitives. Primitives can be incorporated into design
descriptions directly.
3. Data Flow Level: All possible operations on signals and variables are represented in terms
of assignments.
4. Behavioral Level: This level describes a system by concurrent algorithms and the design
description looks like a C program. Compactness and the comprehensive nature of the design
description make the development process fast and efficient. Functions, Tasks and Always
blocks are the main elements.
There are two types of code in most HDLs:
Structural, this is a verbal wiring diagram without storage.
assign p= q & r | s;
assign s = t & (~r);
In structural code, the order of the statements does not matter. Changing t will change p.
Procedural, which is used for circuits with storage, or as a convenient way to write conditional
logic.
always @ (posedge clk) // Execute the next statement on every rising clock edge.
count < = count+1;

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LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG
Verilog has its own constructs and conventions. Any source file in Verilog is made up of
number of ASCII characters.

Keywords
The keywords define the language constructs. All keywords in Verilog are in small letters and
require to be used as such. Some of the examples are:
module - signifies the beginning of a module definition.
endmodule - signifies the end of module definition.
begin - signifies the beginning of block of statements.
end - signifies the end of a block of statements.
if - signifies a conditional activity to be checked.
assign - assigns a value or an expression to a net or variable.
Numbers
The numbers can be of integer type or real type. Integer Numbers Number storage is defined
as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal. The
representation has three tokens with an optional sign preceding it. Numbers may be sized or
unsized. Unsized integers default to at least 32 bits.
Syntax: size base value
Examples:

Logical Values:-
Verilog uses a 4 value logic system for modelling.

Operators
They are of three types.
Unary: the unary operator is associated with a single operand. E.g. b = ~a
Binary: the binary operator is associated with two operands. E.g. c = a & b
Ternary: the ternary operator is associated with three operands. E.g. a = b? c : d
Operator Precedence
The operator precedence is shown below. The top of the table is the highest precedence, and
the bottom is the lowest. Operators listed on the same line have the same precedence. All
operators associate left to right in an expression. Ternary operator is exception to this; it

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associates from right to left. Parentheses can be used to change the precedence or clarify the
situation.

Data Types
Verilog has two major data type classes:
1) Net Data type
2) Variable data type.
Nets
Net data types are used to make connections between parts of a design. Nets reflect the value
and strength level of the drivers of the net or the capacitance of the net, and do not have a value
of their own. A net can be specified in different ways.
Wire
A wire (or net) represents a physical wire in a circuit and is used to connect gates or modules.
The value of a wire can be read, but not assigned to, in a function or block. A wire does not
store its value but must be driven by a continuous assignment statement or by connecting it to
the output of a gate or module.
Syntax wire [msb: lsb] wire_variable_list;
Example wire c; //declare a wire c
Variable data types
Variable data types are used as temporary storage of programming data. Variables can only be
assigned a value from within an initial procedure, an always procedure, a task or a function.
Variables can only store logic values; they cannot store logic strength. Variables are un-
initialized at the start of simulation, and will contain logic X until a value is assigned. Variables
can be declared trough a keyword reg.
Reg
A reg (register) is a data object that holds its value from one procedural assignment to the next.
They are used only in functions and procedural blocks. A reg is a Verilog variable type and
does not necessarily imply a physical register.
Syntax reg [msb: lsb] reg_variable_list;
Example reg a; // single 1-bit register variable

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reg [7:0] r_vector; // an 8-bit vector; a bank of 8 registers.
Examples:
wire [3:0] a ; /* a is a four bit vector of net type; the bits are designated as a[3] , a[2], a[1] ,
a[0].*/
reg [2:0] b; /* b is a vector of reg type ; the bits are designated as b[2] , b[1] , b [0] */
wire [-2:2] d ; /* d is a 5 bit vector with individual bits designated as d[-2] ,d [-1], d[0] , d[1]
, d[2].*/
Modules
Verilog HDL models are represented as modules. A module is the principal design entity in
Verilog. The first line of a module declaration specifies the name and port list (arguments). The
next few lines specify the input/output type (input, output or inout) and width of each port.
The default port width is 1 bit. Then the port variables must be declared wire or reg. The default
is wire. Typically inputs are wire since their data is latched outside the module. Outputs are
type reg if their signals were stored inside an always or initial block.
Syntax

module module_name (port_list);

input [msb: lsb] input_port_list; //input ports output [msb: lsb] output_port_list; //output ports
inout [msb: lsb] inout_port_list; // bidirectional ports
... statements ...
Example:
endmodule

module add_sub(add, in1, in2, sum_12);

input add; // defaults to wire
input [7:0] in1, in2; //wire by default
output [7:0] sum_12;
reg sum;
... statements ...
endmodule

Continuous Assignment
The continuous assignment is used to assign a value onto a wire in a module. It is the normal
assignment outside of always or initial blocks. Continuous assignment is done with an assign
statement or by assigning a value to a wire during its declaration. The order of assign statements
does not matter. A change in any of the right-hand-side inputs will immediately reflect on the
left-hand-side output.
Syntax
wire wire_variable = value;
assign wire_variable = expression;
Example:

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wire [1:0] a = 2b01; // assigned on declaration
assign b = c & d; // using assign statement
assign d = x | y; // The order of the assign statements does not matter.
Behavioral Modeling
Behavioral or procedural statements in Verilog are used to model a design at a higher level of
abstraction than the other levels. Procedural assignments are used within Verilog procedures
(always and initial blocks). Only reg variables and integers can be placed left of the = in
procedures. The assignment may be Blocking or non-Blocking.
variable = expression;
Blocking procedural assignment. Expression is evaluated and assigned when the statement is
encountered. In a beginend sequential statement group, execution of the next statement is
blocked until the assignment is complete. In the sequence ;
begin
m=n;
n=m;
end

Note: The first assignment changes m before the second assignment reads m.
variable <= expression;
Non-blocking procedural assignment. Expression is evaluated when the statement is
encountered, and assignment is postponed until the end of the simulation time-step. In a
beginend sequential statement group, execution of the next statement is not blocked; and
will be evaluated before the assignment is complete.
In the sequence ;
begin
m<=n;
n<=m;
end

Note: Both assignments will be evaluated before m or n changes.

Procedures: Always and Initial Blocks
The always block is the primary construct in RTL modeling. Like the continuous assignment,
it is a concurrent statement that is continuously executed during simulation. This also means
that all always blocks in a module execute simultaneously. The always block is triggered to
execute by the level, positive edge or negative edge of one or more signals (separate signals by
the keyword or). A double-edge trigger is implied if you include a signal in the event list of the
always statement. The single edge-triggers are specified by posedge and negedge keywords.
Example: always @(a or b); // level-triggered; if a or b changes levels
always @(posedge clk); // edge-triggered: on +ve edge of clk
The initial block is like the always block except that it is executed only once at the beginning
of the simulation. It is typically used to initialize variables and specify signal waveforms during
simulation. Initial blocks are not supported for synthesis.
Example:

CEL-120 Digital Logic Design Lab Page 32

 inital
begin
clr = 0; // variables initialized at
clk = 1; // beginning of the simulation
end

inital // specify simulation waveforms

begin
a = 2b00; // at time = 0, a = 00
#50 a = 2b01; // at time = 50, a = 01
#50 a = 2b10; // at time = 100, a = 10
End

Procedure:
We are going to write a simple program in verilog for simple AND gate
To enter this design, first start the Project Navigator of Xilinx ISE 12.1 by clicking on the
Project Navigator Icon, as shown in Figure 11.1

Figure 11.1

CEL-120 Digital Logic Design Lab Page 33

 The Project Navigator will then display the last project the tool worked on as shown in Figure
11.2

Figure 11.2
For a new project, select the File menu and select New Project as shown in Figure 11.3. This
window allows the user create a New Project. For the AND gate design example, we would
like to create a New Project
A New Project window will then appear. It will have the following fields: Project Name (Name
of project), Project Location (location to store files), and Project Device Options. Name the
project and place it as your desire, enter Project Name: myand (in our case)

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 Figure 11.3
The targeted FPGA device is a Xilinx Spartan 3 XC3S200 family device, specifically a
XC3S200FT256 FPGA (it is written directly on the device). Enter the following details:
o Family: Spartan3
o Device: SX3S200
o Package: FT256
o Speed: -4
As shown in Figure 11.4, click Next and the summary will be displayed as shown on Figure
2.5, click Finish

CEL-120 Digital Logic Design Lab Page 35

 Figure 11.4
Either right click on the Project source files area and a drop box will pop up or select the Project
menu on Xilinx Project Navigator, select New Source, a New Source Wizard will pop up as shown,
select Source Type as Verilog Module and Name the file and location of the source file. Click Next,
and define the module by specifying the ports of the module(this part this be done later on as well
if input and output ports are not designed during this phase), click next and a summary of the new
source file will be displayed, click Finish as shown in Figures 11.5 to 11.8.

CEL-120 Digital Logic Design Lab Page 36

 Figure 11.5

Figure 11.6

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 Figure 11.7

Figure 11.8

In the case of our simple AND gate example, we enter following code as shown in Figure 11.9.

CEL-120 Digital Logic Design Lab Page 38

 Figure 11.9
Enter the code as shown and Synthesize the code as shown, right click on Systensize-XST and click
Run from the drop down list as shown in Figure 11.10.

Now write testbench and show simulation

Lab Task:
Implement NAND, OR, NOR and NOT gate and verify it using Testbench.

CEL-120 Digital Logic Design Lab Page 39

 EXPERIMENT 12
Implementation of a Half Adder and a Full Adder in Verilog
Objectives:
To implement a half adder and a full adder.
Equipment/Tool:
Xilinx ISE
Lab Tasks:
Write a truth table for a half adder, design a simplified circuit for it. Implement it on
Xilinx ISE synthesizer.
Write a truth table for a full adder, design a simplified circuit for it. Implement it on
Xilinx ISE synthesizer.
Procedure:
Fill in the following truth table of half adder and full adder and Write Verilog code for them.
Table of Full Adder Table for Half Adder
A B C Sum Carry
A B Sum Carry
0 0 0
0 0
0 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0
1 0 1 1 1
1 1 0
1 1 1

Circuit Diagram:
i) Circuit diagram for Half Adder

Figure 12.1. Half Adder

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 ii) Circuit diagram for Full Adder

Figure 12.2. Full Adder

Code for Half Adder and Full Adder:
i) HALF ADDER
module halfadder (Cout, sum,a,b)
input a,b;
output Cout, sum);
assign sum = a ^ b;
assign Cout = a & b;
endmodule

Half Adder Gate level Description

module halfadder (Cout, sum,a,b)
input a,b;
output Cout, sum;
xor (sum, a, b);
and (Cout ,a,b);
endmodule

ii) FULL ADDER

module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = (a & b) | (a & ci) | (b & ci);
endmodule

Full Adder with Gate level Description

module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co);
wire NET1, NET2, NET3;
xor ( NET1, a, b ); xor( s , NET1, ci );
and ( NET2, NET1, ci);
and ( NET3, a, b );
or ( co, NET2, NET3); endmodule

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 EXPERIMENT 13
Implementation of an Up-Down Counter in Verilog
Objectives:
To implement an up-down counter.
Equipment/Tool:
Xilinx ISE
Background:
Up-down counter is a type of counter which can count both in increasing (up) and decreasing
(down) count order. Here is a model Verilog code for 4-bit Up-down counter.
Procedure:

Module counter (Q , clock, clear);

output [3:0] Q;
input clock, clear;
reg [3:0] Q;
always @ (posedge clear or negedge clock)
begin
if(clear)
Q<=4d0;
Else
Q<=Q+1;
end
endmodule

Task:
Modify above code which will perform function given below.
I. Add one bit input name updw to the sensitivity list if updw == 1 the counter will count
upward e.g. 1 2 3 and when updw =0 it will count down e.g. 3 2 1 0.

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 EXPERIMENT 14:
Implementation of an Odd Up-Down Counter using State Machine in Verilog
Objectives:
To implement an up-down counter using state machine.
Equipment/Tool:
Xilinx ISE
Background:
In this lab, you will design a 4-bit Up/Down Counter using several methods of implementation.
The Up/Down counter has a clock input, clk, a reset input, rst, count enable input, cen, and an
up/down control input, dir. The counter has a 4-bit output, count, which outputs the current
count as a 4-bit binary number. The Even-Odd counter operates as follows:
When rst = '1', the count should be reset to "0000".
Otherwise, if the cen = '1', on every clock cycle the counter should count up when dir =
'1' and count down when dir = '0'.
If cen = '0' the counter should keep the present value.
Procedure:
The following provides the steps that you must follow to complete this lab.
Behaviorally design the 4-bit Up/Down Counter as a Finite State Machine (FSM). You
FSM design should consist of two always procedures. The first always procedure,
should implement the state register. The second always procedure should implement
the the FSM control logic. In the design of the FSM control logic, you must use
a case statement to describe the combinational behavior associated with each state. Use
the following module template for the FSM design:
module updown_Counter_FSM(clk, rst, cen, dir, count);
input clk, rst, cen, dir;
output [3:0] count; // this is how you declare a 4 bit signal initial
Verilog
reg [3:0] count;

// parameter used to define states

// Define the remaining states for your FSM here
parameter S_0 = 4'b0000,
S_1 = 4'b0001,

// state registers for current state and next state

reg [3:0] currentstate;
reg [3:0] nextstate;

// state register procedure with asynchronous reset

always @(posedge rst or posedge clk)
begin
if (rst==1) // initial state
currentstate <= S_0;
else
currentstate <= nextstate;
end

CEL-120 Digital Logic Design Lab Page 43

 // combinational logic procedure for FSM control logic
always @(currentstate or cen or dir)
begin
case (currentstate)
S_0: begin
// complete logic for state S_0
nextstate=S_1;
end

S_1: begin

// complete logic for remaining states

nextstate=S_2;
end
endmodule
TASK:
Test your behavioral FSM design by simulating the functionality of the Even-Odd Up/Down
Counter for several possible control configurations. You must test the following aspects of your
counter design:
Fully test the upward counting of the counter through all possible values.
Fully test the downward counting of the counter through all possible values.
Test your counter properly resets to "0000" whenever rst = '1'. Be sure to test the reset
functionality when the count is at a non-zero number.
Test that whenever cen = '0' the counter retains its present value. Be sure to test the
count enable when the count is at a non-zero number.

CEL-120 Digital Logic Design Lab Page 44