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International Journal of Research in Computer Engineering and Electronics.

Page # 1 ISSN 2319-376X


VOL :2 ISSUE : 2 (June: 2013)

Design of a robust verification environment for AMBA AHB


System in Universal Verification Methodology
[1] [2]
Bhaumik Vaidya Jaydeep Bhatt

ABSTRACT:

There are many interconnect buses that are widely In this paper, Process for developing verification
used in the industry like AMBA, Wishbone, environment for AMBA AHB system in Universal
CoreConnect, Avalon etc. AMBA is most verification Methodology has been shown with the
proffered among all of them because it has a
simulation results of that.
hierarchy of buses with AHB (Advance high
performance bus) can be connected to high
performance peripherals and APB (Advance 2. AHB in UVM
Peripheral Bus) that can be connected to low
performance peripherals. AHB can be used in high The figure below indicates the overall structure of
performance and high bandwidth system because of AHB verification environment. It has two agents.
its high performance features like burst transfer and AHB master agent and AHB slave agent. Both of
split transaction. Today, major time in ASIC design them have driver, monitor and sequencer
flow is spent on verification. So there is a need of a
instantiated in it. Any individual agent can be
robust and reusable verification. Universal
Verification Methodology was introduced just to connected to dut via interface or AHB master and
fulfill that need. More over it is supported by all slave agents can communicate with each other
three major simulator vendor in industry. So in this through well defined transaction level modelling.
paper the process of developing verification
In AHB environment we can configure number of
environment for AMBA AHB master and slave
component is shown. master and slave agents to be instantiated along
with mapping address for each slave. Here only
Index Terms: AMBA, AHB, System on chip , one master and one slave agent is used. The
AHB master, AHB Slave, UVM. ahb_test class will define which sequences to run
on ahb master and slave. By that it will configure
1.INTRODUCTION the whole testbench environment. The following
Today, most of the chips use AMBA AHB bus as a sections will describe the development of ahb
system backbone buses because of its high
master, slave agents, interface and transaction
performance features. Most of the time in overall
chip design is spent on verification. So there is a that is common to both the agents. Here single
growing demand for robust and reusable master and slave module is used so there is no
verification environment. Universal Verification need for the arbiter. Also decoder module to
Methodology was developed to help in building select particular slave is added in the interface.
reusable and robust verification environment. It
has several features that help in improving
verification.

[1] Bhaumik Vaidya is currently in Dept of Electronics
Enginnering Gujarat Technological University,Gandhinagar,
Gujarat, India.

[1] Jaydeep Bhatt is currently in Dept of Electronics


Enginnering Gujarat Technological University,Gandhinagar,
Gujarat, India. Figure 1 AHB in UVM testbench Architecture

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International Journal of Research in Computer Engineering and Electronics. Page # 2 ISSN 2319-376X
VOL :2 ISSUE : 2 (June: 2013)

3. AHB TRANSACTION

Transaction or sequence item is the packet that constraint c_transmit_delay {


uvm components use to communicate with each
transmit_delay <= 10 ;
other. It is a collection of all AHB signals or data
items. Master and slave sequences use this }
sequence item, randomize it and form a series of
sequences to check particular behavior of dut. constraint c_data_size {
Transaction class is extended from uvm_seq_item
class. Code for the transaction class is shown hrdata.size() == 16;
below:
hwdata.size() == 16;
class ahb_transfer extends uvm_sequence_item;
}
rand bit [31:0] haddr;
In this class some of the signals are define using
rand keyword to randomize it from the top
rand ahb_read_write_enum hwrite;
module. Some of the signals are also constrained
to generate a particular group of values
rand bit[2:0] hsize;

rand bit [31:0] hwdata[]; 4. AHB INTERFACE

rand bit [2:0] hburst; Interface is used to connect uvm components to


the device under test. It is set in the configuration
rand bit [31:0] data base of UVM from top module definition and
hrdata[]; fetched whenever necessary in uvm components.
It contains the definition of physical ports that are
bit hready ; to be connected to dut. Here only one master and
slave are there so decoder code is also included in
rand bit [1:0] hresp ;
interface module. It also contains some assertions
bit [1:0] htrans ; or properties that need to be checked on every
positive edge of the clock. Few assertions are
rand int unsigned transmit_delay shown below:
= 0;

string master = "";


1) Once the grant signal is given to any
string slave = ""; master, the value of haddr, hsize and
hburst should not be unknown.
int size ;

bit [3:0] wait_state[]; assertAddrUnknown:assert property (

disable iff(!has_checks)

constraint c_hwrite { ($onehot(hgrant)|->


!$isunknown(haddr)))
hwrite inside { READ, WRITE };
else
}

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VOL :2 ISSUE : 2 (June: 2013)

$error("ERR_ADDR_XZ\n Address went to X or Z generate htrans value and next address value
during Address Phase"); depending on the value of hsize and hburst.

ahb_master_monitor
This component is used to monitor the signals on
2) Reset must be asserted for at least three
the interface. It is a passive component and will
clock cycles.
not drive any dut signals. It is used to collect
coverage information and check that data has
assertResetFor3Clocks: assert property ( been correctly read or not. Simple example of
covergroup define in monitor is described below:
disable iff(!has_checks)

($rose(hreset_l) |=> hreset_l[*2]))


covergroup cg;
else
coverpoint req.hwrite ;

$error("ERR_SHORT_RESET_DURING_TEST\n", coverpoint req.hburst {

"Reset was asserted for less than bins hbursts = {0 ,1, 2,3};}
3 clock cycles");
coverpoint req.hsize {
5. AHB MASTER AGENT
bins hsizes = {0,1,2};}
The ahb master agent is the uvm component that
endgroup
contains the driver, monitor and sequencer for ahb
master. Every ahb master interface will need one During simulation it will monitor these signals and
master agent. So in multiple master system, there check if all the values have been covered or not.
will be as many agents as number of masters.
Following section will describe the development of ahb_master_sequencer
three agent components and also sequence that This is a static uvm component on which
will run on the sequencer. sequences are run. It has a export which is
connected to port of the driver. It gives the
ahb_master_driver sequences to the driver whenever it demands.
The ahb_master_driver takes the transaction from
the sequencer through its port and convert it into ahb_master_seq_lib
the pin level activity that is understood by the dut. In this class, all the sequences are defined by
It supports all the features of ahb master. There grouping or randomizing sequence items. There
are few tasks defined in run phase of the driver are many sequences defined like read byte, half
that perform this function. Reset task is used to word, word with different burst length. Same for
reset all the signals in the interface when transfer write operation. Then combining read and write
is completed. Arbitrate_for_bus task is used to operation in read after write sequence. This class
send the request signal to the arbiter for bus. It is built by extending uvm_sequence class. One
will wait in this task until bus is granted. After that simple sequence isshown below as a example.
it will go into drive_address_phase task where
address and control information of the burst is class read_byte_seq extends ahb_base_sequence;
transferred on the bus. Then it will go into
function new(string name="read_byte_seq");
drive_data task. In this task it will transfer the data
depending on the value of burst. It will also super.new(name);

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VOL :2 ISSUE : 2 (June: 2013)

endfunction Result of AHB master in UVM


The ahb master made in UVM is connected to
ahb_sram_slave RTL code written in Verilog to
check the behavior. Here read after write
`uvm_object_utils(read_byte_seq)
sequence is run on the sequencer which will first
rand bit [31:0] start_addr; write four beat burst into the memory then read
the same location from memory. The simulation
rand int unsigned transmit_del = 0; results for that are shown in figure below.

constraint transmit_del_ct { (transmit_del <= 10);


}

virtual task body();

`uvm_do_with(req,

{ req.haddr == start_addr;

req.hwrite == READ;

req.hsize == 0;

req.hburst == 0;

req.transmit_delay == transmit_del; } )

get_response(rsp);
Figure 2 AHB master in UVM
`uvm_info(get_type_name(),

$sformatf("%s read : haddr = `x%0h, hrdata[0] 6. AHB SLAVE AGENT


= `x%0h",
The ahb slave agent is the uvm component that
get_sequence_path(), rsp.haddr, rsp.hrdata[0]), contains the driver, monitor and sequencer for ahb
slave. Every ahb slave interface will need one slave
UVM_HIGH);
agent. So in multiple slave system, there will be as
endtask many agents as number of slaves. Following
section will describe the development of three
agent components and also sequence that will run
on the sequencer.
endclass : read_byte_seq
ahb_slave_monitor
This component is a passive component in the
uvm_do_with is a built in method which is used to agent which will constantly monitor the activity on
randomized transaction with a particular value as the interface. When it will detect hsel signal for it,
shown in code. it will collect address information in case of read
transfer and address and data information for
write transfer. It is connected to the port on the
sequencer. So when it collects this information it

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VOL :2 ISSUE : 2 (June: 2013)

will notify the sequencer to start read or write


sequence according to the transfer started by the
master. It will also collect coverage information
and check data has been correctly read or not.

ahb_slave_sequencer
This is a static uvm component on which
sequences are run. It has a export which is
connected to port of the driver. It gives the
sequences to the driver whenever it demands.

ahb_slave_driver
It is used to transfer response and hready signal
back to the dut. It also sends the data in case of
the read transfer. It receives appropriate
sequence from the sequence library and it Figure 3 AHB Slave in UVM
converts it into pin level activity understood by the
dut.
7. CONCLUSION
ahb_slave_seq_lib
Over the years AMBA has continued to provide
In this class memory read and write sequence for
state-of-the-art solutions for SoC interconnects
ahb slave has been defined. It contains the
and most of the time spent in SOC design is on
memory in which data will be stored in case of
verification. So Universal Verification Methodology
write transfer and read from in case of read
was built to help in developing robust and reusable
transfer. It will generate random data if no write
development. It helps in reducing time for
has taken place on that memory location. It has
verification. In this paper Process for developing
one parameter which can be varied for providing
verification environment for AHB system is shown.
the delayed response by keeping hready low for
This environment can be plugged into any
that number of cycles.
environment where AHB bus is used as a system
AHB slave simulation results bus.
The simulation result for ahb slave connected to
8.ACKNOWLEDGEMENT
ahb master via transaction level modeling is shown
below. Again read after write sequence is run on
the master and memory sequence is run on the This work was greatly supported by Gujarat
slave. In case of read transfer slave provides one Technological University and Seer Akademi by
cycle delay response by keeping hready low for providing state of the art tools like VCS and Design
one cycle. Compiler from Synopsys

9.REFERENCES:

[1] AMBA specification, version 2.0

[2] Hu Yueli, Yang Ben Building an AMBA AHB compliant


Memory Controller

[3]AHB Example AMBA System, Technical Reference


Manual, ARM Inc.

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International Journal of Research in Computer Engineering and Electronics. Page # 6 ISSN 2319-376X
VOL :2 ISSUE : 2 (June: 2013)

[4] Priyanka Gandhani, Charu Patel Moving from AMBA AHB to


AXI Bus in SoC Designs: A Comparative Study, 2011

[5]UVM users manual from Accellera

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