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Logic Gates

4.1 Introduction

Logic gates are the most fundamental digital circuit that can be constructed from diodes, transistors and registers connected in such a way that circuit output is the result of basic logic operation (OR, AND, NOT) performed on the inputs.

A logic gate is an electronic device with one output and one or more inputs where the output always depends on the input combinations.

Logic symbols used to represent the logic gates are in accordance with ANSI/IEEE standard 91-1984. This standard has been adopted by private industry and the mil- itary for use in the internal documentation as well as published literature.

 Note: 1. AND, OR, NOT gates are called Basic Gates. 2. NAND and NOR gates are called universal gates, because by using only NAND gates or by using only NOR gates, we can realise any logic gate or any basic logic circuit. 3. Special gates are EXCLUSIVE-OR (XOR) & EXCLUSIVE-NOR (X-NOR) gate. 4.2 Types of Logic System (a) Positive level logic system (b) Negative level logic system

4.2

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Positive level logic system

In positive level logic system, the most positive voltage level represents the logic 1-state and the most negative voltage level represents the logic 0-state.

1 (High)

0 (Low)

Fig. 4.1 Positive level logic

For example,

Table 4.1 Table showing different logic levels

 LOGIC 0 LOGIC 1 0 V 5 V -2 V +3 V -7 V -2 V +2 V +7 V

Negative level logic system

In a negative level logic system the most positive voltage level represents the logic 0-state and the most negative voltage level represents the logic 1-state.

High 0

Low 1

Fig. 4.2 Negative level logic

For example,

Table 4.2 Table showing different logic levels

 LOGIC 1 LOGIC 0 0 V 5 V -2 V +3 V -7 V -2 V +2 V +7 V

The effect of changing from one logic designation to other is equivalent to complementing the logic function. The best way of converting the logic designa- tion is that all zeros are replaced by 1 and vice versa, in the truth table.

Logic Gates

4.3

For example, the truth table for AND gate for both the logics is given below.

Truth table for positive

logic AND gate

Truth table for negative

logic AND gate

Table 4.3 Truth table

Input

Output

A

B

F=A.B

0

0

0

0

1

0

1

0

0

1

1

1

Table 4.4 Truth table

Input

Output

A

B

F=A.B

1

1

1

1

0

1

0

1

1

0

0

0

Note: By looking at the Tables 4.3 and 4.4, it can be concluded that negative logic AND gate is same as positive logic OR gate.

4.3 Not Gate (Inverter)

The NOT gate performs the basic logic functions called complementation or in- version. It has one input and one output. Its output logic level is always opposite to the logic level of the input.

In terms of binary bits, it changes a ‘1’ to ‘0’ and a ‘0’ to ‘1’.

Symbol

F
A

Presence of small circle called bubblealways

A

F denotes inversion

Fig. 4.3 Symbol of NOT gate

Truth table of NOT gate

Table 4.5 Truth table of NOT gate

Input

Output

A

F

0

1

1

0

FACT: Common emitter (BJT) ampliﬁer is used to obtain the logical opera- tion of inverter

4.4

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Timing diagram of NOT gate

Timing diagram: It is basically a graph that accurately displays the relationship between input and output waveforms with respect to each other on a time scale.

Input waveform
Output waveform
t

Fig. 4.4 Timing diagram of NOT gate

Logic expression

If A is input, then output,

F = A

4.4 AND Gate

The AND gate may have two or more input but has only a single output. An AND gate produces a HIGH (logic 1) output only when, all the inputs are HIGH. The output is LOW, when any of its input is LOW.

Symbol

A
F
B
Fig. 4.5 2-input AND gate

Truth table of 2-input AND gate

Table 4.6 Truth table for AND gate

Input

Output

A

B

F

0

0

0

0

1

0

1

0

0

1

1

1

Note: Boolean multiplication is same as AND operation

Logic Gates

4.5

Timing diagram of 2-input AND gate

A
B
F
t

Fig. 4.6 Timing diagram of 2- input AND gate

Logic expression

For a 2-input AND gate having inputs A & B, the output, F is given

F = A.B

Similarly for 3 input AND gate with inputs A, B, & C the output is given as

F = A.B.C

4.5 OR Gate

The OR gate may have two or more inputs, but has only a single output.

The OR gate produces a HIGH output, when any of its input is HIGH. The output is low when, all the inputs are LOW.

Symbol

A
F
B
Fig. 4.7 2-input OR gate

Truth table of 2-input OR gate

Table 4.7 Truth table for 2-input OR gate

 Input Output A B F = A + B 0 0 0 0 1 1 1 0 1 1 1 1

Note: Boolean addition is same as OR operation

4.6

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Timing diagram of 2-input OR gate

A

B

F

t

Fig. 4.8 Timing diagram for 2-input OR gate

Logic expression

For a 2-input OR gate having inputs A & B, output F is given by

F = A + B

Similarly for 3-input OR gate with inputs A, B, & C, the output is given as

F = A + B + C

4.6 NAND Gate

The NAND gate produces LOW output only when all the inputs are HIGH. When any of the input is LOW, the output is HIGH.

The term NAND is the contraction of NOT-AND and implies an AND gate followed by a NOT gate.

Symbol

A

B

F

A

B

F

Fig. 4.9 2-input NAND gate

Truth table of 2-input NAND gate

Table 4.8 Truth table for 2-input NAND gate

 Input Output A B F = (A . B)’ 0 0 1 0 1 1 1 0 1 1 1 0

Logic Gates

4.7

Timing diagram of 2-input NAND gate

Fig. 4.10 Timing diagram for 2-input NAND gate

Logic expression

For a 2-input NAND gate having inputs A & B, output F is given by

F = A.B

Similarly for 3-input NAND gate with inputs A, B, & C, the output is given as

F = A.B.C

Note: NAND gate are called universal gate as any logic circuit realisation is pos- sible by using NAND gate alone and any logic gate can also be realised in terms of NAND gate.

4.7 NOR Gate

The NOR gate may have two or more input but has only a single output.

The NOR gate produces LOW output only when any of the inputs is HIGH and a HIGH output, only when all of its inputs are LOW.

The term NOR is the contraction of NOT-OR and implies an OR gate followed by a NOT gate.

Symbol

A

B

F

A

B

F

Fig. 4.11 2-input NOR gate

4.8

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Truth table of 2-input NOR gate

Table 4.9 Truth table for 2-input NOR gate

 Input Output A B F = (A + B)’ 0 0 1 0 1 0 1 0 0 1 1 0

Timing diagram of 2-input NOR gate

A
B
F
t

Fig. 4.12 Timing diagram for 2-input NOR gate

Logic expression

For 2-input NOR gate having inputs A & B, output F is given by

F = A + B

Similarly for 3-input OR gate with inputs A, B, & C, the output is given as

F = A + B + C

Note: NOR gate is called universal gate as any logic circuit realisation is possible by using NOR gate alone and any logic gate can also be realised in terms of NOR gate.

4.8 XOR Gate (Exclusive-OR)

The XOR operation is not a basic operation. But it can be performed by using the basic gates (AND, OR, NOT) or the universal gates (NAND, NOR).

An XOR gate produces HIGH output for odd numbers of logic HIGH inputs.

Logic Gates

4.9

Symbol

A
F
B
Fig. 4.13 2-input XOR gate

Truth table of 2-input XOR gate

Table 4.10 Truth table for 2-input XOR gate

 Input Output A B F = A ⊕ B 0 0 0 0 1 1 1 0 1 1 1 0

Timing diagram of 2-input XOR gate

A
B
F
t

Fig. 4.14 Timing diagram for 2-input XOR gate

Logic expression

For 2-input XOR gate having inputs A & B, output F is given by

 F = A ⊕ B = AB + AB ⊕ −→ Symbol of XOR

FACT:

1. XOR gate is also called “stair

case switch”.

2. It is mostly used in parity gen-

eration and detection.

Note: When one of the inputs of 2 input XOR gate is at logic ‘0’ then, the XOR gate acts as a buffer circuit for the other input.

Concept: The XOR gate gives logic ‘1’ output for odd numbers of logic ‘1’ inputs.

4.10

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For example,

Fig. 4.15 XOR gates

The XOR gate acts like an odd number of 1’s detector.

4.9 X-NOR Gate

The XNOR operation is not a basic operation. But it can be performed by using the basic gates (AND, OR, NOT) or the universal gates (NAND, NOR).

An XNOR gate produces HIGH output when both the inputs are same.

Symbol

A

B

F

The bubble on the output of the XNOR symbol indicates that its

output is complement of XOR gate.

Fig. 4.16 2-input XNOR gates

Truth table of 2-input XNOR gate Table 4.11 Truth table for 2-input XNOR gate

 Input Output A B F = (A ⊕ B)’ 0 0 1 0 1 0 1 0 0 1 1 1

4.10 Buffer Gate

It is a simple gate which gives the same output as that of input. It is used for the purpose of delay.

Symbol

F
A
Fig. 4.17 Buffer gate

Logic Gates

4.11

Truth table

A
F
0
0
1
1

Graphic symbol of gates

 RECTANGULAR LOGIC TRUTH NAME DISTINCTIVE SHAPE SHAPE EXP. TABLE F A 1 F F A NOT A F = A 0 1 1 0 A & B A B F F 0 0 0 AND A F F = A.B 0 1 0 B 1 0 0 1 1 1 A B F A A 1 B F 0 0 0 OR B F F = A+B 0 1 1 1 0 1 1 1 1 A B F A A F & B 0 0 1 NAND B F F = A.B 0 1 1 1 0 1 1 1 0 A B F A F A F 1 B 0 0 1 NOR B F = A+B 0 1 0 1 0 0 1 1 0 A B F A =1 B F 0 0 0 XOR A B F F = A Å B 0 1 1 1 0 1 1 1 0 A B F A 0 0 1 XNOR B F A F =1 B F = A ⊙ B 0 1 0 1 0 0 1 1 1 BUFFER A F A 1 F F = A F A 0 0 1 1 GATE

Relation between XOR and XNOR

XOR function is complement of XNOR and vice-versa.

4.12

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A

B

F1=A B
F2=A B
F2 = A
B
F1 = A
B
F
A
F
B
F1 = A B
F1
= A
B
F2 = F1 = A B
F2 = F1 = A
B
= A
B
= A B

Fig. 4.18 Comparison of gates

Note:

1. In XOR gate when one of the input is at logic ‘0’ then the XOR gate acts as a buffer for the other input.

A

0

A

Fig. 4.19 XOR gate as a buffer gate

2. In XOR gate when one of the input is at logic ‘1’ then the XOR gate acts as an inverter for the other input.

A
A
1
Fig. 4.20 XOR gate as an inverter

Example 4.1 Show that, A B = A B

Solution

 L.H.S, A ⊕ B = AB + AB Let B = x So, A ⊕ B = Ax + A x = A x = A B = R.H.S (Hence Proved)

Example 4.2 Show that,

1. AB + A + B = A B

2. (A + B)(AB) = A B

Logic Gates

4.13

Solution

1. Proof:

L.H.S,

2. Proof:

AB + A + B = AB + A B

= A B = R.H.S

(De Morgan’s law)

(Hence Proved)

 L.H.S, (A + B)(AB) = (A + B)(A + B) (De Morgan’s law) = AA + AB + BA + BB = AB + A B = A ⊕ B = R.H.S (Hence Proved)

Example 4.3 Show the output waveforms for the 2-input AND, OR, NAND, NOR, XNOR gate, if the inputs are given as,

A
B

Fig. 4.21(a) Input waveforms

Solution

The output waveforms can be drawn with the help of truth table or logic expression for each gate as,

A
B
AND
OR
NAND
NOR
XOR
XNOR

Fig. 4.21(a) Input waveforms

Example 4.4 Show the output waveforms for the 2-input AND, OR, NAND, NOR, XNOR gate, if the inputs are given as,

4.14

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A
B
C

Fig. 4.22(a) Input waveforms

Solution

The output waveforms can be drawn with the help of truth table or logic expression for each gate as,

A

B

C

AND

OR

NAND

NOR

XOR

XNOR

0

1

Fig. 4.22(b) Input waveforms

4.11 IC Gates

GND

1

2

3

4

5

6

7

14

13

12

11

10

9

8

IC

74LS08

Vcc

Fig. 4.23 Front view of IC

Logic Gates

4.15

Practically logic gates are available in the forms of IC’s (integrated circuits).

One IC may contain one or more than one number of gates. The kind of gates that an IC contains is determined by an IC number written on the top of the IC.

For example,

74LS08 represents 2-input AND gate IC having 14 number of pins, and con- tains 4 number of AND gate in a single chip.

IC number contain different information about the IC as shown below,

74
LS
08
Indicates the types of logic
device within the series
Indicates the series

Indicates the standard identifier digit used to identify the types of logic gates

The table given below shows the IC numbers with their corresponding gates, one can easily identify which IC contains what types of gate.

Table 4.12 Representation of IC number and corresponding gates

 Sl. No IC number Types of gates 1 7400 Quad 2 input NAND 2 7402 Quad 2 input NOR 3 7404 Hex inverter 4 7408 Quad 2 input AND 5 7410 Triple 3 input NAND 6 7411 Triple 3 input AND 7 7420 Dual 4 input NAND 8 7421 Dual 4 input AND 9 7432 Quad 2 input OR 10 7486 Quad 2 input XOR

PIN conﬁguration diagram for some common ﬁxed function IC gates.

V CC

 14 13 12 11 10 9 8 1 2 3 4 5 6 7 GND

Fig.4.24

7400 Quad 2 input NAND

V CC
14 13
12
11
10
9 8
1 2
3
4
5
6 7

Fig.4.25

GND

7402 Quad 2 input NOR

4.16

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V CC
14 13
12
11
10
9
8
1 2
3
4
5
6
7

GND

Fig.4.26
7404 hex inverter
V CC
14 13
12
11
10
9 8
1 2
3
4
5
6 7

Fig.4.28

GND

7432 Quad 2 input OR

V CC

14 13
12
11
10
9
8
1 2
3
4
5
6
7
GND

Fig.4.27

7408 Quad 2 input AND

V CC
14 13
12
11
10
9 8
1 2
3
4
5
6 7

Fig.4.29

GND

7486 Quad 2 input XOR

4.12 Realisation of Boolean Expression using Basic Gates (AND, OR, NOT)

The following steps must be followed to realise a given Boolean expression using basic gates:

1. Solve the parenthesis

2. Perform negation operation if any (NOT gate)

3. Perform AND operation (AND gate) and then ﬁnally perform OR operation (OR gate) for SOP expression. Or else do the reverse of 3 rd step for POS realisation.

Example 4.5 Realise the logic expression F = BC + AC + AB using basic gates.

Solution

There is neither parenthesis nor NOT operation. So, we 1 st perform AND opera- tion and then OR operation.

Logic Gates

4.17

A

B

C

AB+BC+AC

Fig. 4.30 Realisation of logic function using basic gates

Example 4.6 Realise the logic expression F = (A + B)(B + D) using basic gates.

Solution

In the given expression, there are two sum terms which can be implemented using

two input OR gates and their outputs are AND operated by a 2 input AND gate.

A NOT gate is used to invert the input D.

A

B

D

(A+B)(B+D)

Fig. 4.31 Realisation of logic function using basic gates

Example 4.7 Realise the logic expression F = AB + (B + C)D using basic gates.

Solution

In the given logic expression there are two sum terms and two product terms which is implemented using two OR and two AND gates. As the result needs to be inverted, we use an inverter for that purpose.

A
AB+(B+C)D
B
C
D
Fig. 4.32 Realisation of logic function using basic gates

4.18

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4.13 Realisation of Logic Function Using Universal Gates

4.13.1 Level of gates

The maximum number of gates cascaded in series between an input and output is called level of gates. For example, a sum of product (SOP) expression can be implemented using a two level gate network, i.e., AND gates in the ﬁrst level and a OR gate in the second level.

A

B

C

D

Level 2
Level 1

o/p=sum of

product

Fig. 4.33 SOP form of gates showing different level

Similarly, a 3-level gate network can also be drawn as,

Output
level 1
level 2
level 3

Fig. 4.34 Different gates arranged to form a 3-level gate network

4.13.2 NAND & NOR realisation of basic gates

Rules for converting basic gates to universal gates

1. NAND gate is equivalent to an OR gate with bubbles at its input.

A
F
B
F = A + B = AB

=

A
F
B
F = AB = A + B

Fig. 4.35(a) Conversion of OR gate to NAND (universal) gate

Logic Gates

4.19

A
F
B
F = A + B = A . B

=

A
F
B
F = A . B
= A + B

Fig. 4.35(b) Conversion of AND gate to NOR (universal) gate

3. NAND gate is equivalent to an AND gate with bubbles at its output.

A

B

F
F = A.B

=

A

B

F
F = (AB) = AB

Fig. 4.35(c) Conversion of AND gate to NAND (universal) gate

4. NOR gate is equivalent to an OR gate with bubbles at its output.

A
F
A
=
B
B
F = A + B
F = (A +B) = A + B

Fig. 4.35(d) Conversion of OR gate to NOR (universal) gate

5. A NOT gate is equivalent to shorted inputs NAND or NOR gates.

A A

=

=

A
A
A
A

Fig. 4.35(e) Conversion of basic gate into universal gate

By keeping in mind the above 5 rules, any basic gate can be realised using the universal gates.

AND-OR conversion to NAND-NAND

A
B
F
C
D
Fig. 4.36(a) Basic AND-OR gates

Step-1: Convert the OR gate into NAND by giving bubbles at its input terminals.

Step-2: Give a bubble to each of the outputs of AND gates to convert it into NAND.

4.20

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A

B

C

D

NAND
NAND
NAND

Fig. 4.36(b) Conversion process of basic gates to NAND gates

Step-3: Here all the four bubbles introduced in the logic network cancels out each other so, there is no need of putting additional bubbles.

A

B

C

D

Fig. 4.36(c) Converted NAND-NAND form of Fig.4.36(a)

OR-AND conversion to NAND-NAND

A
B
F
C
D
Fig. 4.37(a) Basic OR-AND gates

Step-1: Convert the OR gate into NAND by giving bubbles at its input terminals.

Step-2: Give a bubble to the output of AND gate to convert it into NAND.

A

B

C

D

NAND
F
NAND
NAND

Fig. 4.37(b) Conversion process of basic gates to NAND gates

Step 3: For each bubble we need one inverter to cancel out the inversion effect of the bubble in the logic circuit.

Logic Gates

4.21

A

B

C

D

F
NAND
NAND
NAND

Fig. 4.37(c) Conversion process of basic gates to NAND gates

→ Each square represents NAND gates with shorted inputs.
A
B
F
C
D

Fig. 4.37(d) Converted NAND-NAND form of Fig.4.37(a)

So, the logic circuit given in Fig.4.37(a) is realised in terms of only NAND gates.

OR-AND conversion to NOR-NOR

A
B
F
C
D
Fig. 4.38(a) Basic OR-AND gates

Step-1: Convert the OR gate to NOR gate by giving bubbles at each of its output.

Step-2: Convert the AND gate to NOR gate by giving a bubble at its input.

A

B

C

D

F
NOR
NOR
NOR

Fig. 4.38(b) Conversion process of basic gates to NAND gates

Step-3: As all the four bubbles introduced in the logic network cancels out each other, so there is a need of additional inversion (NOR gate).

4.22

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A

B

C

D

F

Fig. 4.38(c) - Converted NOR-NOR form of Fig.4.38(a)

AND-OR conversion to NAND-NAND

Fig. 4.39(a) Basic AND-OR gates

Step-1: Convert the OR gate to NOR gate by giving bubbles at each of its output.

Step-2: Convert the AND gate to NOR gate by giving a bubble at its inputs.

A

B

C

D

F

Fig. 4.39(b) Conversion process of basic gates to NAND gates

Step 3: For each bubble we need one inverter to cancel out the inversion effect of the bubble in the logic circuit.

A

B

C

D

F
NOR
NOR

Fig. 4.39(c) Conversion process of basic gates to NAND gates

Each square block represents NOR gates with shorted inputs.

So, the logic circuit given in Fig.4.39(a) is realised in terms of only NOR gates.

Logic Gates

4.23

A
B
F
C
D
Fig. 4.39(d) Converted NOR-NOR form of Fig.4.39(a)

Universal capability of NAND and NOR gates

Example 4.8 Realise the following logic expression

F = B(A + CD) + AC

as,

4.24

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(i) NAND-NAND gate network

(ii) NOR-NOR gate network.

Solution

(i) NAND-NAND realisation:

Step-1: Implement the function using basic gates,
F = B(A + CD) + AC
B
C
D
A
A
C

F

Fig. 4.40(a) Implementation of function using basic gates

Step-2: Convert each AND gate to NAND by giving bubble to its output, and convert each OR gate to NAND by giving bubble to its input.

B

C

D

A

A

C

F

Fig. 4.40(b) Putting appropriate bubble in Fig.4.40(a)

Step-3: All the bubbles are mutually cancelled and only the bubble in the input of OR gate (A) is left. To cancel it, one additional NAND gate is required.

C

D

A

A
C

B

F = B(A+CD)+AC

Fig. 4.40(c) Converted NAND-NAND form of Fig.4.40(a)

The above implementation is the required NAND-NAND implementation.

Logic Gates

4.25

(ii) NOR-NOR realisation:

Step-1: Implement the function using basic gates,
F = B(A + CD) + AC
B
C
D
A
A
C

F

Fig. 4.41(a) Implementation of function using basic gates

Step-2: Convert each OR gate into NOR gate by giving bubble to its output, and convert each AND gate to NOR gate, by giving bubble to its input.

B

C

D

A

A

C

F

Fig. 4.41(b) Putting appropriate bubble in Fig.4.41(a)

Step-3: Place additional bubble (wherever required) to cancel the inversion effect on the circuit, by putting the bubble in Fig.4.41(b).

 Fig. 4.41(c) Putting additional bubble in ﬁg 4.41(b) to compensate inver- sion effect

Each small square block represents NOR gates with shorted inputs.

4.26

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B

C

A

A

C

F = B(A+CD)+AC

Fig. 4.41(d) Converted NOR-NOR form of Fig.4.41(a)

The above implementation is the required NOR-NOR implementation.

Example 4.9 Realise the following logic expression

F = ABC + DE as,

(i) NAND-NAND gate network (ii) NOR-NOR gate network.

Solution

(i) NAND-NAND realisation

Step-1: Implement the function using basic gates,

F = ABC + DE

A
B
F
C
D
E

Fig. 4.42(a) Implementation of function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output, and convert each OR gate to NAND gate by placing bubble at its input.

Step-3: Place the additional bubble (if required) to cancel the effect of bubble placed in step-2.

A

B

C

D

E

NAND

 F NAND

Fig. 4.42(b) Putting appropriate bubble in Fig.4.42(a)

Logic Gates

4.27

A
B
C
D
E

F

Fig. 4.42(c) Converted NAND-NAND form of Fig.4.42(a)

The above implementation is the required NAND-NAND implementation.

(ii) NOR-NOR realisation

Step-1: Implement the function using basic gates,

F = ABC + DE

A
B
F
C
D
E

Fig. 4.43(a) Implementation of function using basic gates

Step-2: Convert each OR gate into NOR gate by giving bubble to its output, and convert each AND gate into NOR gate, by giving bubble to its input.

Step-3: Place the additional bubble (if required) to cancel the effect of bubble placed in step-2.

A

B

C

D

E

NOR
NOR
F
NOR
NOR

Fig. 4.43(b) Putting appropriate bubble in Fig.4.43(a)

A
B
C
F
D
E

Fig. 4.43(c) Converted NOR-NOR form of Fig.4.43(a)

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Each small square block represents NOR gates with shorted inputs.

The above implementation is the required NOR-NOR implementation.

4.14 Sensitive and Inhibitive Inputs

Sensitive inputs

For a particular input, if the output of a logic gate is ﬁxed regardless of the other inputs present, then the gate is said to be sensitive to that particular input.

As for example,

AND gate is sensitive to logic 0.

A
0

0

A

0

The inputs A, B, C does not affect the output when one of the input is 0

B

C 0

Fig. 4.44(a) AND gate with sensitive to logic 0 input

NAND gate is sensitive to logic 0.

A

0

1

Fig. 4.44(b) NAND gate with sensitive to logic 0 input

OR gate is sensitive to logic 1

A

1

1

Fig. 4.44(c) OR gate with sensitive to logic 1 input

NOR gate is sensitive to logic 1

Fig. 4.44(d) NOR gate with sensitive to logic 1 input

Inhibitive inputs

For a particular input, if the output of a logic gate does not depend on that partic- ular input, the gate is said to be inhibitive to that particular input.

For example,

Logic Gates

4.29

A

A
1

Fig. 4.45(a) AND gate with inhibitive to logic 1 input

NAND gate is inhibitive to logic 1.

A
A

1

Fig. 4.45(b) NAND gate with inhibitive to logic 1 input

OR gate is inhibitive to logic 0.

A
A

0

Fig. 4.45(c) OR gate with inhibitive to logic 0 input

NOR gate is inhibitive to logic 0.

A

A

0

Fig. 4.45(d) NOR gate with inhibitive to logic 0 input

4.15 Phantom or Wired Logic

Some NAND or NOR gates allow the possibility of a wire connection between the outputs to provide a speciﬁc logic operation, this type of logic is called wired logic. The wired AND and the wired OR are not the physical gates.

Wired AND logic (AND-OR-Invert)

AB
A
B
AB. CD
C
D
CD
Fig. 4.46(a) Wired NAND gate

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Digital Electronics, an easy approach to learn

Wired OR logic (OR-AND-INVERT)

A

B

C

D

A+B
(A+B) + (C+D)
C+D

Fig. 4.46(b) Wired NOR gate

Note:

1. The wired AND logic can be implemented when the outputs of the NAND gates are tied together.

2. The wired OR logic can be implemented when the outputs of the NOR gates are tied together.

Example 4.10 Realise the 2-input XOR gate using NAND gates only.

Solution

Let the two inputs be A and B.

output, F = A B = AB + AB

Step-1: Implement the function using basic gates

A

B

A

B

F

Fig. 4.47(a) Implementation of XOR function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output, and convert each OR gate to NAND gate by placing bubble at its input.

A

B

A

B

F
NAND

Fig. 4.47(b) Putting appropriate bubble in Fig.4.47(a)

Logic Gates

4.31

Each small square block represents NAND gates with shorted inputs.

A

B

A

B

F

Fig. 4.47(c) Implementation of XOR gate using only NAND gate

Here 5 NAND gates are used, but the XOR gate can also be implemented using 4 numbers of NAND gates which is more efﬁcient.

A
A
AB
B
B
A.A.B = A+AB = A+B
F = (A+B)(B+A)
= (A+B)+(B+A)
= AB + AB
= A B
B.B.B = B+AB = B+A

Fig. 4.47(d) Implementation of XOR gate using minimum number of NAND gate

Example 4.11 Realise the 2-input XNOR gate using NAND gates only.

Solution

Let the two inputs be A and B.

output, F = A B = A B + AB

Step-1: Implement the function using basic gates

A

B

A

B

F

Fig. 4.48(a) Implementation of XNOR function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output, and convert each OR gate to NAND gate by placing bubble at its input.

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Digital Electronics, an easy approach to learn

A

B

A

B

F
NAND

Fig. 4.48(b) Putting appropriate bubble in Fig.4.48(a)

Each small square block represents NAND gates with shorted inputs.

B

A
A
B

F

Fig. 4.48(c) Implementation of XNOR gate using only NAND gate

The XNOR gate can also be realised by putting an inverter at the output of XOR gate. Hence in Fig.4.47(d) by putting an additional NOT gate (shorted input NAND) we can get XNOR gate.

A
A
AB
B
B

A. A.B = A+AB = A+B

F = (A+B)(B+A)
B.B.B = B+AB = B+A
F = (A+B)(A+B)
= AB + AB
= A
B

Fig. 4.48(d) Alternative implementation of XNOR gate using NAND gate

Example 4.12 Realise the 2-input XOR gate using NOR gates only.

Solution

Let the two inputs be A and B.

output, F = A B = AB + AB

Step-1: Implement the function using basic gates

A

B

A

B

F

Fig. 4.49(a) Implementation of XOR function using basic gates

Logic Gates

4.33

Step-2: Convert each AND gate to NOR gate by placing bubbles at its inputs, and convert each OR gate to NOR gate by placing bubble at its output. Also place additional bubbles (if required) to cancel the inversion effect.

A

B

A

B

NOR
F
NOR
NOR

Fig. 4.49(b) Putting appropriate bubble in Fig.4.49(a)

Each small square block represents NOR gates with shorted inputs.

A

B

A

B

F

Fig. 4.49(c) Implementation of XOR gate using only NOR gate

Example 4.13 Realise the 2-input XNOR gate using NOR gates only.

Solution

Let the two inputs be A and B.

output, F = A B = A B + AB

Step-1: Implement the function using basic gates

A

B

A

B

F

Fig. 4.50(a) Implementation of XNOR function using basic gates

Step-2: Convert each AND gate to NOR gate by placing bubbles at its inputs, and convert each OR gate to NOR gate by placing bubble at its output. Also place additional bubbles (if required) to cancel the inversion effect.

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Digital Electronics, an easy approach to learn

A

B

A

B

NOR
F
NOR
NOR

Fig. 4.50(b) Putting appropriate bubble in Fig.4.50(a)

Each small square block represents NOR gates with shorted inputs.

A

B

A

B

F

Fig. 4.50(c) Implementation of XNOR gate using only NOR gate

Example 4.14 Use minimum number of NOR gate to implement XOR and XNOR logic.

Solution

Implementation of XNOR gate:

A
A+(A+B) = A.(A+B)
= AB
A
A+B
AB + AB
= A B
B
B (B+
A+B
) =
B
.(A+B)

= A B

Fig. 4.51(a) Implementation of XNOR gate using only NOR gate

Implementation of XOR gate:

A
A+(
A+B
) =
A
.(A+B)
=
A B
A
AB + AB
A+B
AB + AB
= A B
B
B
(B+
A+B
) =
B
.(A+B)

= A B

Fig. 4.51(b) Implementation of XOR gate using only NOR gate

Logic Gates

4.35

Example 4.15 How many NAND gates are required to design an OR gate and a NOR gate.

Solution

OR gate implementation:

Fig. 4.52(a) OR gate

We know that, OR gate is converted to NAND by putting bubbles to its inputs.

To cancel the effect of bubble at inputs, we put additional two bubbles at input.

Fig. 4.52(b) Putting appropriate bubble in Fig.4.52(a)

Each small square block represents NOR gates with shorted inputs.

Fig. 4.52(c) Implementation of OR gate using only NAND gate

So total three number of NAND gates are required to implement the OR gate.

NOR gate implementation:

Fig. 4.52(d) NOR gate

Fig. 4.52(e) Implementation of NOR gate using only NAND gate

We know that the OR gate can be converted to NOR gate by placing an addi- tional NOT gate to its output.

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Digital Electronics, an easy approach to learn

So, four number of NAND gates are required to implement the NOR gate.

Example 4.16 How many NAND gates are required to implement the Boolean function,

F = AB + BC + AC

Solution

F = AB + BC + AC

Step-1: Implement the above function using basic gates.

A

B

B

C

A

C

F

Fig. 4.53(a) Implementation of the given function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output and convert each OR gate to NAND gate by placing bubble at its input.

Step-3: Place additional bubble (if required) to cancel the inversion effect.

A

B

B

C

A

C

NAND
NAND
F
NAND

Fig. 4.53(b) Putting appropriate bubble in Fig.4.53(a)

A
B
B
C
A
C

F

Fig. 4.53(c) Implementation of given function using only NAND gate

So, six number of NAND gates are required to implement the given function.

Logic Gates

4.37

Example 4.17 How many NAND gates are required to implement the Boolean function,

F (A, B, C, D) = A(CD + B) + BC

Solution

F (A, B, C, D) = A(CD + B) + BC

Step-1: Implement the above function using basic gates.

C

D

B

A

B

C

F

Fig. 4.54(a) Implementation of the given function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output and convert each OR gate to NAND gate by placing bubble at its input. The input of NAND gate is shorted to get NOT gate.

Step-3: Place additional bubble (if required) to cancel the inversion effect.

C

D

B

A

B

C

NAND
NAND

NAND

Fig. 4.54(b) Putting appropriate bubble in Fig.4.54(a)

C

D

B

A

C

B

F

Fig. 4.54(c) Implementation of given function using only NAND gate

So, seven number of NAND gates are required to implement the given func- tion.

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Digital Electronics, an easy approach to learn

Example 4.18 What is the minimum number of NAND gates required to imple- ment the function

F = A + AB + ABC

Solution

 F = A + AB + A B C = A(1 + B) + ABC = A + ABC (∵ 1 + B = 1) = A(1 + BC) (∵ 1 + BC = 1) = A

Hence, no gate is required.

Example 4.19 What is the minimum number of 2 input NOR gates required to implement the function

F (A, B, C, D) = m(0, 1, 2, 3, 8, 9, 10, 11)

Solution

To implement a function using NOR gate we prefer POS(product of sum) form,

So, we ﬁrst convert the given min term to corresponding max term as,

F (A, B, C, D) = M (4, 5, 6, 7, 12, 13, 14, 15)

Drawing the K-map,

CD
00
01
11
10
AB
00
0
1
3
2
01
0
0
0
0
4
5
7
6
0
0
0
0
11
12
13
15
14
10
8
9
11
10

Fig. 4.55(a) K-map

F = B

So, only one NOR gate is required,

B

B

Fig. 4.55(b) Implementation of the given function using only NOR gate

Logic Gates

4.39

4.16 Degenerated and Non Degenerated Forms

A two-level gate network is said to be degenerative, if it gives the same operation, when degenerated to a single level.

For example, AND-AND is equivalent to AND

Fig. 4.56(a) Two AND gates degenerates to one AND gate

16 possible combination of two-levels forms, with four types of gates: AND, OR, NAND & NOR. Out of these 16-combinations, 8 are non-degenerative forms and 8 are degenerative forms

8 Non-Degenerative Forms:

 SOP(Sum Of Product) POS(Product Of Sum) AND − OR OR − AND NAND − NAND NOR − NOR NOR − OR NAND − AND OR − NAND AND − NOR

Fig. 4.56(b) Non-Degenerative gates

It cannot be converted into a single level. So, Non-Degenerative. Similarly, remaining seven can be veriﬁed

8 Degenerative Forms:

 Two level gates Degenerates to single gate AND − AND AND OR − OR OR OR − NOR NOR AND − NAND NAND NOR − AND OR NAND − NOR AND NOR − AND AND NAND − OR OR

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Digital Electronics, an easy approach to learn

A
AB
AB+C
B
C
= A+B+C
A
A+B+C
B
C

Fig. 4.56(c) Degenerative gates

The remaining seven combinations, can be veriﬁed in a similar manner.

Brain teasers

1. F (A, B, C) = m(1, 2, 3, 4, 5, 7). Assuming inverting inputs are al- lowed, ﬁnd out

 (i) Minimum number of two input NAND gates that are required (ii) Minimum number of NOR gates that are required

Solution

(i) F (A, B, C) = m(1, 2, 3, 4, 5, 7)

To represent the above function in NAND-NAND realisation, we should write the above function using SOP form.

Since, it is required to use minimum number of NAND gates we go for K-map minimisation

Fig. 4.57(a) K-map

F (A, B, C) = AB + C + AB

Representing the above K-map function using basic gates, we get,

A
B
F
C
A
B

Fig. 4.57(b) Representation of logic function using basic gates

Converting the AND & OR gates to NAND by bubbling the outputs and inputs respectively & using extra bubbles (if required) to cancel the inversion effect in the logic circuit we get,

Logic Gates

4.41

A

B

C

A

B

NAND
NAND
NAND
F
NAND

Fig. 4.57(c) Putting appropriate bubble in Fig.4.57(b)

Each small square block represents NAND gates with shorted inputs.

A
B
C
A
B

F

Fig. 4.57(d) Implementation of given function using only NAND gate

So a minimum of 5 numbers of two input NAND gates are required to implement the Boolean function, F (A, B, C, ) = m(1, 2, 3, 4, 5, 7).

(ii) F (A, B, C, ) = m(1, 2, 3, 4, 5, 7)

To represent the above Boolean expression in NOR-NOR realisation, we should write the expression in POS form that is F (A, B, C) = M (0, 6)

For minimisation, K-map must be drawn for POS form

 L1 00 01 0 0 11 10 1 3 2 4 5 7 0 6
A BC

0

1

L:2

Fig. 4.58(a) K-map

L1 (A + B + C)

L2 (A + B + C)

F (A, B, C) = (A + B + C)(A + B + C)

Representing the above reduced expression using basic gates, we get,

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Digital Electronics, an easy approach to learn

A

B

C

F
A

B

Fig. 4.58(b) Representation of logic function using basic gates

Convert each AND gate to NOR gate by placing bubbles at its inputs, and convert each OR gate to NOR gate by placing bubble at its output. Also, place additional bubbles (if required) to cancel the inversion effect.

A

B

C

A

B

NOR
F
NOR
NOR

Fig. 4.58(c) Putting appropriate bubble in Fig.4.58(b)

Representing the Fig.4.58(c) using NOR gate we get,

A

B

C

A

B

F

Fig. 4.58(d) Implementation of given function using only NOR gate