Академический Документы
Профессиональный Документы
Культура Документы
MEMORY
Memory is a cornerstone of the modern PC. The CPU processes memory that holds
the program code and data that—and it is this intimate relationship between memory
and the CPU that forms the basis of computer performance. With larger and faster
CPUs constantly being introduced, and more complex software is developed to take
advantage of the processing power. In turn, the more complex software demands
larger amounts of faster memory. With the explosive growth of Windows (and more
recently, Windows 95) the demands made on memory performance are more acute
than ever. These demands have resulted in a proliferation of memory types that go far
beyond the simple, traditional DRAM. Cache (SRAM), fast page-mode (FPM)
memory, extended data output (EDO) memory, video memory (VRAM), synchronous
DRAM (SDRAM), flash BIOS, and other exotic memory types (such as RAMBUS)
now compete for the attention of PC technicians. These new forms of memory also
present some new problems.
Historical review
Back in the 80s, PCs were equipped with RAM in quantities of 64 KB, 256 KB, 512
KB and finally 1 MB. Think of a home computer like Commodore 64. It had 64 KB
RAM, and it worked fine. Around 1990, advanced operating systems, like Windows ,
appeared on the market, That started the RAM race. The PC needed more and more
RAM. That worked fine with the 386 processor, which could address larger amount of
RAM. The first Windows operated PCs could address 2 MB RAM, but 4 MB soon
became the standard. The race has continued through the 90s, as RAM prices have
dropped dramatically.
Today. it would be foolish to consider less than 32 MB RAM in a PC. Many have
much more. 128 MB is in no way too much for a "power user" with Windows 95/98,
it is important with plenty of RAM. Click here to read about the swap file and RAM
considerations. Windows 98 is a little better at handling memory, but still a lot af
RAM is a good thing.
Memory Organization
All memory is basically an array organized as rows and columns. Each row is known
as an address—one million or more addresses might be on a single memory IC. The
columns represent data bits—a typical high-density memory IC has 1 bit, but might
have 2 or 4 bits, depending on the overall amount of memory required.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
As you probably see in the intersection of each column and row is an individual
memory bit (known as a cell). This is important because the number of components in
a cell—and the way those components are fabricated onto the memory IC—will have
a profound impact on memory performance. For example, a classic DRAM cell is a
single MOS transistor, and static RAM (or SRAM) cells often pack several transistors
and other components onto the IC die. Although you do not have to be an expert on
IC design, you should realize that the internal fabrication of a memory IC has more to
do with its performance than just the way it is soldered into your computer.
MEMORY SIGNALS
A memory IC communicates with the “outside world” through three sets of signals:
address lines, data lines, and control lines. Address lines define which row of the
memory array will be active. In actuality, the address is specified as a binary number,
and conversion circuitry inside the memory IC translates the binary number into a
specific row signal. Data lines pass binary values back and forth to the defined
address. Control lines are used to operate the memory IC. A Read/–Write (R/–W) line
defines whether data is being read from the specified address or written to it. A –Chip
Select (–CS) signal makes a memory IC active or inactive (this ability to “disconnect”
from a circuit is what allows a myriad of memory ICs to all share common ad-dress
and data signals in the computer). Some memory types require additional signals,
such as Row Address-Select (RAS) and Column Address-Select (CAS), for refresh
operations. More exotic memory types might require additional control signals.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
Here you see a couple of SIMM modules. On top is a 64-bit module. Next is a 32-bit
module with a 72-pin connector. Below is an 8-bit module with a 30-pin connector:
64 bit
SDRAM:
32 bit
DRAM:
and
16 bit
DRAM:
DIMMs appear virtually identical to SIMMs, but they are larger. And where each
electrical contact on the SIMM is tied together between the front and back, the DIMM
keeps front and back contacts separate—effectively doubling the number of contacts
available on the device. For example, if you look at a 72-pin SIMM, you will see 72
electrical contacts on both sides of the device (144 contacts total)—but these are tied
together, so there are only 72 signals (even with 144 contacts). On the other hand, a
DIMM keeps the front and back contacts electrically separate (and usually adds some
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
additional pins to keep SIMMs and DIMMs from accidentally being mixed. Today,
virtually all DIMM versions provide 168 pins (84 pins on each side). DIMMs are
appearing in high-end 64-bit data-bus PCs (such as Pentiums and PowerPC RISC
workstations).
As PCs move from 64 to 128 bits over the next few years, DIMMs will likely replace
SIMMs as the preferred memory-expansion device.
Finally, you might see SIMMs and DIMMs referred to as composite or non-composite
modules. These terms are used infrequently to describe the technology level of the
memory module. For example, a composite module uses older, lower-density
memory; so more I.C’s are required to achieve the required storage capacity.
Conversely, a non-composite module uses newer memory technology; so fewer ICs
are needed to reach the same storage capacity. In other words, if you encounter a
high-density SIMM with only a few ICs on it, chances are that the SIMM is non-
composite.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
Memory Organization
The memory in your computer represents the result of evolution over several
computer generations. Memory operation and handling is taken care of by your
system’s microprocessor. As CPUs improved, memory-handling capabilities have
improved as well. Today’s microprocessors, such as the Intel Pentium or Pentium Pro,
are capable of addressing more than 4GB of system memory—well beyond the levels
of contemporary software applications. Unfortunately, the early PCs were not nearly
so powerful.
CONVENTIONAL MEMORY
Conventional memory is the traditional 640KB assigned to the DOS Memory Area.
The original PCs used microprocessors that could only address 1MB of memory
(called real-mode memory or base memory). Out of that 1MB, portions of the
memory must be set aside for basic system functions. BIOS code, video memory,
interrupt vectors, and BIOS data are only some of the areas that re-quire reserved
memory. The remaining 640KB became available to load and run your application,
which can be any combination of executable code and data. The original PC only
provided 512KB for the DOS program area, but computer designers quickly learned
that another 128KB could be added to the DOS area while still retaining enough
memory for overhead functions, so 512KB became 640KB. Every IBM-compatible
PC still provides a 640KB “base memory” range, and most DOS application programs
continue to fit within that limit to ensure backward compatibility to older systems.
However, the drawbacks to the 8088 CPU were soon apparent. More memory had to
added to the computer for its evolution to continue. Yet, memory had to be added in a
way that did not interfere with the conventional memory area.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
EXTENDED MEMORY
The 80286 introduced in IBM’s PC/AT was envisioned to overcome the 640KB
barrier by incorporating a protected mode of addressing. The 80286 can address up to
16MB of memory in protected mode, and its successors (the 80386 and later) can
handle 4GB of protected-mode memory. Today, virtually all computer systems
provide several MB of extended memory. Besides an advanced microprocessor,
another key element for extended memory is software.
application program. The DOS extender loads a program in real-mode memory. After
the program is loaded, it switches program control to the protected-mode memory.
When the program in protected mode needs to execute a DOS (real mode) function,
the DOS extender converts protected-mode addresses into real-mode addresses,
copies any necessary program data from protected to real-mode locations, switches
the CPU to real-mode addressing, and carries out the function. The DOS extender
then copies any results (if necessary) back to protected-mode addresses, switches the
system to protected-mode once again, and the program continues to run.
EXPANDED MEMORY
HIGH MEMORY
A peculiar anomaly occurs with CPUs that support extended memory—they can
access one segment (about 64KB) of extended memory beyond the real-mode area.
This capability arises because of the address line layout on late-model CPUs. As a
result, the real-mode operation can access roughly 64KB above the 1MB limit. Like
high DOS memory, this “found” 64KB is not contiguous with the normal 640KB
DOS memory range, so DOS cannot use this high memory to load a DOS application,
but device drivers and T.S.R’s can be placed in high memory. DOS 5.0 is
intentionally designed so that its 40 to 50KB of code can be easily moved into this
high memory area. With DOS loaded into high memory, an extra 40 to 50KB or so
will be available within the 640KB DOS range.
Memory Considerations
Memory has become far more important than just a place to store bits for the
microprocessor. It has proliferated and specialized to the point where it is difficult to
keep track of all the memory options and architectures that are available.
A wait state orders the CPU to pause for one clock cycle to give memory additional
time to operate. Typical PCs use one wait state, although very old systems might
require two or three. The latest PC designs with high-end memory or aggressive
caching might be able to operate with no (zero) wait states. As you might imagine, a
wait state is basically a waste of time, so more wait states result in lower system
performance. Zero wait states allow optimum system performance.
There are three classic means of selecting wait states. First, the number of wait states
might be fixed (common in old XT systems). Wait states might be selected with one
or more jumpers on the motherboard (typical of i286 and early i386 systems). Current
systems, such as i486 and Pentium computers, place the wait state control in the
CMOS setup routine. You might have to look in an “advanced settings” area to find
the entry. When optimizing a computer, you should be sure to set the minimum
number of wait states.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
MEMORY TYPES
For a computer to work, the CPU must take program instructions and exchange data
directly with memory. As a consequence, memory must keep pace with the CPU (or
make the CPU wait for it to catch up). Now that processors are so incredibly fast (and
getting faster), traditional memory architectures are being replaced by specialized
memory devices that have been tailored to serve specific functions in the PC. Some of
the memory designations are
.
FPM DRAM (Fast-Page Mode DRAM) This is a popular twist on
conventional DRAM. Typical DRAM access is accomplished in a fashion
similar to reading from a book—a memory “page” is accessed first, then the
contents of that “page” can be located. The problem is that every access
requires the DRAM to re-locate the “page.” Fast-page mode operation
overcomes this delay by allowing the CPU to access multiple pieces of data on
the same “page” without having to “re-locate” the “page” every time—as long
as the subsequent read or write cycle is on the previously located “page,” the
FPDRAM can access the specific location on that “page” directly.
EDO RAM (Extended Data Output RAM) EDO RAM is a relatively well-
established variation to DRAM, which extends the time that output data is
valid—thus the word’s .presence on the data bus is “extended.” This is
accomplished by modifying the DRAM’s output buffer, which prolongs the
time where read data is valid. The data will remain valid until a motherboard
signal is received to release it. This eases timing constraints on the memory
and allows a 15 to 30% improvement in memory performance with little real
increase in cost. Because a new external signal is needed to operate EDO
RAM, the motherboard must use a chipset designed to accommodate EDO.
Intel’s Triton chipset was one of the first to support EDO, although now most
chipsets (and most current motherboards) currently support EDO. EDO RAM
can be used in non-EDO motherboards, but there will be no performance
improvement.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
BEDO (Burst Extended Data Output RAM) This powerful variation of EDO
RAM reads data in a burst, which means that after a valid address has been
provided, the next three data addresses can be read in only one clock cycle
each. The CPU can read BEDO data in a 5-1-1-1 pattern (5 clock cycles for
the first address, then one clock cycle for the next three addresses. Although
BEDO offers an advantage over EDO, it is only supported currently by the
VIA chipsets: 580VP, 590VP, 680VP. Also, BEDO seems to have difficulty
supporting motherboards over 66MHz.
RDRAM (Rambus DRAM) Most of the memory alternatives so far have been
variations of the same basic architecture. Rambus, Inc. (joint developers of
EDRAM) has created a new memory architecture called the Rambus Channel.
CPU or specialized IC is used as the “master” device and the RD-RAM’s are
used as “slave” devices. Data is then sent back and forth across the Rambus
channel in 256-byte blocks. With a dual 250MHz clock, the Rambus Channel can
transfer data based on the timing of both clocks—this results in data-transfer rates
approaching 500MB/s (roughly equivalent to 2-ns access time). The problem with
RDRAM is that a Rambus Channel would require an extensive re-design to the
current PC memory architecture—a move that most PC makers strenuously resist.
As a result, you are most likely to see RDRAM in high-end, specialized
computing systems. Still, as memory struggles to match the microprocessor, PC
makers might yet embrace the Rambus approach for commercial systems.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
MEMORY TECHNIQUES
The three most-popular architectures are: paged memory, interleaved memory, and
memory caching.
Paged memory : This approach basically divides system RAM into small groups (or
“pages”) from 512 bytes to several KB long. Memory-management circuitry on the
motherboard allows subsequent memory accesses on the same “page” to be
accomplished with zero wait states. If the subsequent access occurs outside of the
current “page,” one or more wait states might be added while the new “page” is
found. This is identical in principle to fast-page mode DRAM. You will find page-
mode architectures implemented on high-end i286, PS/2 (model 70 and 80), and many
i386 systems.
Shadow memory : ROM devices (whether the BIOS ROM on your motherboard
or a ROM IC on an expansion board) are frustratingly slow with access times often
exceeding several hundred nanoseconds. ROM access then requires a large number of
wait states, which slow down the system’s performance. This problem is compounded
because the routines stored in BIOS (especially the video BIOS ROM on the video
board) are some of the most frequently accessed memory in your computer.
Beginning with the i386-class computers, some designs used a memory technique
called shadowing. ROM contents are loaded into an area of fast RAM during system
initialization, then the computer maps the fast RAM into memory locations used by
the ROM de-vices.
Whenever ROM routines must be accessed during run time, information is taken from
the “shadowed ROM” instead of the actual ROM IC. The ROM performance can be
improved by at least 300%. Shadow memory is also useful for ROM devices that do
not use the full available data bus width. For example, a 16-bit computer system
might hold an expansion board that contains an 8-bit ROM IC. The system would
have to access the ROM not once, but twice, to extract a single 16-bit word. If the
computer is a 32-bit machine, that 8-bit ROM would have to be addressed four times
to make a complete 32-bit word. You might imagine the hideous system delays that
can be encountered. Loading the ROM to shadow memory in advance virtually
eliminates such delays. Shadowing can usually be turned on or off through the
system’s CMOS Setup routines.
PARITY ISSUES
It is vital that data and program instructions remain error-free. Even one incorrect bit
because of electrical noise or a component failure can crash the PC, corrupt drive
information, cause video problems, or result in a myriad of other faults. PC designers
approached the issue of memory integrity by using a technique known as parity.
The basic idea behind parity is simple—each byte written to memory is checked, and
a 9th bit is added to the byte as a checking (or “parity”) bit. When a memory address
is later read by the CPU, memory-checking circuitry on the motherboard will
calculate the expected parity bit and compare it to the bit actually read from memory.
In this fashion, the PC can continuously diagnose system memory by checking the
integrity of its data. If the read parity bit matches the expected parity bit, the data
(and, indirectly, the RAM) is assumed to be valid, and the CPU can go on its way. If
the read and expected parity bits do not match, the system registers an error and halts.
Every byte is given a parity bit, so for a 32-bit PC, there will be 4 parity bits for every
address. A 64- bit PC, has 8 parity bits, etc.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
The two types of parity are even and odd. With even parity, the parity bit is set to 0 if
an even number of 1s is already in the corresponding byte (keeping the number of 1s
even). If an even number of 1s is not in the byte, the even parity bit will be 1 (making
the number of 1s even). With odd parity, the parity bit is set to 0 if an odd number of
1s is already in the corresponding byte (keeping the number of 1s odd). If an odd
number of 1s is not in the byte, the odd parity bit will be 1 (making the number of 1s
odd). Although even and odd parity work opposite of one another, both schemes serve
exactly the same purpose and have the same probability of catching a bad bit. The
memory device itself does not care at all about what type of parity is being used—it
just needs to have the parity bits available. The use of parity (and the choice of even
or odd) is left up to the motherboard’s memory-control circuit.
RAM speeds
RAM speed is measured in ns (nano seconds). The fewer ns, the faster is the RAM.
Years ago, RAM came in 120, 100 and 80 ns. Today, we are talking about 60 ns and
faster. It becomes complicated to describe the relationship between RAM speed and
the ability of the system bus to utilize fast RAM. I will gloss over that. But here is a
table, which illustrates RAM speed, relative to clock speed.
Peak Bandwidth
Here you see the maximal peak bandwidth of the three well-known RAM types. The
figure illustrates the absolutely maximal transfer from RAM to the L2-cache - in
peaks, not as continuously transferred.
On the Pentium motherboard, the system bus is 64 bit wide. Therefore, the 32 bit
SIMMs are installed in pairs. Since the standard motherboard only has two banks with
a total of four SIMM sockets, RAM expansion possibilities are limited. NOTE: never
use different speed RAM modules on the Pentium motherboard. All modules must
have the same speed. Here you see a few configurations on an old Pentium
motherboard with four SIMM sockets:
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
16 MB + 16 MB - 32 MB
16 MB + 16 MB 32 MB + 32 MB 96 MB
32 MB + 32 MB 32 Mb + 32 MB 128 MB
Rambus RDRAM
While the CPUs has become around 200 times faster in ten years, the RAM
performance has only gone up 20 times. So we need new RAM types. But which?
Many vendors decided to go for DDR RAM as described in. Where DDR RAM is a
development of the existing SDRAM technology, Intel chooses RDRAM, which
represents a much more revolutionary change in RAM design.
Intel is committed to the Rambus RAM, which also is called RDRAM (Rambus
Direct RAM), nDRAM, or RIMM (Rambus Inline Memory Modules). RDRAM is an
advanced technology patented by a company, who sells the technology to other chip
manufactures for a 2% in license. In 1997 Intel signed a contract that apparently
commits them to support RDRAM only in all new chipset up to 2002. Originally
AMD also expected to support the Rambus RAM for its Athlon processor. But having
seen all Intel's problems with the technology, AMD is not so keen on the Rambus
anymore. However, RDRAM is already used in Sony PlayStation 2 and in
Nintendo64 machines. In the Sony PlayStation 2 you find 32 MB of RDRAM
delivering a bandwidth of 3.2 GB/sec. During 1999 and 2000, Rambus was not very
successful. In fact, Intel has suffered a serious set-back due to their commitment to the
Rambus design. The chip set i820 "Camino" became a little disaster. Intel failed to
produce a reliable way to interface SDRAM to the 820 chipset. The MTH (Memory
Translator Hub - which translated RDRAM bus to SDRAM modules) had some
timing or noise issues that caused unreliable operation. Intel replaced CC820 boards
with VC820 boards (with 128MB RDRAM included) as the CC820 use the MTH and
SDRAM while the VC820 used RDRAM.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
RDRAM is developed from the traditional DRAM, but the architecture is completely
new. It has been streamed and optimized to yield new performance. The RAMBUS-
design gives a more intelligent access to the RAM, meaning that units can "prefetch"
data and this way free the CPU some work. The idea is that data is read in small
packets at a very high clock speed. The RIMM modules are only 16 bit wide
compared to the traditional 64 bit SDRAM DIMMs, but they work at a much higher
clock frequency:
The Rambus modules work on 2.5 volts, which internally is reduced down to 0.5 volt
when possible. This helps to reduce heat and radio signals. The RIMMs hold
controlling chips that turn off the power to sections not in use. They can also reduce
the memory speed if thermal sensors report of overheating. The RIMM modules hold
184 pins.
The RDRAM chips have to be placed very close to the CPU to reduce radio noise.
This indicates, that RIMM technology is rather sensitive.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
DDR RAM
A very interesting RAM type is the DDR RAM, which is expected to hit the market in
2001. DDR stands here for Double Data Rate. It is a technology that transmits data
on both sides of a tact signal. This way the performance has been doubled; a 133
MHz SDRAM chip can very easy become altered to a 266 MHz DDR chip:
It should be pretty easy for the market to change for DDR RAM. The modules look
like and operate quite similar to existing SDRAMs. We just need new chipsets to start
the migration. However, the modules hold 16 pins more than SDRAM do, so they do
not fit into the same sockets.
NetPro Certification Courseware for NetPro Certified Systems Engineer – N.C.S.E
PC2100
The Taiwanese company VIA, which produces chip sets and CPUs and who are
fighting Intel, is fully supporting the DDR RAM strategy. Soon we shall see 266 MHz
moduls (being "overclocked"133 MHz SDRAM modules).The 266 MHz modules
reaches a 2.1 GB/sec bandwidth. Hence they are to be sold as PC2100 RAM.
Other terms used are:
VIA expects DDR to be used in all segments of the pc market. Intel, who is behind
the Rambus technology, only expects to use DDR in large servers, where you find
several Gigabytes of RAM installed, and where RAM price really matters.
Comparing bandwidth
Below you see the theoretical bandwidths of different RAM types. However, SDRAM
does not perform as good as the figures show. This is due to latencies; the CPU and
other units cannot read the data at these speeds; they have to wait some clock circles
in between each reading before the data transfers start. The same goes for DDR RAM.