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    BITS MTech Microelectronics question paper

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    BITS MTech Microelectronics Question Paper

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    s_subbulakshmi
    BITS MTech Microelectronics question paper

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    © All Rights Reserved
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    Birla Institute of Technology & Selenee, Pilani Work-Integrated Learning Programmes Division ‘Second Semester 2015-2016 Mia Semester Test Course No. MEL 20520 Course Tile Digital Signal Processing Nature of Exam ‘Closed Book Weishtage 30 No. of Pages Duration 1% hours No.of Question Date of Fxam 281052016 _ FN) Note 1. Please foil he ieructons to Candidates give onthe caver pase ofthe answer book 2. Allpars ofa question shoud be answered consecutively. Each ane shoud sta roma fesh age [3__Asaumptions made fan, shouldbe sated clearly athe beginning of your answer QI. The impulse response of @ TI is shown below. eA nt | Determine and sketch the response of this system tothe input xn) [n—4}. [5 Marks} 2. Determine whether the system a . im = wth rown= Sai wis in stable, cus tinear and ime-invasin, = (6 Marks} 03. A contiuces time sigaal x1), with Furer ransom X.(J) shown in gue is sampled wih sampling period T = 2 to fom the sequence fn) = x(n) 2) Sketch the Fourier transform X(e!#) fo a] < 7 1 Marks} ') Draw the block diagram of a recovery system to recover 2-(@). Assume that ideal filters are available 13 Marks} 4. Acaual LIsystem ha nips response hy for which he etansommis 4, G80 - ate » oe @iayie of 8) Whats thereon of converge of HC)? [BMarks} 2 'b) Is the system stable? Explain ate RMA ZA Q5._ The frequency response of the LTI system is, ae wom =etend) (sett) newer Determine the output of the system, y[n], when the input is x{n] = Cos (m2). Express your saree ines sioploe frm Yous Te Marks} ay settee ee a ae a(geere? * § x pot oe (Regula) (Course Tile & Code : VLSI Design- MELWT 26621 hongeeT Nature ofEsam —: Closed Book [No.of Questons= 8 Weightage 30% Date ofEsam —— : 21/05/2016 ‘Durston: 90 Min Now: a a a A a + ilustnite with the help of plots, how the value of back-bias voltage effects the - A Birla Institute of Technology & Science, Pi Work-Integrated Learning Programmes Division First Semester 2015-2016 ‘Mid-Semester/Comprehensive Test 1, Please follow all the Inston: to Candids given on the cover page of the answer book, 2 Answer all the questions 5. Allpars of a question should be answered consecutively ‘4 Assumptions made ifany, should be tated clearly a the beginning of your anew. M Derive an expression for desin to source current Ty, in struation region of AMOS transistor. Interpret VIC of CMOS inverter by specifying diferent regions of operation and also list che states of pMOS and’ nMOS in each region, ‘What are the pros and cons of using cell-based ASICS? List the Abstraction levels in the design and verification paths of VLSI circuits ‘aration in threshold voltage, Vand drain to source current, [de> Construct the modified BiCMOS inverter. For the dynamic CMOS logic cireuit shown below, find node voluge at A (voltage across capacitor C) in teims of Vaz, if capacitor C wa initially pe charged to Vas, Assume C1 = C2= C. Realize the fllowing function sing nMOS logic, Z= DFE TBC aks a 0s Birla Institute of Technology & Scienee, Pilani Work-Integrated Learning Programmes Division T Semester (2015-2016) Mid-Term Examination Course No MEL G631 Course Title Physies and Modeling of Microelectronic Devices (PMMD) Nature of Exam Closed Book Weighinge £3086 No. of Pages Duration Shes No. of Questions = 5 Dale of Exam 21/05/2016 (12:00pm - 01:30pm, AN) a Note: 1 Please olowall he Msruetons to Candee gven onthe caver page of he answer book 2. Allpans ofa question should be answered consecutively. Each ansver sould start fom a resh page 5._Assumsions made fay, shouldbe sted ell lhe beginning of your answer, AA. Bxplain following terms. [x36 Marks) 1) Diffusion current ) P-N junction with energy band disgram. 10cm?) has the following properties at 300K. 6x10") [2x36 Marks} 0.0259 via (n= 15.10% om Peside:N, =10° em *:T, = 0.Ausi, = 7000m"" N~side :N, =10" em?37, =10us;u, = 450em?y" 1) The junction is forward biased by 0.5V. what isthe forward current? 'b). What isthe current at a reverse bias of -0.SV? /Q3. Describe following terms. [2x3 = 6 Marks} {a} Shorted-gate drain current (IDSS) ’) Pinch off voltage (VP) n(n oe 523, (eH -1) Aa. 8) AJFET show in Fig. has values of Ves(off) = -8V and Idss~i6mA. Determine the values of Ves, Id and Vas for the eireui, Draw an Output Characteristics of a JPET. AS. 4) Using given circuit prove BIT isin Active mode? 1h Re Vee c 100k Er aai0yiov Re av e Vea ) Explain egimes of operation of a NPN BIT? [Ht Marks} eel [2 Macks) [4 Marks) [2 Marks} 6. In the igur given below, zl) = x(n") and ola] {an} (0) Assume that s(t) bas Fourier transform such that Xo(jM) = 0, |} > 2n(100). What ‘value of Ti required so that xno, Tews () How should 1 be chosen so that y(t) = zelt)? oo h pic 7) 2H) te 7d i t z a (6 marks) 1. The impue response of an LTT systam i glen by hla] = 2 —n]. Determine the output +" forthe following input soquence zn] = wn — I. (Gmarks) 8. If sf = 0.2"uj) find the soquence yfo} whose Z-teansiorm is ¥(z) — X(2"). Hence find the sequence g(r} whose Ztraasforn ia Ge) = (14 9X (4 marks) "ind out the impulse response of a FIR fer designed by Windowing using a Hamming ‘window to approximate the frequency response given below. Wel = i rad We? = 2 rad (7 marks) JOA Butterworth LPP of fourth ovder and entof frequency of 1K isto be designed Sampling froqneney is 10 KHs, Transform this Ber into diserote time domain by bilinear transos~ ‘mation such thatthe vesultiag fer preserves the gain ot! KH. Find H(2) its poles and eros, and mark the poles and zeros in-plane. (20 marks) ARM assembly language reference card eavhto mans wed - yparganmese at hg) em Ma iy ilaeNT ol wir ame py Pt tent Bergen ike A mom soy at Speman Mia ck BAT omg ta nia Regan Wii exireOR MIR Nga hak minh tne Ke eRe ans MIO AR AMDT A) STR Rm oes yotonesney eee on ll Tae aor ome ome ae bape nies fem on ew Sm we Senestahpionte Se cney abiatnnrclaunais :F cgi ttn a RAE OR mg. sas fap soi hay hy Tiber bis nota yh a rom ony kde ‘late DLA amt, | uesarbiss ng herpes ney lt fev cee rose age ori ted eer th spa ete ih i epitoral 1 on oR ex Hou alt nd? A Hn, attita tttnght t9 Rov tim, fuaoryge tos Rik tlaceany bt tht tag Ink oR rae take lope date bye ak ag aiivitc i me ye owe tld by te Birla Institute of Technology & Sclence, Pian Work-lntegrated Learning Programmes Division First Semester 2015-2016 Mid-Term Examination Course No. ML 26512 Course Tithe EMBEDDED SYSTEM DESIGN Naure of Fxam_ Closed Book ~ Weighage 30% No. of Paes on 590 minutes No.of Questions 10 Date at Exam 2810572016 (FN) [Please fallow all the Jarno Jo Canidae wven on the cover page ote ansiver book. 2 ll paso a question sould be answered conseutvely. Fach answer should toma resk ‘ssunptons made i any, shoul be stated clearly atthe beginning of your answer. Answee ALL, Questions PART A-(I x55 marks) 1. Answer the follawsing questions: ra) What type of ARM cove does I.PC2378 have? Io) Among ARM Cortex-A. ARM Cortex-M and ARM Cortex-R cows, which one is more stable fora smaiphone? Ai) What does the acccenbly intnetion MOY +15, r14 do (other than the abi)? 2. Stat with jstitieation i the flowing statements are righ (or wang) Fa), Dynamic RAMs accupy more space por word sorage Yh) ‘The usecase diagram isan example of structural diagram, PARTB. Qx5~1Omarks) A Which ofthe following sare rel time embedded systems? Justify your answer a) Ceiling Fan 1b) Microwave Oven ©) Television Sot 4) Desktop Key Boat ©} Digital Camera ive a sequence of ARM instructions that will multiply 9 by 20 (without using MUL). % 8 ¢5_Fyplain any to dstnet functions that can be performed by “TIMER and COUNTER Unit in embedded controllers, 6. Is Register Windowing 9 par of ARM architecture? Why oF why not? Mention any tv examples of dieet addressing instructions in 8051 a 0 PART C (15 marks) For the below ARM assembly code, trae the values as it execttes that will he plac into the registers Ra, RS, and RE. (x33 marks 4 Mov Ra, #7 Mov RS, #4 MOV R6, ¥4 again MoV RI, RA ADD RA, RS, RA MOV RS, R7 SUBS RG, R6, For the below ARM assembly code snippet memory is show inthe follin (Assume the memory location assigned oat by the assemblers Os IC), Also assum ‘hat the code will execute ona litle endian processor. Show the contents a ths rss RO and RI after each instrution 4 A marks) c ADR RI, data Mov R2, 6a ewan LDR RO, IRI se: a eS pk RO, (R1),R2 | Sesso20% RBaR UDR RO, (RI, #41! Suppose your organisation wants to design a Parking Cale Contos, Assume that ths controler has a sensor controlled parking garage arm which controls adoisse to 3 parking garage 6 Assume thatthe Parking Gate Controller funetions a follows 8) a car wants to come through, the gate needs to raise the ann unt iis the position bb) Once the gate is atthe top position, it has t0 stay there unl the ear fas civ ‘through the ate €} After the car has driven through the gate aces to lower them yi i ces bottom position ‘You have 19 model a State diagram and Sequence dingram which describes th areiving seenario for the parking Io Birla Institute of Technolosy & Science, Pilani \Worke-Integeated Learning Programmes Division VLSI Desigu (MLWT 2.6821) CCoapshensive Exam (Open Book) Drsson: 08 Hoare ‘Weghtage: 60% Dace of Esa: 06/08/2016 Note: 1 Follow ll the Imation te Candida given onthe cove pe of the answer book. 2 Answer al he following quer dons. All pers ofr geexton should be answuzed consecutively. 5 Ausumprions made fany shouldbe stated ler the binning of your anawex Qa Macks 1. Determine dhe optimum path delay for te loge esin shown in che figure. Als, find C2 and 10 (C3. Given logieal tio # = 2.5 and Cl = 1 pF ignore p and q of every stage. Few, Aoooe* Ow nse _Z7* Forte pass tmasstor cascade shown ia the gure find the ump voltage at nodes Voand 0g ‘You forthe folowing inpat voltages (V). Assume Vin cece Va Vb ‘ 1 33 33 c 205 $0 fat 320 2st 4 B : 77 For an sE5T consiier the data provided in the uble. Determine Vy, k G3), K, and Vy 08 Assume 20f 64,and (W/Le « @ 2h va Pa, oe , 0 “50 312 Ke Gon : wb mes : ae A ee donioo CMOS ca Fx Pope Pad Genea (Genie nC OF Implant i aving Bookan freon ing PAand LA design os PIABCD) = T6932 ie F2(A,B,C,D) = Lm(1,3,5,8,9,11) © Devise a dgial BICMOS circait that implements the Boolesa fonction, P = AVEO) 05 74 Realine the CMOS logic gate that implements the Boolean function, F = AWB? O)> A 5 A semper den he pont cpa PRP ad GY ach 2 ee gem ee mm ofan dn miteson of 10014 10011 ming Booth econ 0s /@) For the Binary data: = 10, B= 11 & Cin = 0 perform addition using Conditional Sum adder. 04 143 mi/Vand V0.7. Compute din caret “ AD An oF ET has 8 i. Vos=20 Vand Vox OF TECHNOLOGY AND SCIENCE, PILANI MS MICRO ELECTRONICS COMPREHENSIVE EXAMINATION SEWI Z.C421: Digital Signal Processing Duration: $ hours 660 Marks Answor all Questions _ 3 Consider the following daa low-pass system with cut of frequen (2) What isthe impulse responoe of the system? (marks) () Is the system causal? (1 mark) (6) Is the system BIBO stable? (1 mark) 2. The signal zo] has the spectrum “ee ‘The signal Draw the DTFT Z(e!) if (é-marks) 4. Consider this discrete-time eystam RU Cece] al Le ‘The frequency response H(o™) is shown below mle) F ‘This is a very wseful aster, cllad a Hulhert-Filter, and is often used in communication, ver the interval ~ << 7 the frequency response i ven by jo -rewed He)= 45 O ‘Comprehensive Examination a MEL 0 GeeRE Nie gles and Modeling of Mireesonic Devi (PMD) ares eas Wages oe Dota oe Pee ——STVOW2016 (930an-12:30an) Ta Se Se a re tral nt at fons to a ne eee Sanaa are au (2510 Mars) @ Catelate yd 9 Sion PN junction wth N, =10" ems, =10" ems (oye tas x10 ge AE aba ik Ty AAS 0Hig 1.6210") _-b) 152 BJT equivalent to two diodes connected back-to-back? Prove your statement with an example circuit élagram? ipge? a2 i. (>xs10 Mans) a) Challenges for MOSFET scaling. = 3) Chin ofFDSOIVSFaPET 9 43. 3. [2x5=10 Marks] «Energy band comparison of i Vs Gans oe Mats 1) en anor nm tara tages Swng Masing neni spy Frat bond Te Rta 0 Accumulation ee piel x 0 Depletion sz counted & b} Draw and explain Bad a oN characteristics of a MOSFET » QS. Explain i 2 "Gpraon of ight Eniting Diode wi diagram, 3) Opeaion of Lie de - . as ® 90%? sesecrtveee peeve Meee eececnarsege { Birla Insttate of Technology & Science, Plant Work-tntgrated Learning Programmes Division ‘Second Semester 2015-2016 Comprenensive Test (EC-2 Regular) Course No. MELCA 20573 Covtse Title Digital Signal Processing Nature of Exam Open Book Weighave o Duration Shou Date of Exam 002016 CEN) ‘Note: 1 Pleweftw al he ton 19 Candidate given nthe cover pa of teaver book 2 Allpasofs question boul be mayer cosseutvely Each noe esl Sa ory sh oes 5._Aasmpions made uy, shuld este lary tte bepning of our ener Qu, Consider an FIR LTI system having the following impulse response. An] = of} = s(n = 2) AAG) Compute y{n} a the Tnear convolution of fifa] above with the input sequence below. ‘State the rumericl value of yn] ~ x{n]« A] fr eoch a, ~e>

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