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The mathematics behind the unlocked state are beyond the scope of this presentation. In
the section we will attempt to answer the following questions from an intuitive viewpoint:
1.) Under what conditions will the LPLL become locked?
2.) How much time does the lock-in process require?
3.) Under what conditions will the LPLL lose lock?
2.) The pull-in range (P) is the range within which an LPLL will always become
locked, but the process can be rather slow.
Pull-in Range
o-P o o+P Fig. 2.1-112
3.) The pull-out range (PO) is the dynamic limit for stable operation of a PLL. If
tracking is lost within this range, an LPLL normally will lock again, but this process can
be slow.
Pull-Out Range (Dynamic Limits of Stability)
o-PO o o+PO Fig. 2.1-113
4.) The lock range (L) is the frequency range within which a PLL locks within one
single-beat note between reference frequency and output frequency. Normally, the
operating frequency range of an LPLL is restricted to the lock range.
Lock Range
o-L o o+L Fig. 2.1-112
Hold-in Range
Pull-in Range
o-H o-P
in
o+P o+H
Fig. 2.1-115
The following pages will attempt to relate the key parameters of hold range, pull-in range,
pull-out range, and lock range to the time constants, 1 and 2 and the gain factors Kd, Ko,
and Ka.
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
2(t)
t
Fig. 2.1-12
Note: No locking occurs in the above illustration because > KoKd |F(j)|.
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
t
Fig. 2.1-13
Locks within one cycle or beat note.
2
o
2(t)
t
Fig. 2.1-14
Since min is less than max, the frequency of the positive going sinusoid is less than
the frequency of the negative going sinusoid. As a consequence, the average value of the
VCO output pulls toward 1.
o 2(t)
Pull-in Time, TP t
Fig. 2.1-15
Type of Filter P (Low Loop Gains) P (High Loop Gains) Pull-In Time, TP
Passive Lag 4 4 2 2 o2
2nKoKd - n2 nKoKd = 16 3
n
Active PI Lag 2 o2
= 16 3
n
R.M. Best, Phase-Locked Loops Design, Simulation, and Applications, 4th ed., McGraw-Hill Book Co., 1999, Appendix A.
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
Lecture 060 Linear Phase Lock Loops - II (5/15/03) Page 060-11
Example
A second-order PLL having a passive lag loop filter is assumed to operate at a center
frequency, fo, of 100kHz and has a natural frequency, fn, of 3 Hz which is a very narrow
band system. If = 0.7 and the loop gain, KoKd = 21000 sec.-1, find the lock-in time,
TL, and the pull-in time, TP, for an initial frequency offset of 30 Hz.
Solution
1 1
TL fn = 3 = 0.333 secs.
2 o2 44 fo2 302
TP = 16 3 = 1683 f 3 = 32(0.7)33 = 4.675 secs.
n n
n1(t)
v1(t)+n1(t)
t
Phase error
Fig. 2.1-16
Input
Signal Phase Output
Filter
Bi Detector
f
fo
VCO
Fig. 2.1-17
Spectral Power
Area = Ps
reference signal, v1(t), and
Density
the superimposed noise Area = Pn Bi
signal, vn(t). = WiBi
Wi
fo Frequency
n1(j)2
Area = vn12
Spectrum of the phase noise
at the input of the PLL.
Bi/2 Frequency
|H(j)|
Frequency response of the
phase-transfer function,
H(j). Function of
BL Frequency
n2(j)2
Area = vn22
Spectrum of the phase noise
at the output of the PLL.
BL Frequency
Fig. 2.1-18
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
Rsmall(not locked)
v1(t) Phase vf(t)
Detector
Rlarge(locked)
v2(t)
Switched Loop Filter
VCO
Fig. 2.1-20
In the unlocked state, the filter bandwidth is large so that lock range exceeds the
frequency range within which the input is expected.
In the locked state, the filter bandwidth is reduced in order to reduce the noise.
o
2min
vf
Fig. 2.1-21
vf(min) VB vf(max) VB
2
6.) Determine the value of Kd from the data sheet. Kd will depend upon the signal level. It
is preferred to have a large value of Kd.
7.) Determine the natural frequency, n.
a.) Lock range has been specified in step 3.).
L
n = 2
b.) Noise bandwidth has been specified in step 3.)
2BL
n = + 0.25
Frequency Spectrum
S1 E1 Channel Channel Channel Channel
1 2 3 N
Bi
S2 E2
f
f01 f02 f03 f0N
300 Hz 2Lmin 3 kHz
SN EN Fig. 2.1-22
2Lmax
Each transmitter is to transmit a binary signal with a baud rate of 50 bits/sec. The signal
is encoded in a non-return to zero format which means that the bandwidth required is half
the baud rate or 25 Hz. The spectrum of the FM-modulated carrier consists of the carrier
frequency and a number of sidebands displaced by 25 Hz, 225 Hz, etc. from the carrier
frequency.
Assuming that a narrow-band FM is used, the channel spacing will be selected as 60 Hz.
The channel is assumed to be an ordinary telephone cable with a bandwidth of 300 Hz to
3000 Hz giving Bi = 2700 Hz. Therefore, the maximum number of channels is
Max. no. of channels = Bi/Channel spacing = 2700/60 = 45 channels.
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
Phase-Locked Loop Data Book, Exar Integrated Systems, Sunnyvale, CA, 1981.( http://www.exar.com/products/XR215A.html)
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
Lecture 060 Linear Phase Lock Loops - II (5/15/03) Page 060-29
Cutoff frequency:
c = n 22 + 44+1 = 17.53 20.72 + 40.74+1 = 27.045 rads/sec (4.3 Hz)
The phase margin can be written as,
PM = 180 - 90 + tan-1(c60.6x10-3) - tan-1(c169.2x10-3)
= 90 + 58.61 - 77.67 = 70.94
PSPICE Input File:
LPLLDesignProblem-OpenLoopResponse
VS10AC1.0
R11010K
*Loopbandwidth=Kv=52sec.-1Tau1=60.6E-3Tau2=108.6E-3
ELPLL20LAPLACE{V(1)}={(52/(S+0.00001))*((1+60.6E-3*S)/(1+108.6E-3*S))}
R22010K
*SteadystateACanalysis
.ACDEC200.01100
.PRINTACVDB(2)VP(2)
.PROBE
.END
60 Phase
Margin
40 79
20
Magnitude
0 Cutoff
-20 Frequency
5Hz
-40
0.01 0.1 1 10 100
Frequency (Hz)
Cutoff frequency 5Hz
Phase margin 79
C= C=
Phase 18.1 F 18.1 F Co = 0.27F
Rx
Detector R2 = 5k
R2 =
Outputs 3.35k Timing
3.35k
Capacitor
VCC
Phase 16 2 3
+15V Detector Range 10 13 14
0.1F Inputs R1=6k Select
4 Phase
R =6k VCO Output
FM Input 0.1F Detector 1 VCO 15
6
10k
2.2k
4.7k 2.2k Op Amp VCO
XR-215 -
Output Sweep
Phase
5 Op Amp + VCO
Input Input
Comparator Gain
4.7k 0.1F 9 2 1 8 12 11
Bias VEE PD 4.7k 100k 10k Control
Out
68nF Demodulated Output Signal
vd(t)
mV
vf(t)
vf(t)
V
SUMMARY
Lectures 050 and 060 constitute a systems perspective of the LPLL
LPLL components are:
1.) Multiplying phase detector
2.) Low pass filter
3.) Voltage controlled oscillator
Locked state: Input frequency = VCO frequency
The phase response is low pass
The phase error response is high pass
Unlocked state:
- Hold range (H) frequency range over which a PLL can statically maintain phase
- Pull-in range (P) - frequency range within which a PLL will always lock
- Pull-out range (PO) dynamic limit for stable operation of a PLL
- Lock range (L) - frequency range within which a PLL locks within one single-beat
note between reference frequency and output frequency
The order of a PLL is equal to the number of poles in the open-loop PLL transfer
function
LPLL design Design the parameters Ko, Kd, , and the filter F(s) of the LPLL for a
given performance specification.
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003