QSOCs AXI TO AHB BRIDGE

1. INTRODUCTION ....................................................................................................................... 2
1.1 AMBA AXI (Advanced eXtensible Interface) .............................................................. 3
1.2 Advanced High-performance Bus (AHB).................................................................... 4
2. AXI TO AHB BRIDGE ........................................................................................................ 5
2.1 Features and Limitations of the Bridge ....................................................................... 6
3. Test Bench Architecture ........................................................................................................ 7
4. AXI TO AHB BRIDGE BLOCK DIAGRAM ................................................................................. 8
5. STIMULUS DRIVING FROM AXI MASTER ................................................................... 9
6. STIMULUS DRIVING FROM AHB SLAVE ................................................................................ 11
8. Functional Coverage ............................................................................................................ 16
9. STRUCTURE FOR AXI TO AHB BRIDGE PROJECT ................................................................... 19

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QSOCs AXI TO AHB BRIDGE

1. INTRODUCTION

Integrated circuits has entered the era of System -on-a-Chip (SoC), which refers to
integrating all components of a computer or other electronic system into a single
chip. It may contain digital, analog, mixed-signal, and often radio -frequency
functions all on a single chip substrate. With the increasing design size, IP is an
inevitable choice for SoC design. And the widespread use of all kinds of IPs has
changed the nature of the design flow, making On-Chip Buses (OCB) essential to
the design. Of all OCBs existing in the market, the Advanced Microcontroller Bus
Architecture (AMBA) bus system is widely used as the de facto standard SoC bus.
It facilitates development of multi-processor designs with large numbers of controllers
and peripherals. Since its inception, the scope of AMBA has, despite its name, gone far
beyond micro controller devices. Today, AMBA is widely used on a range of ASIC and
SoC parts including applications processors used in modern portable mobile devices like
smartphones. AMBA was introduced by ARM in 1996. The first AMBA buses were
Advanced System Bus (ASB) and Advanced Peripheral Bus. It is very commonly used
bus architecture.

In order to support high-speed pipelined data transfers, AMBA 4.0 supports a rich set of
bus signals, making the analysis of AMBA-based embedded systems a challenging
Proposition.

The goal of this project is to verify a AXI to AHB bridge. The bridge provides interface
between the high performance AXI and high bandwidth peripherals of AHB domain. The
AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible
Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4
transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4
master transactions and converts them to AHB master transactions and initiates them on
the AHB bus.

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QSOCs AXI TO AHB BRIDGE

1.1 AMBA AXI (Advanced eXtensible Interface)

The AMBA AXI protocol is targeted at high-performance, high-frequency system

designs and includes a number of features that make it suitable for high-speed submicron
interconnects.

The key features of the AXI protocol are:

Separate address/control and data phases
Support for unaligned data transfers using byte strobes
Burst-based transactions with only start address issued
separate read and write data channels to enable low-cost Direct Memory Access
(DMA)
Ability to issue multiple outstanding addresses
Out-of-order transaction completion
Easy addition of register stages to provide timing closure.

As well as the data transfer protocol, the AXI protocol includes optional extensions that
cover signaling for low-power operation.

The AXI protocol is burst-based. Every transaction has address and control information
on the address channel that describes the nature of the data to be transferred. The data is
transferred between master and slave using 5 channels including Write Address Channel,
Write Data Channel, Write Response Channel, Read Address Channel, Read Data
Channel (Write data channel to the slave or a read data channel to the master).In write
transactions, in which all the data flows from the master to the slave, the AXI protocol
has an additional write response channel to allow the slave to signal to the master the
completion of the write transaction.

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QSOCs AXI TO AHB BRIDGE

1.2 Advanced High-performance Bus (AHB)

AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs.
It is a bus interface that supports a single bus master and provides high-bandwidth
operation. AHB has address and data phase. Pipelining is done by the overlapping both
the phases.

AHB-Lite implements the features required for high-performance, high clock frequency
systems including:

burst transfers
Single-clock edge operation
Non-tristate implementation
Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.

It is highly pipelined. The most common AHB-Lite slaves are internal memory devices,
external memory interfaces, and high bandwidth peripherals. Although low-bandwidth
peripherals can be
Included as AHB-Lite slaves, for system performance reasons they typically reside on the
AMBA Advanced Peripheral Bus (APB). Bridging between this higher level of bus and
APB is done using a AHB-Lite slave, known as an APB bridge

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QSOCs AXI TO AHB BRIDGE

2. AXI TO AHB BRIDGE

The AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible
Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4
transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4
master transactions and converts them to AHB master transactions and initiates them on
the AHB bus.

AXI has five channels such as write address channel, Write data channel, write response
channel, Read address channel and Read data channel. AXI clock is Operating
independent of AHB clock. AXI to AHB converts AXI read and write transactions to
corresponding AHB read and write transactions. This bridge provides an interface
between high performance AXI processors and high bandwidth peripherals of AHB
protocol like memory controller, DMA controller, and Touchpad, SD card.

AXI uses hand shake mechanism for data transfer in all the five channels. The VALID
signal is asserted from master when valid address or control and data information is
available. The READY signal is asserted from slave when it can accept address or control
and data information. The AHB Bridge buffers address, control and data from AXI4
drives the AHB peripherals and returns data and response signal to the AXI4. It decodes
the address using an internal address map to select the peripheral. The bridge is designed
to operate when the AHB and AXI4-Lite have independent clock frequency and phase.
For every AXI channel, invalid commands are not forwarded and an error response
generated. That is once a peripheral accessed does not exist, the AHB Bridge will
generate DECERR as response through the response channel (read or write). And if the
target peripheral exists, but asserts ERR, it will give a SLVERR response.

The DUT used to verify in this project is LogiCORE IP AXI to AHB-Lite Bridge
(v1.00a) from Xilinx.

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QSOCs AXI TO AHB BRIDGE

2.1 Features and Limitations of the Bridge

The Xilinx AXI to AHB-Lite Bridge is a soft IP core with the following features:

AXI4 Slave Interface:

AXI interface is based on the AXI4 specification
Supports 1:1 (AXI to AHB) synchronous clock ratio
Connects as a 32/64-bit slave on 32/64-bit AXI4
Supports incrementing burst transfers (of length 1 to 256)
Supports wrapping burst transfers of length 2, 4, 8, and 16
Supports fixed burst transfers (of length 1 to 16)
Supports narrow transfers (8/16-bit transfers on a 32-bit bus and 8/16/32-bit
transfer on a 64-bit data bus)
Supports limited cache encoding and limited protection unit support
Supports address/data phase time out AHB-Lite Master Interface.

AHB-Lite Master Interface:

Supports AHB-Lite interface
Connects as a 32/64-bit Master on 32/64-bit AHB-Lite
Supports single burst transfers
Supports wrapping burst transfers of length 4, 8 and 16 and undefined burst length
AHB-Lite master does not issue incrementing burst transfers that cross 1 kB
address boundaries
Supports limited protection control
Supports narrow transfers (8/16-bit transfers on a 32-bit data bus and 8/16/32-bit
transfers on a 64-bit data bus)

Not Supported Features/Limitations

AXI4 Slave Interface

Data bus widths greater than 64 are not supported
No registers are implemented because posted writes are not supported
Locked, Barrier, trust zone, and exclusive operations are not supported
Out-of-order read transaction completion
Out-of-order write transaction completion
Unaligned/Sparse transfers (holes in strobes) are not supported
EXOKAY and DECERR responses to AXI4 are not supported
Low-power state is not supported
Secure accesses are not supported
AHB-Lite Master interface
Data bus widths greater than 64 are not supported
No cacheable access support

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QSOCs AXI TO AHB BRIDGE

3. Test Bench Architecture

axi_ahb_top

axi_ahb_test

Sequence item axi_sequence

Sequence

env
Axi
intf
SQR
SQR Driver
S
C Monitor
monitor
O
R ahb_agent DUT
E
B Ahb AXI TO AHB
O intf BRIDGE
A
R SQR driver
Driver
D
Monitor
monitor
ahb_agent

ahb_seq_item ahb_sequence

Testbench Architecture

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QSOCs AXI TO AHB BRIDGE

4. AXI TO AHB BRIDGE BLOCK DIAGRAM

Protocols Using: AXI4, AHB Lite (with Data Width 32/64)

AHB Lite
AXI SLAVE Master

AHB
AXI WRITE STATE
STATE MACHINE
AXI AHB
MACHINE

AXI READ
STATE
MACHINE TIME OUT
MODULE

AXI TO AHB BRIDGE

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QSOCs AXI TO AHB BRIDGE

5. STIMULUS DRIVING FROM AXI MASTER

Write Address
Write Queue
Sequence

Write Data
Queue
Driving
Read Logic AXI Interface
Sequence Read Address
Queue

Matching Queue

ID of Requests

Write Address
RESPONSE Response
HANDLER Queue

Write Data
Response
AXI SEQUENCE Queue AXI DRIVER

Stimulus Driving Logic For AXI Master

1.) Axi to Ahb Bridge

The bridge translates AXI4 transactions into AHB lite transactions. Data Bus may
be 32 or 64.
2.) Axi_seq_item,Ahb_seq_item
Describes the transaction level items for the Stimulus Driving. For axi part it has
size, address data like items.

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QSOCs AXI TO AHB BRIDGE

3.) Sequence
It creates sequences and drives it to the driver. Here we have write sequence and
read sequence for the axi master.
4.) Axi /Ahb Sequencer
It selects multiple sequences and serves as an arbiter for controlling transaction flow
of UVM.
5.) Axi/Ahb Driver
It drives the stimulus on to the DUT interface.
6.) Axi/Ahb Monitor
It samples the DUT interface and captures the information there in transactions that
are sent out to the scoreboard for further analysis.
7.) Axi/Ahb Agents
For Axi to Ahb Bridge, we have two different signal interfaces, each of which have
their own protocol. The UVM agent collects together a group of uvm_components
focused around a specific pin-level interface. The purpose of the agent is to provide
a verification component which allows users to generate and monitor pin level
transactions.
8.) Scoreboard
It compares the data coming from axi and ahb interface.
9.) Environment
The environment, or env, is a container component for grouping together sub-
components orientated around a block, or around a collection of blocks at higher
levels of integration.

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QSOCs AXI TO AHB BRIDGE

6. STIMULUS DRIVING FROM AHB SLAVE

DUT
S
AHB_DRIVER
E
Ahb_Interface
Q

U
AXI To AHB
E
Bridge
N

MEMORY E

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 QSOCs AXI TO AHB BRIDGE

7. AXI TO AHB BRIDGE TEST PLAN

AXI TO AHB BRIDGE TEST PLAN

DUT: AXI to AHB BRIDGE

SL
TEST CASE DESCRIPTION FEATURE STATUS PASS/FAIL
NO

BASIC TRANSACTIONS
Checking the
functionality of During reset condition the
DUT when it is ouputs of DUT will be some
1 reset_check in reset condition pre-configured value even if
by randomly we toggle the values to the
driving data to inputs
all the inputs Completed PASS
Driving data and control
information through 2
Writing to DUT
different channel to a
with a basic
peripheral and getting
2 basic_write_transaction write transfer of
response from another
single beat and
channel through flow
size as 4
control signals READY and
VALID Completed PASS
Writing to DUT
Reading data from a
with a basic
peripheral using two
3 basic_read_transaction Read transfer of
different channels using
single beat and
flow control mechanisms
size as 4 Completed PASS
Randomly
driving basic any number of transactions
4 multiple_read_write read and write is possible in AXI to AHB
transfers for bridge
multiple times Completed PASS
BURST TRANSACTIONS
Driving data as a
Data is written to a fixed or
4 fixed_burst_single_beat burst with single
fifo type memory
beat
Completed PASS
Repeated driving
multiple_fixed_ of data as fixed AXI4 protocol supports
5
burst_varying_length burst with maximum beats of 256
varying length Completed PASS

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 QSOCs AXI TO AHB BRIDGE

Data is written as a burst by

Driving data as giving start address
6 INCR_burst_single_beat burst of INCR only.Then address is
with length as 1 incremented w.r.t INCR
parameters Completed PASS
Driving data as
burst of INCR AXI4 protocol supports
7 INCR_length_check
with varying maximum beats of 256
Length Completed PASS
Driving data as AXI to AHB bridge maps
8 INCR_burst_length_2 burst of INCR INCR burst with length 2 as
with length as 2 INCR2 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
9 INCR_burst_length_4 burst of INCR INCR burst with length 4 as
with length as 4 INCR4 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
10 INCR_burst_length_8 burst of INCR INCR burst with length 8 as
with length as 8 INCR8 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
11 INCR_burst_length_16 burst of INCR INCR burst with length 16
with length as 16 as INCR16 in AHB side
Completed PASS
Driving Data as There is only of wrap 2,4,8
12 WRAP_length_check a WRAP with and 16.All others may throw
varying Length an error
Completed PASS
Driving data as AXI to AHB bridge maps
13 WRAP_burst_length_2 burst of WRAP WRAP burst with length 2
with length as 2 as WRAP2 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
14 WRAP_burst_length_4 burst of WRAP WRAP burst with length 4
with length as 4 as WRAP4 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
15 WRAP_burst_length_8 burst of with INCR burst with length 8 as
length as 8 WRAP8 in AHB side
Completed PASS
Driving data as AXI to AHB bridge maps
16 WRAP_burst_length_16 burst of INCR INCR burst with length 2 as
with length as 16 WRAP16 in AHB side
Completed PASS

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 QSOCs AXI TO AHB BRIDGE

Driving random
bursts with AHB protocol supports
17 burst_beat_size_with_aligned_addr
aligned address aligned transfers only
and varying size Completed PASS
UNALIGNED TRANSACTIONS
Driving data as a DUT converts unaligned
FIXED burst transfers into aligned
with unaligned address using STROBE
18 FIXED_unaligned_address
address with signals.AXI supports
different size and unaligned address,but AHB
lengths not Completed
Driving data as a DUT converts unaligned
INCR burst with transfers into aligned
unaligned address using STROBE
19 INCR_unaligned_address
address with signals.AXI supports
different size and unaligned address,but AHB
lengths not Completed
Driving data as a DUT converts unaligned
WRAP burst transfers into aligned
with unaligned address using STROBE
20 WRAP_unaligned_address
address with signals.AXI supports
different size and unaligned address,but AHB
lengths not Completed

ATOMIC ACCESS & OTHER FEATURES

AXI protocol supports

Driving random
NORMAL,PRIVILEGED
bursts with
21 protection_check and SECURE access.But
different levels
DUT doesn't support all the
of Protection
features.
Checking of
AXI4 supports
Exclusive access
LOCKED,NORMAL and
of AXI by using
22 exclusive_access EXCLUSIVE access to the
LOCK signal by
slave.But DUT and AHB
driving random
doesn't support
bursts
Checking of
AXI4 supports
Locked access
LOCKED,NORMAL and
of AXI by using
23 locked_access EXCLUSIVE access to the
LOCK signal by
slave.But DUT and AHB
driving random
doesn't support
bursts

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 QSOCs AXI TO AHB BRIDGE

Checking of
AXI4 supports
Normal access
LOCKED,NORMAL and
of AXI by using
24 normal_access EXCLUSIVE access to the
LOCK signal by
slave.But DUT and AHB
driving random
doesn't support
bursts
Checking the
Bridge supports only limited
25 cache_support_check cache unit of
features of Cache
AXI
Bridge doesn't support out
Checking out of
of order transaction.it helps
26 out_of_order_txn Order
finishing transfers from fast
Transaction
devices reather than slower.
Checking
AXI supports outstanding
outstanding
27 outsatnding_address_check address transactions,but
addresses
AHB doesn't.
transactions

28 data_interleaving_Check

Driving random
AXI supports 4KB locations
burst with out of
29 boundary_cross_check and AHB supports 1KB
boundary
locations
conditions
ERROR RESPONSES
Cheecking for
different errors AXI having
responses OKAY,EXOKAY,DECERR
30 error_response_check
associated and AHB having OKAY
withAXI to AHB and ERROR.
bridge
CORNER CASES
Giving Same Id's
to different
31 same_id_check
address for a
transaction

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QSOCs AXI TO AHB BRIDGE

8. Functional Coverage

Functional Coverage
Sl Cover
Cover Point Description Status Hit/Fail
No group

1 Write
Access
2 Read
It is writing to the same
address .DUT converts
unaligned transfers into
aligned address using
3 Fixed
STROBE signals.AXI
supports unaligned
address,but AHB does
not
Burst DUT converts unaligned
transfers into aligned
address using STROBE
4 Increment
signals.AXI supports
unaligned address,but
AHB not
CG-AXI
Here the address will
5 Wrap wrap after the address
boundary(Here its 4)
6 Protect_NSD
7 Protect_PSD
8 Protect_NND
9 Protect_NSI
Protect
10 Protect_PSI
11 Protect_NNI
12 Protect_PNI
13 Protect_PNI
14 Cache Cache Cache

15 Okay
Response
16 EXOKAY
17 SLVERR

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QSOCs AXI TO AHB BRIDGE

18 DECERR

19 Addr_align
Address_type
20 Addr_unalign
21 Address 0-1000 Divisible by 4
This will transfer single
22 Single
transfer i,e single beat
23 Increment
Undefined length burst
24 Undefined that has burst of length
one
The previous address is
25 INCR4
increments by 4
The previous address increments
26 INCR 8
by 8
The previous address is
27 INCR 16
Burst incremented by 16
Here to single address
28
the data is written
29 Wrap
The address will incrent
30 Wrap 4
with 4 wrap to boundary
The address will
31 Wrap 8 increment by 8 and wrap
to the boundary
The address will
32 Wrap 16 increment by 16 and
wrap to the boundary
Undefined length burst
33 Idle that has burst of length
one
Burst is taking place but
transfer cannot take
place immediately ,
34 Busy
Transaction Undefined length can
Type have busy as last
transition

It is single or first transfer

of the burst . Single
Non
35 transfer on the bus are
Sequential
treated as burst of length
one

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QSOCs AXI TO AHB BRIDGE

If its sequencial address

is related to the previous
36 Sequential transfer , The control
information is same as
previous transfer
37 Byte When size is byte
38 Half_word
Size
39 Word When size is half_byte
40 Double Word
41 Address
Address lying between 1k
42 1000 to 2000
and 2k

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QSOCs AXI TO AHB BRIDGE

9. STRUCTURE FOR AXI TO AHB BRIDGE PROJECT

AXI_TO
AHB Bridge

doc script sim src testlib verif

agent env intf

Directory Structure
Doc : Keep all the related documents in this file
Script : Keep all the Scripting file like run_test ,regression files
Sim : All the simulations has to done here
Src : keep all the source rtl file in this directory
Testlib : it having all the sequence items,sequences,test files for
verification
Verif :Includes three sub directories agent, env and intf
Intf :Keep all the interface files in here
Env: it consist environment, top, scoreboard and packages.
Agent : it consists sequencer, driver monitor related files

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