JEDEC

STANDARD

Procedure for Measuring N-Channel

MOSFET Hot-Carrier-Induced
Degradation Under DC Stress

JESD28-A
(Revision of JESD28)

DECEMBER 2001

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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 JEDEC Standard No. 28-A

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-

INDUCED DEGRADATION UNDER DC STRESS

CONTENTS

Page

Introduction ii

1 Scope 1

2 Applicable standards 1

3 Terms and definitions 2

4 Technical requirements 4
4.1 Equipment requirements 4
4.2 Test structure requirements 4
4.3 Measurement requirements 4

5 Hot carrier stress test procedure 5

5.1 Determining stress bias conditions 6
5.2 Selecting test devices 7
5.3 Initial characterization 7
5.4 Stress cycle 7
5.5 Interim characterization 7
5.6 Stress termination 7

6 Data analysis 8

7 Precautions 9
7.1 Test sample 9
7.2 Stress 9
7.3 Interim measurements 9
7.4 Data analysis 10

8 Required reporting 10
8.1 Test transistor identification 10
8.2 VDD, VBB 10
8.3 MOSFET channel length and width 10
8.4 VDS at stress, VBS at stress, VGS at stress 10
8.5 Initial IB at stress 10
8.6 Initial ID(lin), gm(max), VT(ci), VT(ext), ID(sat) 11
8.7 tTAR for ID(lin), gm(max), VT(ci), VT(ext), ID(sat) 11
8.8 Total test time 11
8.9 Measurement temperature 11

-i-
JEDEC Standard No. 28-A

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-

INDUCED DEGRADATION UNDER DC STRESS

Introduction

Hot-carrier-induced degradation of MOSFET parameters over time is an important reliability

concern in modern microcircuits. High energy carriers, also called hot carriers, are generated in
the MOSFET by the large channel electric fields near the drain region. The electric fields
accelerate the carriers to effective temperatures well above the lattice temperature. These hot
carriers transfer energy to the lattice through phonon emission and break bonds at the Si/SiO2
interface. Carriers also are injected into the SiO2 and can be trapped there. The trapping or bond
breaking creates oxide charge and interface traps that affect the channel carrier mobility and the
effective channel potential.

Interface traps and oxide charge affect transistor performance in all operating regimes.
Parameters such as threshold voltage, transconductance, and drive currents are commonly
monitored to identify performance change. The rate of change of each parameter is determined
by the MOSFET design and IC process details. Both p and n-channel MOSFETs are affected by
hot carriers. This document addresses only n-channel MOSFETs.

-ii-
 JEDEC Standard No. 28-A
Page 1

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-

INDUCED DEGRADATION UNDER DC STRESS

(From JEDEC Board Ballot JCB-01-48, formulated under the cognizance of the JC-14.2, Hot
Carrier Working Group.)

1 Scope

This document describes an accelerated test for measuring the hot-carrier-induced degradation of
a single n-channel MOSFET using dc bias. The purpose of this document is to specify a
minimum set of measurements so that valid comparisons can be made between different
technologies, IC processes, and process variations in a simple, consistent and controlled way.
The measurements specified should be viewed as a starting point in the characterization and
benchmarking of the transistor manufacturing process.

In this document, degradation criteria are specified. However, these are to be used for
comparison purposes only and should not be used as acceptance or rejection criteria. It is also
important to realize that this procedure should not be interpreted as a means of predicting MOS
IC failure rates. The impact of the n-channel MOSFET degradation on actual circuit performance
is not addressed in this document. Though this procedure was developed for wafer level
stressing, it is also applicable to packaged structures.

The material contained in this publication was formulated under the cognizance of the JEDEC
JC-14.2 Committee.

2 Applicable standards

ASTM F616-86, Standard Method for Measuring MOSFET Drain Leakage Current

ASTM F617-86, Standard Method for Measuring MOSFET Linear Threshold Voltage

ASTM F1096-87, Standard Method for Measuring MOSFET Saturated Threshold Voltage

JESD77-A, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and
Optoelectronic Devices

JESD60, A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation

Under DC Stress
JEDEC Standard No. 28-A
Page 2

3 Terms and definitions

3.1 Metal oxide semiconductor field effect transistor (MOSFET): An insulated-gate, field-
effect transistor in which the insulating layer between each gate electrode and the channel is
oxide material; the gate is metal or another highly conductive material.

NOTE See JESD77-B for further clarification of MOSFET terms.

3.2 drain voltage (VDS): The dc drain-source voltage.

3.3 gate voltage (VGS): The dc gate-source voltage.

3.4 bulk voltage (VBS): The dc bulk-source voltage.

3.5 drain current (ID): The direct current into the drain contact.

3.6 bulk current (IB): The direct current into the bulk contact.

3.7 forward mode: The mode in which the drain to source polarity during test is the same as
that during the application of stress.

3.8 nominal power supply voltage (VDD): The nominal drain supply voltage of the technology.

3.9 nominal bulk supply voltage (VBB): The nominal bulk voltage of the technology.

3.10 linear drain voltage (VDS(lin)): The dc drain-source voltage for linear region
measurements.

NOTE Typically, VDS(lin) is 100 mV for VDD = 5 V.

3.11 linear drain current (ID(lin)): The dc drain current measured when the transistor is biased
in the linear region.

NOTE Typical dc bias voltages for ID(lin) measurements are VDS = 0.1 V, VGS = VDD, VBS = VBB.

3.12 maximum linear transconductance (gm(max)): The maximum slope of the ID-VGS curve in
the linear region. The gate voltage shall be varied in increments no greater than 0.02 V from
below the turn-on voltage to a value great enough to ensure that the maximum slope point has
been reached. The slope shall be calculated using a three-point linear least squares best fit
algorithm as defined in ASTM F617-86 standard.

NOTE Typical dc bias voltages for gm(max) measurements are VDS = VDS(lin), VBS = VBB.
 JEDEC Standard No. 28-A
Page 3

3 Terms and definitions (contd)

3.13 constant current threshold voltage (VT(ci)): The constant current threshold voltage is
defined as
(
VT(ci) = VGS @ I D = 0.1A
W
L ) (1)

VT(ci) is the gate voltage applied to the device at which the drain current is equal to 0.1 A times
the ratio of gate width (W) to gate length (L). W and L are the gate width and gate length as
printed on the wafer.

NOTE 1 The measurement technique must determine VT(ci) to within a 1 mV resolution. If the VGS step
size is larger than 1 mV, then a linear interpolation method may be used to achieve the 1 mV resolution.

NOTE 2 Typical dc bias voltages for VT(ci) measurements are VDS = VDS(lin), VBS = VBB for linear region
measurment, or VDS = VDS(sat), VBS = VBB for saturation region measument.

3.14 extrapolated threshold voltage (VT(ext)): The ASTM F617-86 document describes a
technique for extracting the extrapolated threshold voltage based on a measurement of the
maximum slope (gm(max)) of the ID-VGS curve. VT(ext) can be calculated using

I D (g m(max) )
VT(ext) = VGS (g m(max) ) (2)
g m(max)

where: VGS(gm(max)) is the gate voltage at the point of the maximum slope of the ID-VGS curve.
ID(gm(max)) is the drain current at the point of the maximum slope of the ID-VGS curve.
VDS is typically VDS(lin).

NOTE DC bias voltages for VT(ext) measurements are VDS = VDS(lin), VBS = VBB for linear
measurement or VDS = VDS(sat), VBS = VBB for saturation measurement.

3.15 saturation drain current (ID(sat)): The dc drain current measured when the transistor is
biased in the saturation region.

NOTE Typical DC bias voltages for ID(sat) measurements are VDS = VGS = VDD, VBS = VBB.

3.16 time to target (tTAR): The stress time at which a particular parameter has changed by a
given value from its unstressed value. 10% change is a commonly used value but a different
value can be used based on test speed, instrument needs or circuit requirements. It should be
noted that these values have been arbitrarily chosen, and no relationship to circuit failure should
be inferred.
JEDEC Standard No. 28-A
Page 4

4 Technical requirements

4.1 Equipment requirements

The measurement system must be capable of the simultaneous application of voltage and
measurement of current at the gate, drain, and substrate terminals of the device. Before any data
collection, the repeatibility of the monitored parameters must be within 0.5%.

4.2 Test structure requirements

An n-channel MOSFET fabricated on a p-type bulk substrate/well should be used. A minimum

channel length of the process is recommended, but other channel lengths may also be used.
Transistors with narrow channel widths should be avoided. A channel width of greater than 10
m at the nominal channel length is recommended to avoid narrow-channel, hot carrier effects.

NOTE Narrow-width devices may also be studied with this test procedure.

All four terminals of the device must be contacted; i.e. terminals shall not be floating. To
minimize parasitic voltage drops between the applied drain stress voltage and the device, the
resistance from the probe pads to the device source, drain, and substrate should be minimized.

4.3 Measurement requirements

The device should be set up at the wafer level on a probe station providing a stable platform via a
vacuum chuck or as a packaged part in a test fixture. Once set, this temperature must be
maintained to within +/- 2.0 C of this set point for the duration of the measurement.

At the end of each hot carrier stress interval, the stress is terminated and device parameters are
measured. The stress time interval should be known to an accuracy of +/- 1%.
 JEDEC Standard No. 28-A
Page 5

5 Hot carrier stress test procedures

Figure 1 describes the hot carrier stress test procedure.

Select Test
Device

Initial
Characterization

NO
Valid?

YES

Record Data

Stress Cycle

Interim
Characterization
Increment
Stress Timer

Record Data

NO
Termination?

YES

Stop Test

Figure 1 The hot carrier stress test procedure

Initial tests are used to select a good device (see 5.2) and to determine initial unstressed
parameter values. If the device is determined to be good data is recorded and the stress cycle
begins. During the stress cycle the device is biased using the selected stress bias condition.
Since parameter degradations typically exhibit a power-law behavior the recommended stress
intervals are 1/2 decade time-steps (see 5.4). After each stress cycle the device parameters are
again determined, recorded and compared to the initial values. If the parameter degradation
exceeds the termination criteria (see 5.6), testing ends. Otherwise, another stress cycle is
initiated. The sections below describe in greater detail the hot carrier stress algorithm.
JEDEC Standard No. 28-A
Page 6

5 Hot carrier stress test procedures (contd)

5.1 Determining stress bias conditions

Hot carrier stressing should be performed under constant voltage bias conditions at the
temperature specified in 4.3.

To determine the drain stress voltage, the ID-VDS curves for the device must be examined.
Examples of ID-VDS characteristic curves for an n-channel MOSFET are shown in Figure 2.

0.025

Saturation Region
0.02

Linear
0.015 VGS = 4.0 V
I (A)

Region Breakdown
D

VGS = 3.5 V
0.01 Region
VGS = 3.0 V

0.005

0
0 2 4 6 8 10
VDS (V)
Figure 2 N-channel MOSFET drain current characteristics

The drain current is plotted as a function of drain voltage at three different gate bias conditions.
The linear, saturation, and breakdown regions are shown on the plot. Transistor breakdown,
whether due to drain avalanching, punchthrough, or bipolar snapback, determines the maximum
VDS stress limit. The maximum Vds stress limit should be deterimined at the Vgs which produces
the worst case degradation. The minimum realistic drain stress bias is restricted by long test
times or by inaccurate extrapolations to tTAR. Maximum stress conditions should be set to
minimize activating any effect that is not seen at the operating conditions.

For a given selected drain bias condition, the corresponding gate bias should be set to induce the
maximum possible degradation. Operating conditions of the device should be taken into account
when setting the gate bias voltage. Peak IB gate biasing may produce the greatest rate of
n-channel MOSFET degradation, but this should be verified for each technology. A series of hot
carrier tests at a fixed Vds and at least 5 Vgs values can be used to estimate the peak degradation.
 JEDEC Standard No. 28-A
Page 7

5 Hot carrier stress test procedures (contd)

5.2 Test devices

A transistor with gate, drain, and source leakage currents that meet the requirements of the
process shall be used. Transistors used for drain breakdown, peak IB measurements, or for any
other test that use bias voltages greater than nominal operating conditions shall not be used for
hot carrier stress testing.

5.3 Initial characterization

Monitored parameters shall include VT(ci), VT(ext), gm(max), ID(lin), and ID(sat) all in the forward mode.
The parameters shall be recorded, as these will be used for determining parametric shifts. Other
parameters may also be measured.

5.4 Stress cycle

The transistor will be stressed with the voltages determined in 5.1. The voltages shall be applied
in the following order: VBS first, VGS second, and VDS last. The stress begins when VDS has been
applied. The stress continues until a stress time interval has been reached. Turning off the bias
shall be done in the reverse order, with VDS first, VGS second, and VBS last.

Since the typical degradation follows a power-law with time, the recommended stress intervals
are 1/2 decade time-steps. For example, the cumulative stress times could be 10, 30, 100, 300,
1000, 3000, 10000, 30000, and 100000 seconds. In this example, the device would be stressed
for 10 seconds. After this stress interval, the device parameters are measured. The device would
then be stressed for 20 additional seconds and the parameters again measured. The next stress
interval would be 70 seconds. This procedure continues until stress termination occurs.

5.5 Interim characterization

The five parameters that shall be measured and recorded are VT(ci), VT(ext), gm(max), ID(lin) and ID(sat).
Other parameters may also be measured.

5.6 Stress termination

Each device shall be stressed until at least one parameter reaches or exceeds the specified target
value (see 3.16), or two time decades of valid data have been taken (see 7.4).
JEDEC Standard No. 28-A
Page 8

6 Data analysis

The percent change values are calculated from:

P(t) - P(0)
Y(t) = * 100 (3)
P(0)

where: P(0) is the initial parameter value.

P(t) is the parameter value at time t.

The absolute value of the change in each parameter shall be fitted to the following equation using
a least-squares fit:

Y(t) = Ct n (4)

where: Y(t) is the absolute value change in the parameter.

t is the cumulative stress time.

For each parameter analyzed, tTAR should be interpolated or extrapolated from the data based on
the C and n values from this least-squares fit. Figure 3 shows an example of the use of equation
4. See applicable precautionary notes in 7.3 and 7.4.

100
Y(t), percent change

10

t TAR
0.1
0.1 1 10 100 1000 10000 100000 1000000
t, stress time (s)

Figure 3 Example of power law fit to hot carrier stress data

 JEDEC Standard No. 28-A
Page 9

7 Precautions

While the procedures outlined above are quite straightforward, there are subtle effects that can
cause significant errors. Listed below are some precautions that shall be followed to ensure
correct implementation of the procedure.

7.1 Test sample

It is essential that devices used in hot carrier stress testing should be unstressed devices. Test
devices should not have operated at a bias condition exceeding the nominal power supply voltage
of the technology. Prestressed devices can show an appreciable shift in tTAR when compared to
unstressed parts.

7.2 Stress

Since the degradation is a sensitive exponential function of applied stress voltage, it is essential
that the correct stress bias voltage be applied to the device under test. Discrepancies can arise
due to high series resistance caused by poor probe-to-pad contact or from device short circuits
leading to power supply compliance limitations. The optimal gate stress bias voltage must be
determined from identically processed but different devices from those to be hot carrier stress
tested. It must be determined that the MOSFET gate has not shorted during stress.

7.3 Interim measurements

Certain technologies have shown partial parameter recovery once stress biasing is removed. In
this case, parameter measurements should be made as soon as possible after each stress cycle has
been completed, and additional stressing restarted immediately.

Significant device self-heating may occur during stress testing. This effect may be more
pronounced in packaged test transistors. This may effect the comparison of hot carrier test results
especially between wafer and packaged-parts.

When a device degradation parameter reaches its specified stress termination criteria, it may be
worth continuing the stress beyond tTAR. This ensures a good interpolation of data around tTAR,
especially if the degradation data is noisy.
JEDEC Standard No. 28-A
Page 10

7 Precautions (contd)

7.4 Data analysis

A simple theory of hot carrier degradation assumes that the degradation follows a power law with
stress time for interface-states. That is, the fractional change in a parameter versus the stress
time is a straight line on a log-log plot. This is not always the case. The slope of the log-log
degradation curve can decrease with increasing stress time. It may be necessary to take these
effects into account when fitting degradation data. If the shift criterion is exceeded during a
stress, tTAR should be determined by using a linear interpolation between the surrounding points.
If the shift criterion is not exceeded, a power law extrapolation should be used based on the last
two time decades.

If the stress voltage is relatively low, the first few degradation measurements may produce
parameter changes that are smaller than the test equipment can resolve. These data points should
not be included in the data analysis (see figure 4).

8 Required reporting

As a minimum, the following information relevant to the n-channel MOSFET hot carrier
degradation measurement should be reported.

8.1 Test transistor identification

Provide information sufficient to uniquely identify the MOSFET tested.

8.2 VDD, VBB

The nominal power supply and bulk voltage for the process technology (3.8, 3.9).

8.3 MOSFET channel length and width

The drawn gate dimensions for the n-channel MOSFET under test.

8.4 VDS at stress, VBS at stress, VGS at stress

The MOSFET drain, bulk and gate voltage applied during stress.

8.5 Initial IB at stress

The initial MOSFET bulk current at stress conditions.

 JEDEC Standard No. 28-A
Page 11

8 Required reporting (contd)

8.6 Initial ID(lin), gm(max), VT(ci), VT(ext), ID(sat)

The initial (pre-stress) characterization data (see 3.11-3.15). Terminal voltage conditions for
monitor parameters should be given.

8.7 tTAR for ID(lin) , gm(max), VT(ci), VT(ext), ID(sat)

The calculated Time to Target (see 3.16) for each of the five required parameters (if possible).
The failure criteria should also be reported.

8.8 Total test time

The total cumulative stress time.

8.9 Measurement temperature

The chuck or fixture temperature maintained during the measurement (4.3).

JEDEC Standard No. 28-A
Page 12