Simulation Lab File

EXPERIMENT-1
AIM:Design and simulation of half-adder and full-adder using different modeling.
EDA TOOL USED: Xilinx ISE 14.7
METHODOLOGY:
HALF ADDER
An half adder is a combinational circuit which logically adds two single bit binary digits and
gives the single bit outputs sum and carry. Let a, b be two single bit inputs to a half adder and
sum, carry be the outputs. The truth table and boolean expression obtained from the binary
addition of a and b are given below.
TRUTH TABLE :
Table 1.1 Truth table of an half adder
INPUTS OUTPUTS
A B sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
BOOLEAN EXPRESSIONS :
sum= a b
carry = a.b
CIRCUIT DIAGRAM :
Fig 1.1 Circuit diagram for an half adder

APPLICATIONS :
Half adders are used to build full adder circuit which is one of the primary element in an
ALU of a processor.
FULL ADDER
A full adder is a combinational circuit which logically adds three single bit binary digits and
gives the single bit outputs sum and carry. It is similar to the half adder except that it adds two
binary inputs along with an input carry. Let a, b be two single bit inputs and c_in an input
carry to the full adder, let sum, c_out be the sum and output carry. The truth table and
boolean expression obtained from the binary addition of a and b are given below.
TRUTH TABLE :
Table 1.2 Truth table of a full adder
INPUTS OUTPUTS
A B c_in sum c_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
sum = a b c_in
c_out = a.b + b.c_in +a.c_in
APPLICATIONS :
A parallel adder or a carry look ahead adder can be constructed by cascading full adders.
These adders are used in real time single bit additions which have an input carry bit.
CIRCUIT DIAGRAM :
Fig 1.2 Circuit diagram for a full adder
VERILOG CODE :
HALF ADDER
A. Gate-level modeling
module HA_1(input in1, input in2, output sum, output carry);
xor g1(sum,in1,in2);
and g2(carry,in1,in2);
endmodule
B. Data flow modeling

moduleHA_dataflow(input a, nput b, output sum, output carry);
assign {carry,sum}=a+b;
endmodule
C. Behavioral modeling
module HA( input a, input b, output reg sum, output regcout);
always @(a or b)
begin
case ({a,b})
2'b00:begin sum=0;cout=0; end
endcase
end
endmodule
FULL ADDER
module FA_1(input a, input b, input c_in, output sum, output c_out);
wire [2:0]w;
xor g1(sum,a,b,c_in);
and g2(w[0],a,b);
and g3(w[1],a,c_in);
and g4(w[2],c_in,b);
or g5(c_out,w[0],w[1],w[2]);
endmodule

moduleFA_dataflow(input a, input b, input c_in, output sum, output c_out);
assign {c_out,sum}=a+b+c_in;
endmodule
module FA(input a, input b, input c, output reg sum, output regcout);

always@(a,b,c)
begin
case({a,b,c})
endcase
end
endmodule
INPUT TEST BENCH

HALF ADDER
initial begin
in1 = 0; in2 = 0; // Initialize Inputs
#100; // Wait 100 ns for global reset to finish
in1 = 0; in2 = 1; #100;
in1 = 1; in2 = 0; #100;
in1 = 1; in2 = 1; #100;
end
initial begin
a = 0; b = 0; // Initialize Inputs
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
end
initial begin
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
end
FULL ADDER
initial begin
a = 0; b = 0; c_in = 0; // Initialize Inputs
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c_in = 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end

initial begin
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c_in = 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end
initial begin
a = 0; b = 0; c = 0; // Initialize Inputs
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;
end
RTL SCHEMATIC VIEW
HALF ADDER
Fig 1.3 Gate-level schematic of half adder
Fig 1.4 Data flow schematic of half adder

Fig 1.5 Behavioral modeling schematic of half adder
FULL ADDER
Fig 1.6 Gate-level schematic of full adder

Fig 1.7 Data flow schematic of full adder

Fig 1.8 Behavioral schematic of full adder
OUTPUT WAVEFORM
HALF ADDER
Fig1.9 Output waveform of gate-level half adder

Fig1.10 Output waveform of data flow half adder

Fig1.11 Output waveform of behavioral half adder

FULL ADDER
Fig1.12 Output waveform of gate-level full adder
Fig1.13 Output waveform of data flow full adder

Fig1.14 Output waveform of behavioral full adder
RESULT
The half adder and full adder circuits were designed and simulated in gate-level, data flow and
behavioral modeling abstractions using Xilinx ISE design suite.
EXPERIMENT-2
AIM: Design and simulation of half-subtractor and full-subtractor
METHODOLOGY:
HALF SUBTRACTOR
An half subtractor is a combinational circuit which logically subtracts two single bit binary digits
and gives the single bit outputs difference and borrow. Let a, b be two single bit inputs to a
half subtractor and diff, b_out be the outputs. The truth table and boolean expression
obtained from the binary subtraction of a and b are given below.
TRUTH TABLE :
Table 2.1 Truth table of an half subtractor
INPUTS OUTPUTS
A B Diff b_out
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
diff = a b
b-out = .b
CIRCUIT DIAGRAM :
Fig 2.1 Circuit diagram for an half subtractor

FULL SUBTRACTOR
A full subtractor is a combinational circuit which logically subtracts three single bit binary digits
and gives single bit outputs difference and borrow. It is similar to the half subtractor except that
it subtracts two binary inputs including an input borrow. Let a, b be two single bit inputs and
b_in an input borrow to the full subtractor, let diff, b_out be the difference and output
borrow respectively. The truth table and boolean expression obtained from the binary subtraction
of a and b are given below.
TRUTH TABLE :
Table 2.2 Truth table of a full subtractor
INPUTS OUTPUTS
A B b_in diff b_out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
sum = a b b_in
c_out = .b+b.b_in+.b_in
APPLICATIONS :
In logic circuits subtraction is implemented using the adders which are already
available, we can also use subtractors instead of adders in a circuit and we can
perform addition, subtraction, multiplication, division of two binary numbers.
CIRCUIT DIAGRAM :
Fig 2.2 Circuit diagram for a full subtractor
VERILOG CODE :
HALF SUBTRACTOR
module HS_1(input a, input b, output diff, output b_out);
wirea_bar;
xor g1(diff,a,b);
not g2(a_bar,a);
and g3(b_out,a_bar,b);
endmodule

modulehalf_subtractor_DF(input a, input b, output diff, output c_out);
assign {c_out,diff} = a-b;
endmodule
modulehalf_sub_behavioral(input a, input b, output reg diff, output regb_out);
always@(a,b)
begin
case({a,b})
2'b00:begin diff=0; b_out=0; end
endcase
end
endmodule
FULL SUBTRACTOR
module FS_1(input a, input b, input c_in, output diff, output b_out);
wire a_bar,w1,w2,w3;
xor g1(diff,a,b,c_in);
not g2(a_bar,a);
and g3(w1,a_bar,c_in);
and g4(w2,a_bar,b);
and g5(w3,b,c_in);
or g6(b_out,w1,w2,w3);
endmodule

modulefull_subtractor_DF(input a, input b, input c_in, output diff, output b_out);
assign {b_out,diff} = a-b-c_in;
endmodule
modulefull_sub_behavioral(input a, input b, input c_in, output reg diff, output

regb_out);
always@(a,b,c_in)
begin
case({a,b,c_in})
endcase
end
endmodule
INPUT TEST BENCH :
HALF SUBTRACTOR
initial begin
in1 = 0; in2 = 0; // Initialize Inputs
in1 = 0; in2 = 1; #100;
in1 = 1; in2 = 0; #100;
in1 = 1; in2 = 1; #100;
end

initial begin
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
end
initial begin
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
end
FULL SUBTRACTOR
initial begin
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c _in= 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end

initial begin
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c _in= 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end
initial begin
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c _in= 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end
RTL SCHEMATIC VIEW :
HALF SUBTRACTOR
Fig 2.3 Gate-level schematic of half subtractor

Fig 2.4 Data flow schematic of half subtractor

Fig 2.5 Behavioral schematic of half subtractor
FULL SUBTRACTOR
Fig 2.6 Gate-level schematic of fullsubtractor

Fig 2.7 Data flow schematic of fullsubtractor

Fig 2.8 Behavioral schematic of fullsubtractor
OUTPUT WAVEFORM :
HALF SUBTRACTOR
Fig2.9 Output waveform of gate-level half subtractor

Fig 2.10 Output waveform of data flow half subtractor
Fig 2.11 Output waveform of behavioral half subtractor
FULL SUBTRACTOR
Fig 2.12 Output waveform of gate-level full subtractor

Fig 2.13 Output waveform of data flow full subtractor
Fig 2.14 Output waveform of behavioral full subtractor
RESULT
The half subtractor and full subtractor circuits were designed and simulated in gate-level, data
flow and behavioral modeling abstractions using Xilinx ISE design suite.
EXPERIMENT-3
AIM: Design and simulation of 4-bit parallel adder
METHODOLOGY :
A 4-bit parallel adder is a combinational arithmetic circuit that adds two 4-bit binary numbers
along with a carry and gives the 4-bit sum and a carry. This can be implemented using 4 full
adders where each full adder does 1-bit addition and the carry from each adder is given to next
higher order full adder. As carry from each stage is given to the next stage parallel adder is also
known as ripple carry adder.
Let a, b be two 4-bit inputs and c_in a input carry, let s, c_out be the 4-bit sum
and output carry. The implementation and boolean expression for the binary addition of a and
b are given below.
CIRCUIT DIAGRAM :
Fig 3.1 Circuit diagram for a 4-bit parallel adder using full adders
s[i] = a[i] b[i] c[i] 0i3
c_out = a[3]b[3] + b[3]c[3] + a[3]c[3]

VERILOG CODE :
module PA_FA_DF(input [3:0] A, input [3:0] B, input c_in,
output [3:0] sum, output c_out);
wire c1,c2,c3;
FA_dataflowf0(A[0],B[0],c_in,sum[0],c1); //module instantiation
FA_dataflowf1(A[1],B[1],c1,sum[1],c2);
FA_dataflowf2(A[2],B[2],c2,sum[2],c3);
FA_dataflowf3(A[3],B[3],c3,sum[3],c_out);
endmodule
//full adder module
moduleFA_dataflow(input a, input b, input c_in, output sum, output c_out);
assign {c_out,sum}=a+b+c_in;
endmodule
INPUT TEST BENCH :

initial begin
A = 4'b1101; // Initialize Inputs
B = 4'b1000;
c_in = 1;
A = 4'b1011;B = 4'b0100;c_in = 0;
#200;
A = 4'b1001;B = 4'b0110;c_in = 1;
#200;
end
Fig 3.2 Schematic of parallel adder using full adder

OUTPUT WAVEFORM
Fig 3.3 Output wave form of the parallel adder
RESULT
The 4-bit parallel adder circuit was implemented using four full adders with module instantiation
in Xilinx ISE design suite.
EXPERIMENT-4
AIM :Design and simulation of full-adder using half-adder
METHODOLOGY:
A full adder is a combinational circuit which logically adds three single bit binary digits and
gives the single bit outputs sum and carry. As we have seen a full adder can be constructed using
basic logic gates, another way of doing it is using two half adders and an OR gate. Let a, b
be two single bit inputs and c_in an input carry, let sum, c_out be the sum and output carry.
Now a, b are first given to an half adder, sum bit of first halfadder and c_in are given
to a second half adder which gives sum. Now c_out can be obtained by giving output carry of
both the half adders to an OR gate. The truth table and boolean expression obtained from the
binary addition of a and b are given below.
TRUTH TABLE :
Table 4.1 Truth table of a full adder
INPUTS OUTPUTS
A B c_in sum c_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
sum of HA1 = a b sum of HA2 = a b c_in

c_out of HA1 = a.b c_out of HA2 = (a b).c_in
sum = a b c_in
c_out = (a b).c_in + a.b
CIRCUIT DIAGRAM :
Fig 4.1 Circuit diagram for a full adder using half adders
VERILOG CODE :
module FA_HA(output s, output cout, input A, input B, input C);
wire w1,w2,w3;
HA_dataflowh1(A,B,w1,w2); //module instantiation
HA_dataflowh2(w1,C,s,w3); //module instantiation
assigncout=w2+w3;
endmodule
//half adder module
moduleHA_dataflow(input a, nput b, output sum, output carry);
assign {carry,sum}=a+b;
endmodule
INPUT TEST BENCH :

initial begin
a = 0;b = 0;c_in = 1;#100;
a = 0;b = 1;c_in = 0;#100;
a = 0;b = 1;c_in = 1;#100;
a = 1;b = 0;c_in = 0;#100;
a = 1;b = 0;c_in = 1;#100;
a = 1;b = 1;c_in = 0;#100;
a = 1;b = 1;c_in = 1;#100;
end
Fig 4.2 Schematic of full adder using half adder
OUTPUT WAVEFORM :
Fig 4.3 Output waveform of a full adder using half adder
RESULT :
The full adder circuit was implemented and simulated using half adders with module
instantiation in Xilinx ISE design suite.
EXPERIMENT-5
AIM: Design and simulation of 4:1 multiplexer.
METHODOLOGY :
A multiplexer is an arithmetic combinational circuit which takes one of its inputs as an output
based upon the select lines. A 4:1 mux has 4 inputs, 2 select lines (the control inputs) and an
output. Let in1, in2, in3, in4 be four inputs and s1, s0 be the select lines; now the mux gives four
inputs at the output one for each binary combinations of s1, s0. The truth table and boolean
expression for a 4:1 multiplexer are given below.
TRUTH TABLE :
Table 5.1 Truth table of a 4:1 mux
INPUTS (select lines) OUTPUT
s1 s0 Out
0 0 in1
0 1 in2
1 0 in3
1 1 in4
.0
out = 1 .in1 + 1
.s0.in2 + s1.0
.in3 + s1.s0.in4
APPLICATIONS :
Multiplexers are used in telephone exchange for time division multiplexing.

In some processors mux is used to decrease the number of lines by multiplexing both data
and address lines on a single bus.
4:1 mux can be used for implementing higher order multiplexers.
CIRCUIT DIAGRAM :
Fig 5.1 Circuit diagram 4:1mux
VERILOG CODE :
module mux_4x1_GL(input in1, input in2, input in3,
input in4, input s0, input s1, output out);
wire w1,w2,w3,w4,s0_bar,s1_bar;
not g1(s0_bar,s0);
not g2(s1_bar,s1);
and g3(w1,s0_bar,s1_bar,in1);
and g4(w2,s0_bar,s1,in2);
and g5(w3,s0,s1_bar,in3);
and g6(w4,s0,s1,in4);
or g7(out,w1,w2,w3,w4);
endmodule

module mux_4x1(input [3:0] i, input [1:0] s, output out);
assign out = s[1]?(s[0]?i[3]:i[2]):(s[0]?i[1]:i[0]);
endmodule
module mux_4x1_behavioral(input [4:1] in, input [1:0] s, output reg out);
always@(in,s)
begin
case({s[1],s[0]})
2'b00:out=in[1];
2'b01:out=in[2];
2'b10:out=in[3];
2'b11:out=in[4];
endcase
end
endmodule
INPUT TEST BENCH
initial begin
in1 = 0; in2 = 1; in3 = 1; in4 = 0; // Initialize Inputs
s0 = 0; s1 = 0;
s0 = 0; s1 = 1; #100;
s0 = 1; s1 = 0; #100;
s0 = 1; s1 = 1; #100;
end

initial begin
i = 4'b1101; // Initialize Inputs
s = 2'b00;
s = 2'b01; #100;
s = 2'b10; #100;
s = 2'b11; #100;
s = 2'b00; #100;
s = 2'b01;
end
initial begin
in = 4'b1011; // Initialize Inputs
s = 2'b00;
s = 2'b01; #100;
s = 2'b10; #100;
s = 2'b11; #100;
end
Fig 5.2 Schematic of Gate-level modeling of 4:1 mux

Fig 5.3 Schematic of Data flow of 4:1 mux
Fig 5.4 Schematic of behavioral of 4:1 mux

OUTPUT WAVEFORM
Fig 5.5 Output waveform gate-level of 4:1 mux
Fig 5.6 Output waveform data flow of 4:1 mux
Fig 5.7 Output waveform behavioral of 4:1 mux
RESULT:
The 4:1 multiplexer was designed and simulated in gate-level, data flow and behavioral
modeling abstractions using Xilinx ISE design suite.
EXPERIMENT-6
AIM:Design and simulation of 16:1 multiplexer using 4:1 multiplexer.
METHODOLOGY:
A multiplexer is an arithmetic combinational circuit which takes one of its inputs as an output
based upon the select lines. A 16:1 mux has 16 inputs and 4 select lines. To implement a 16:1
mux using 4:1 mux we need five of them.
This can be done in a two stage computation where in first stage we use four 4:1 mux, 16
inputs and two lower bit select lines which are same to all the four. In next stage the outputs from
these mux are given as inputs to the fifth mux and the remaining higher bit select lines are also
given.
TRUTH TABLE:
Table 6.1 Truth table of a 16:1 multiplexer
INPUTS (select lines) OUTPUT

s[3] s[2] s[1] s[0] Out
0 0 0 0 in0
0 0 0 1 in1
0 0 1 0 in2
0 0 1 1 in3
0 1 0 0 in4
0 1 0 1 in5
0 1 1 0 in6
0 1 1 1 in7
1 0 0 0 in8
1 0 0 1 in9
1 0 1 0 in10
1 0 1 1 in11
1 1 0 0 in12
1 1 0 1 in13
1 1 1 0 in14
1 1 1 1 in15
BOOLEAN EXPRESSIONS:
.0
out 1= 1 .in0 + 1
.s0.in1 + s1.0
.in2 + s1.s0.in3
.0
out2 = 1 .in4 + 1
.s0.in5 + s1.0
.in6 + s1.s0.in7
.0
out3 = 1 .in8 + 1
.s0.in9 + s1.0
.in10 + s1.s0.in11
.0
out4 = 1 .in12 + 1
.s0.in13 + s1.0
.in14 + s1.s0.in15
.2
out= 3 .out1 + 3
.s2.out2 + s3.2
.out3 + s3.s2.out4
CIRCUIT DIAGRAM:
Multiplexer
in[0] S1 D
in[1] S4
in[2] 4:1
in[3]
C1 C2 ENB
S[1] S[0]
Multiplexer
in[4] S1 D
in[5] S4
in[6] 4:1
Multiplexer
in[7] S1 D out
C1 C2 ENB
S4
4:1
S[1] S[0]
Multiplexer
C1 C2 ENB
in[8] S1 D
in[9] S4
in[10] 4:1 S[3] S[2]
in[11]
C1 C2 ENB
S[1] S[0]
Multiplexer
in[12] S1 D
in[13] S4
in[14] 4:1
in[15]
C1 C2 ENB
S[1] S[0]
Fig 6.1 Circuit diagram for a 16:1 mux using 4:1 mux
VERILOG CODE:
module mux_16_1(input [15:0] I, input [3:0] S, output out );
wire [3:0] w;
mux_4x1 m1(I[3:0],S[1:0],w[0]); //module instantiation
mux_4x1 m2(I[7:4],S[1:0],w[1]);
mux_4x1 m3(I[11:8],S[1:0],w[2]);
mux_4x1 m4(I[15:12],S[1:0],w[3]);
mux_4x1 m5(w[3:0],S[3:2],out);
endmodule
//4:1 mux module
module mux_4x1(input [3:0] i, input [1:0] s, output out);
assign out = s[1]?(s[0]?i[3]:i[2]):(s[0]?i[1]:i[0]);
endmodule
INPUT TEST BENCH:

initial begin
I = 16'b1010101010000101; // Initialize Inputs
S = 4'b0000;
S = 4'b0001; #50;
S = 4'b0010; #50;
S = 4'b0011; #50;
S = 4'b0100; #50;
S = 4'b0101; #50;
S = 4'b0110; #50;
S = 4'b0111; #50;
S = 4'b1000; #50;
S = 4'b1001; #50;
S = 4'b1010; #50;
S = 4'b1011; #50;
S = 4'b1100; #50;
S = 4'b1101; #50;
S = 4'b1110; #50;
S = 4'b1111; #50;
end
RTL SCHEMATIC VIEW:
Fig 6.2 Schematic of 16:1 mux using 4:1 mux
OUTPUT WAVEFORM
Fig 6.3 Output waveform of 16:1 mux using 4:1 mux
RESULT
The 16:1 multiplexer circuit was designed and simulated using 4:1 multiplexers with module
instantiation in Xilinx ISE design suite.
EXPERIMENT-7
AIM: Design and simulation of 3:8 decoder
METHODOLOGY:
A decoder is a combinational circuit which on an active enable makes one of the outputs active
based on the input code. Outputs of a decoder are one-hot i.e only one of the output is active at a
time. A 3 to 8 decoder has 3 inputs and 8 outputs. The truth table and boolean expression for a
3:8 decoder are given below.
TRUTH TABLE:
Table 7.1 Truth table of 3:8 decoder
INPUTS OUTPUT
Enable
in[2] in[1] in[0] out[7] out[6] out[5] out[4] out[3] out[2] out[1] out[0]
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
0 x x x Z z Z z z z Z z
out[0] = .[0]
[2].[1] .[0]
out[4]= [2].[1]
out[1] = . [0]
[2].[1] . [0]
out[5]= [2].[1]
out[2] =
[2].[1].
[0]
out[6]= [2].[1].[0]
.[1]. [0]
out[3] = [2] out[7]= [2]. [1]. [0]
CIRCUIT DIAGRAM :
Fig 7.1 Circuit diagram of3:8decoder
APPLICATIONS :
Decoders are used in memory architecture like ROM to decode a particular

memory location.
Also decoders are used for decoding the logical instruction to a processor.
VERILOG CODE :
module dec_3x8_GL(input [2:0] in, output [7:0] out, input enable);
wire w0,w1,w2;
not g1(w0,in[0]);
not g2(w1,in[1]);
not g3(w2,in[2]);
and g4(out[0],w2,w1,w0,enable);
and g5(out[1],w2,w1,in[0],enable);
and g6(out[2],w2,in[1],w0,enable);
and g7(out[3],w2,in[1],in[0],enable);
and g8(out[4],in[2],w1,w0,enable);
and g9(out[5],in[2],w1,in[0],enable);
and g10(out[6],in[2],in[1],w0,enable);
and g11(out[7],in[2],in[1],in[0],enable);
endmodule
module dec_3x8(input [2:0] i, output [7:0] out, input enable);
assign out[0]=enable?(~i[2]&~i[1]&~i[0]):1'bz;
assign out[1]=enable?(~i[2]&~i[1]&i[0]):1'bz;
assign out[2]=enable?(~i[2]&i[1]&~i[0]):1'bz;
assign out[3]=enable?(~i[2]&i[1]&i[0]):1'bz;
assign out[4]=enable?(i[2]&~i[1]&~i[0]):1'bz;
assign out[5]=enable?(i[2]&~i[1]&i[0]):1'bz;
assign out[6]=enable?(i[2]&i[1]&~i[0]):1'bz;
assign out[7]=enable?(i[2]&i[1]&i[0]):1'bz;
endmodule
module dec_3x8_behavioral(input [2:0] in, output reg [7:0] out, input enable);
always@(in,enable)
begin
case({in[2],in[1],in[0],enable})
4'bxxx0: out=8'bxxxxxxxx;
4'b0001: out=8'b00000001;
4'b0011: out=8'b00000010;
4'b0101: out=8'b00000100;
4'b0111: out=8'b00001000;
4'b1001: out=8'b00010000;
4'b1011: out=8'b00100000;
4'b1101: out=8'b01000000;
4'b1111: out=8'b10000000;
endcase
end
endmodule
INPUT TEST BENCH

initial begin
in = 3'b000; enable = 0; // Initialize Inputs
enable = 1;
in = 3'b000; #100;
in = 3'b001; #100;
in = 3'b010; #100;
in = 3'b011; #100;
in = 3'b100; #100;
in = 3'b101; #100;
in = 3'b110; #100;
in = 3'b111; #100;
end
initial begin
i = 3'b000; // Initialize Inputs
enable = 0;
enable = 1;
i = 3'b000; #100;
i = 3'b001; #100;
i = 3'b010; #100;
i = 3'b011; #100;
i = 3'b100; #100;
i = 3'b101; #100;
i = 3'b110; #100;
i = 3'b111; #100;
end
initial begin
in = 3'b000; // Initialize Inputs
enable = 0;
enable = 1;
in = 3'b000; #100;
in = 3'b001; #100;
in = 3'b010; #100;
in = 3'b011; #100;
in = 3'b100; #100;
in = 3'b101; #100;
in = 3'b110; #100;
in = 3'b111; #100;
end
Fig 7.2 Gate-level schematic of 3:8 decoder
Fig 7.3 Data flow schematic of 3:8 decoder

Fig 7.4 Behavioral schematic of 3:8 decoder
OUTPUT WAVEFORM
Fig 7.5 Output waveform of gate-level 3:8 decoder
Fig 7.6 Output waveform of data flow 3:8 decoder

Fig 7.7 Output waveform of behavioral 3:8 decoder
RESULT
The 3x8 decoder was designed and simulated in gate-level, data flow and behavioral modeling
abstractions using Xilinx ISE design suite.

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EXPERIMENT-1

AIM:Design and simulation of half-adder and full-adder using different modeling.

EDA TOOL USED: Xilinx ISE 14.7

Fig 1.1 Circuit diagram for an half adder

Table 1.2 Truth table of a full adder

Fig 1.2 Circuit diagram for a full adder

B. Data flow modeling

B. Data flow modeling

module FA(input a, input b, input c, output reg sum, output regcout);

INPUT TEST BENCH

B. Data flow modeling

RTL SCHEMATIC VIEW

Fig 1.3 Gate-level schematic of half adder

B. Data flow modeling

Fig 1.4 Data flow schematic of half adder

Fig 1.5 Behavioral modeling schematic of half adder

Fig 1.6 Gate-level schematic of full adder

Fig 1.7 Data flow schematic of full adder

Fig 1.8 Behavioral schematic of full adder

Fig1.9 Output waveform of gate-level half adder

Fig1.10 Output waveform of data flow half adder

Fig1.11 Output waveform of behavioral half adder

Fig1.12 Output waveform of gate-level full adder

B. Data flow modeling

Fig1.13 Output waveform of data flow full adder

Fig1.14 Output waveform of behavioral full adder

AIM: Design and simulation of half-subtractor and full-subtractor

EDA TOOL USED: Xilinx ISE 14.7

Table 2.1 Truth table of an half subtractor

Fig 2.1 Circuit diagram for an half subtractor

Table 2.2 Truth table of a full subtractor

A B b_in diff b_out

Fig 2.2 Circuit diagram for a full subtractor

B. Data flow modeling

B. Data flow modeling

modulefull_sub_behavioral(input a, input b, input c_in, output reg diff, output

INPUT TEST BENCH :

B. Data flow modeling

B. Data flow modeling

RTL SCHEMATIC VIEW :

Fig 2.3 Gate-level schematic of half subtractor

Fig 2.4 Data flow schematic of half subtractor

Fig 2.5 Behavioral schematic of half subtractor

Fig 2.6 Gate-level schematic of fullsubtractor

Fig 2.7 Data flow schematic of fullsubtractor

Fig 2.8 Behavioral schematic of fullsubtractor

Fig2.9 Output waveform of gate-level half subtractor

Fig 2.10 Output waveform of data flow half subtractor

Fig 2.11 Output waveform of behavioral half subtractor

Fig 2.12 Output waveform of gate-level full subtractor

Fig 2.13 Output waveform of data flow full subtractor

Fig 2.14 Output waveform of behavioral full subtractor

AIM: Design and simulation of 4-bit parallel adder

EDA TOOL USED: Xilinx ISE 14.7

s[i] = a[i] b[i] c[i] 0i3

c_out = a[3]b[3] + b[3]c[3] + a[3]c[3]

INPUT TEST BENCH :

RTL SCHEMATIC VIEW :

Fig 3.2 Schematic of parallel adder using full adder

Fig 3.3 Output wave form of the parallel adder

AIM :Design and simulation of full-adder using half-adder

EDA TOOL USED: Xilinx ISE 14.7

Table 4.1 Truth table of a full adder

sum of HA1 = a b sum of HA2 = a b c_in