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Course consists of
1. Three assignments: To be submitted on or before the given dates in the activity diary.
Late submissions will not be accepted and will be given zero marks.
2. Continuous Assessment Tests: CAT#1 ( up to lesson 8 of Book 1 and up to lesson 4 of Book 2.
Open Book Test)
CAT#2 (Book 1 and Book 2B. Open Book Test )
3. Lab Work: A pre report must be prepared before coming to the lab classes. See
Experimental Work Book for details. Minimum mark of 40% for lab
work is compulsory to obtain eligibility in addition to the marks
obtained from other activites.
4. Final Examination on all lessons including lab work. (Closed Book Test )
Answers to each assignment must be written clearly. They should be sent by post to the Course
Coordinator - ECX 3230 or should be placed in the relevant box provided in Block 12 of the
Colombo Regional Center on or before the due date.
Negative marks will be given for copying.
Direct reproduction of course material as answers will cause a reduction of marks.
Clear and brief answers with no unnecessary details will gain maximum marks.
ECX3230 Electronics
Assignment no. 01 (Due date: see the activity diary)
Answer all the questions
1)
a) Draw the characteristic curve of a Germanium diode.
b) A Germanium diode when forward biased at 250C carries a 3mA current at 0.2V. Assume
VT is 25mV at 250C.
i) Calculate the diode current when this diode is reversed biased by 10V.
ii) Find the diode current when the diode is forward biased and at a temperature of 500C.(
=1 for Ge)
c) A certain PN junction was designed to use as a voltage controlled capacitor which is shown
in Figure 1.1. Ohmic resistance and reverse resistance of the diode is negligible.
Choke
20mH
Capacitance Cj (pF)
+ L
(30mH) 6
+
P N
VC Vsinwt 4
R
_
(2.2KW)
2
2)
a) Draw the output characteristic curve of a silicon transistor with respect to common emitter
configuration. Mark the regions of the transistor.
i) Calculate the output voltage of the circuit shown in Figure 2, when a 6V input is applied
at the input? (Assume the transistor current gain () = 20 and VBE = 0.7V and voltage of
the LED is 1V.)
VCC(10V)
R1
720W R4
o/p 100W
i/p
R2
10KW
R3
220W
Figure 2
b) A unipolar transistor amplifier is shown in Figure 2.1. The drain current is 10mA at VGS = 0
and the pinch off voltage of the device is -3V. The circuit is to be designed so that the
quiescent point is at ID = 5mA and VDS = 5V.
+VDD(25V)
Rd
D
R G
V1 S
VGG
Figure 4.2
A
B
C
A
D
B
4)
a) Write the truth tables for two input NAND gate and NOR gate.
c) The input to a combinational logic circuit is a 4 bit binary number ABCD. Where A is the
most significant bit. The output of the circuit will be high when the input satisfies the
following conditions ;
A+C = 1
Or
BD =1.
i) Draw the truth table and the Karnaugh map for the output function.
ii) Minimize the logic function of the output using the Karnaugh map and implement it
using two input NAND gates.
ECX3230 Electronics
Assignment no. 02 (Due date: see the activity diary)
Answer all the questions
1) A common emitter transistor amplifier is shown in Figure 1. Transistor is silicon and its current
gain is 60.
+Vcc (10V)
RC
RB (680W)
(10KW)
o/p
i/p
Figure 1
a) Draw the D.C load line.
b) Find the base current at Q point.
c) Mark the Q point on the load line.
d) What is the maximum possible value of the undistorted output signal?
e) Derive an expression for the stability factor for the circuit given in Figure 1.
f) Calculate the stability factor.
2) A regulated dc power supply is shown in Figure 2. The transistor and diodes are made of silicon
semiconductor. A minimum current of 0.5 mA is required to operate the zener diode and its
worst case power dissipation in this circuit is 25mW.
P
L
240V
(150 mH)
r.m.s
Q X Y
12:1
C R1 Vou
RL
(10 mF) (470W) t
Vz
(5.6 V)
Figure 2
E C
(10V) (220mF)
Figure 3.1
R
(2.2KW)
L
E (33mH)
(10V)
Figure 3.2
4)
a) Clipping and clamping circuits are shown in Figure 4.1 and 4.2.
i) Explain the behaviour of the circuit with help of equations.
ii) Draw the output waveform with reference to the input waveform.
R1
(1kW) C
(0.1mF)
D1 R2
10V/AC (22kW) D2
(100kW)
5kHz
R
AC
5V E
(3V
R3
R1 3.3kW
8.2kW
C
R4
680W
Figure 4.3
R3
R1(10kW) (2.7kW)
C2(10mF) C3(10mF)
i/p o/p
R1(5kW)
R2(1kW) C1(10mF)
Figure 1
AC
Figure 2
i) Derive the voltage gain of this circuit.
ii) If the input voltage is 4sin1000t, find the output voltage.
iii) Sketch the output signal with reference to the input signal.
iv) State the function of this circuit.
3) Figure 3 shows a circuit containing four flip flops and two exclusive-or gates. The circuit has
two independent clock pulse signals, C and D, which have 20 kHz and 100 khz frequencies
respectively. The input signal, U, consists of pulse which operates at twice of the signal of C
and whose transitions occur slightly after the rising edge of C.
Complete the timing diagram, showing the waveforms of V, W, X, Y and Z.
Assume all signals are initially low.
W Z
D D D D
X
U V Y
C C1 C1 C1 C1
D
Figure 3
4) A multivibrator circuit is shown in Figure 4.
a) What is the type of this multivibrator?
b) Explain the operation in the multivibrator shown in figure 4.
c) Draw the waveforms at points A,B,D, E in a common time scale. Assume that at time t =0,
Tr1 is switched on.
VCC
R1 R2 R4
C1 R3
A B
Out put
D E
Q1 Q2
R5
C2
0V
Input +VBE
-V Figure 4
T