EECE-315 (VLSI I)

Introduction
Major Md Tawfiq Amin, PhD
Department of Electrical, Electronic, and Communication Engineering

Military Institute of Science and Technology (MIST)

 References:
TEXT Book:
Design of VLSI system A practical introduction by Linda E. M.
Brackenbury, MacMillan Education Ltd.
Basic VLSI Design (3rd Edition) by Douglas A. Pucknell and
Kamran Eshragian, Prentice Hall
CMOS VLSI design (3rd edition) by Weste, Harris & Banerjee
CMOS Circuit Design, Layout and Simulation( 2nd Edition) by R.
Jacob Baker, Wiley-IEEE

Reference Book:
Fundamentals of Digital Logic with Verilog Design Stephen
Brown and Zvonko Vranesic, Tata McGraw-Hill Publishing
Company Ltd, Tata-McGraw-Hill Edition 2002.
MIST- Major Md Tawfiq Amin, PhD 2
 Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication

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 Why VLSI

Money, technology, civilization

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

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 A Brief History

Vacuum tubes ruled in first half of 20th century Large,

expensive, power-hungry, unreliable
1947: first point contact transistor (3 terminal devices)
Shockley, Bardeen and Brattain at Bell Labs

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 A Brief History

1958: First integrated circuit

Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas
Instruments
Robert Noyce (Fairchild) is also considered as a
co-inventor

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 A Brief History
First Planer IC built in 1961

2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller, cheaper, faster, lower in power!
Revolutionary effects on society

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 A Brief History
2010
Intel Core i7 mprocessor
2.3 billion transistors
64 GB Flash memory
> 16 billion transistors

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 MOS Integrated Circuits

1970s processes usually had only nMOS transistors

Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

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Annual Sales

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 Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

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At Present.

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Feature Size

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 Other Factors
Many other factors grow exponentially
Ex: clock frequency, processor performance

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 Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large
currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
First patent in the 20s in USA and Germany
Not widely used until the 60s or 70s

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 nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal
Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si

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 nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

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 nMOS Operation
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

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pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

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 Power Supply
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny
transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

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Transistor as Switch
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

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 CMOS Inverter

A Y
VDD
0
1
A Y

A Y
GND
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 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
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CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
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CMOS NAND Gate

A B Y
0 0
0 1 Y
1 0 A
1 1
B

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CMOS NAND Gate

A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

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CMOS NAND Gate

A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

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CMOS NAND Gate

A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

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CMOS NAND Gate

A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

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 Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of = f/2
E.g. = 0.3 mm in 0.6 mm process

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IC Design Flow

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Schematic

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Simulation

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Layout

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 Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields

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Fabrication & Packaging

Tape out final layout

Fabrication
(6-12) wafers
Optimized for throughput,
not latency (10 weeks!)
Cut into individual dice
Packaging
Bond gold wires from die I/O pads to package
580 m

285 m
LF Ltank

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 Testing
Test that chip operates
Design errors
Manufacturing errors
A single dust particle or wafer defect kills a
die
Yields from 90% to < 10%
Depends on die size, maturity of process
Test each part before shipping to customer

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PCB For Test

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Test Environment

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Thanks

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