IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO.

1, MARCH 2012 93

Modes of Operation and System-Level Control

of Single-Phase Bidirectional PWM Converter for
Microgrid Systems
Dong Dong, Student Member, IEEE, Timothy Thacker, Member, IEEE, Igor Cvetkovic, Student Member, IEEE,
Rolando Burgos, Member, IEEE, Dushan Boroyevich, Fellow, IEEE, Fred Wang, Fellow, IEEE, and
Glenn Skutt, Member, IEEE

AbstractRobust system control design and seamless transition

between various modes of operation are paramount for multifunc-
tional converters in microgrid systems. This paper proposes a con-
trol system for single-phase bidirectional PWM converters
for residential power level microgrid systems which is robust and
can tolerate transitions between the different modes of operation.
This is achieved by means of a common inner ac current-loop. Each
of the operating modes has an individually designed outer loop per-
forming the corresponding regulation tasks, most commonly in-
cluding the ac voltage and the dc voltage regulation. A modified
, phase-locked loop (PLL) system is used for system-level oper-
ation with both small steady-state error and fast response; and a Fig. 1. Single-phase AC/DC interactive renewable energy system.
novel islanding detection algorithm based on PLL stability is pro-
posed to facilitate the transition between grid-connected mode and TABLE I
stand-alone mode. Finally, a frequency-response based design pro- SYSTEM PARAMETERS.
cedure for the proposed control system is presented in detail for all
operating modes, and its performance is verified experimentally
using a DSP-controlled 6 kW 120 V rms (ac)/ 300 V (dc) labora-
tory converter prototype.
Index TermsIslanding detection, microgrid system, multi-
function converter, PLL, single-phase.

I. INTRODUCTION

I N RECENT years, due to the growing concern with en-

ergy shortage and network stability, the concepts of dis-
tributed generation (DG), microgrid systems [1], [2], dc nano-
grid systems [3], [4], and ac/dc hybrid power systems [5][7]
utility grid under normal operating conditions, but also have
have all become progressively more popular; especially with
the additional capability to sustain a local system (micro- or
the decreasing costs of various clean renewable energy sources
nanogrid) by sourcing power directly from the renewable en-
(RES), such as: wind, solar, and fuel-cells to name a few and
ergy sources and energy storage devices if necessary to make
more adoption of dc powered residential loads, such as solid-
grid transmission level black- and brownouts seem transparent
state lighting. These DG systems would be connected to the
to the local system loads.
Distributed hybrid power systems (DHPS) consist of ac and
Manuscript received March 18, 2011; revised June 28, 2011; accepted August
dc subsystems connected to various load types, where DG re-
21, 2011. Date of publication January 23, 2012; date of current version February
23, 2012. Paper no. TSG-00014-2011. sources can be connected on the ac or dc systems [6]. The crit-
D. Dong, I. Cvetkovic and D. Boroyevich are with the Center for Power Elec- ical component for such a system is the ac/dc bidirectional,
tronics Systems, Virginia Tech, Blacksburg, VA 24061 USA (e-mail: dongd@vt.
pulsewidth-modulation (PWM) converter that connects the ac
edu; igorc@vt.edu; dushan@vt.edu).
T. Thacker and G. Skutt are with PowerHub System, Blacksburg, VA 24060, and dc subsystems together and to the utility grid. The diagram
USA (e-mail: tthacker@vpt-es.com; gskutt@vpt-es.com). in Fig. 1 illustrates an example of a , DHPS with renewable
R. Burgos is with the ABB U.S. Corporate Research Center, Raleigh, NC
energy sources throughout the system, and the system param-
27606 USA (e-mail: rburgos@ieee.org).
F. Wang is with the University of Tennessee, Knoxville, TN 37996 USA eters are shown in Table I. Other devices for realizing such a
and also with the Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA system, such as the supervisory control, communication, and
(e-mail: f.wang@ieee.org).
protection components, can be found in [7].
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Using this type of system configuration, the ac/dc converter of
Digital Object Identifier 10.1109/TSG.2011.2167352 a DHPS should operate in the following modes and submodes:

1949-3053/$31.00 2012 IEEE

94 IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012

1) Stand-Alone Mode (SAM): When the grid is lost, the

converter regulates the ac bus voltage and frequency
feeding the ac loads while drawing energy from dc-side,
supported by the renewable energy sources or energy
storage on the dc-side. The RES on the ac side act as
current sources in this case. Fig. 2. Multifunctional single-phase bidirectional converter.
2) Grid-Connected Mode (GCM): When the grid is present,
the converter acts as an ac current regulator, injecting or
sinking power from the grid to achieve: simple, as well as reliable, to implement and seamless transfers
a) Inverter submode: Regulate the power flow (active between the modes of operation is easy to achieve.
and reactive) between the dc and ac subsystems, while
other dc sources regulate the dc bus voltage , II. SYSTEM MODES OF OPERATION: MODELING AND
b) Rectifier submode: Regulate the dc bus voltage and CONTROL STRUCTURE
performs energy balancing to sustain dc bus integrity Before the control structure is designed and implemented, the
while other dc side energy sources operate as current converter system needs to be modeled. Specifically, the full-
sources. bridge, multifunctional PWM converter with different possible
3) Grid-Disconnected Mode (GDM): When the grid is lost, ac or dc configurations is shown in Fig. 2, where is the cur-
the converter still operates as GCM inverter/power flow rent flowing from the dc DG resources, and its average model
control supplying ac loads. Normally, GDM is the transient of full-bridge is described in (1) and (2).
state in mode transition between GCM and SAM; however,
given the nondetection zones (NDZ) [8], GDM could exist (1)
for a while. (2)
Islanding refers to the condition of the single-phase converter
operating at SAM or GDM continuing to power a local ac load As seen in (1) and (2), , and are the average ter-
even though power from the electric utility is no longer present. minal voltage of the full bridge, average dc-link current, and av-
For GDM, it is the unintentional islanding condition, which is erage duty-cycle varying between and 1, respectively. No-
specified by IEEE 1547 standard [9] for the clearing times. But tice that if is constant, the terminal voltage is only a
SAM, an intentional islanding condition, is still under discus- function of the duty-cycle . The differential equations de-
sion in IEEE 1547. scribing the average model of the full-bridge converter may then
Many control strategies have been proposed recently, such be derived as follows:
as hysteretic and predictive control for GCM (acting as an
inverter) [10], [11], fuzzy-logic/neural-network, sliding mode, (3)
and repetitive control for SAM [11][13], and predictive control
for GCM (acting as a rectifier) [14]. Some work has covered the (4)
capability and control behind the seamless transitions between
different modes [11][13]. (5)
Many of the existing methods require a different control
system for each mode of operation, which increases the com- The average and small-signal models for the different modes
plexity and decreases the reliability of the system, as well can be derived by combining (1)(5). Notice that in GCM, the
as increasing the difficulty in transitioning between modes. dynamics of the ac capacitor can be ignored due to the stiff
Moreover, existing papers did not cover all of the probable grid, just as the dynamics of the dc-link capacitor can be
modes of operation, neither the overall functionality nor the ignored because of the constant dc-link voltage during SAM.
modeling and control design of all the aforementioned modes. With the control architecture selected to be a double-loop
As it will be shown, some of them are very different requiring feedback system, as shown in Fig. 3, the inner loop is used to
different control approaches. regulate the ac line inductor current. In order to achieve fast dy-
In terms of system level control reliability, compared to namic responses from a wide array of disturbances, the inner
the above, multiloop current-voltage PID controls based on loop will need to be designed with high bandwidth, while the
frequency-response analysis provides several advantages in outer loops regulate different control variables depending on the
terms of design and implementation simplicity, achieving good operating mode.
regulation, excellent performance, but most importantly, a Inclusion of all control features, such as digital delays and
well-defined region of predictable stability for the converter sensor filters should also be included. Each sensor filter is as-
operation. sumed to be a second-order, low-pass-filter, (6). A one
In this paper, all of the basic modes of operation for GCM switching-cycle delay, (7), is modeled in the
and SAM are defined and modeled. A generic inner current loop modulator to approximate the digital computation and A/D con-
based multiloop control structure is proposed to integrate and version delay. The modulator gain is assumed to be unity.
simplify the various modes of operation. A novel single-phase
PLL and associated islanding detection algorithm is proposed (6)
for system level operation. The proposed control system is very
DONG et al.: MODES OF OPERATION AND SYSTEM-LEVEL CONTROL OF SINGLE-PHASE BIDIRECTIONAL PWM CONVERTER 95

Fig. 3. Control structures under different modes of operation.

(7)

III. GENERIC INNER AC CURRENT LOOP DESIGN

It is worthwhile to demonstrate that the same current loop
compensator can be designed and shared by all modes. Specifi-
cally, for GCM inverter mode the small-signal transfer function
from control-to-current can be simply obtained from the average
model given by (1)(3) and applying a small-signal perturba-
tion, of which the result is as follows:
Fig. 4. Bode plot of control-to-current transfer function in stand-alone inverter
mode under different load levels.
(8)

Notice that (8) is obtained by assuming the small-signal grid With the transfer functions described in (8)(10), the cur-
voltage is zero due to the stiff grid condition. For the SAM, the rent compensator can be designed; but the varying nature of
transfer function from control-to-current is obtained from the the resultant transfer functions must be considered given that
average model described by (1)(4): it changes under varying line and load conditions, actual op-
erating mode, and even the converter operating point itself. A
(9) comprehensive linear design can still be carried out however,
if the control-to-current transfer function is closely examined
under these different conditions.
Although SAM does not have a constant operating point for
Specifically, the Bode plots in Figs. 46 show that for SAM
the output, the small-signal model is linear time-invariant
and GCM, the different load conditions only change the low-fre-
when dc-link voltage is constant. For the GCM rectifier mode
quency response of the converter, that is, below the resonance
however, since there is no fixed operating point and no constant
point created by and . This is
dc-link voltage, the dynamics of both sides of the bridge have
observed in the SAM control-to-current Bode plots in Fig. 4, in
to be considered. The result is that there is not a complete ac-
the rectifier Bode plots in Fig. 5 under different loads, and in the
curate small-signal model that can describe the entire dynamics
rectifier control-to-current Bode plots in Fig. 6 under different
from dc up through the Nyquist frequency [15]. However,
operating points . In the latter plots, it can be seen how the
if the current loop is modeled in a higher frequency range
low-frequency response and resonant frequency shift in recti-
and the voltage loop in a lower frequency range separately,
fier mode. It should also be noticed that when compared with
following the quasi-static modeling approach proposed in [15],
SAM, the resonant frequency of the GCM rectifier mode is al-
the high-frequency small-signal current loop can be modeled
ways lower than that of the SAM. This is due to the much larger
since the all the operating points (60 Hz) and varying dc-link
dc-link capacitor compared to that of the ac line/load ca-
voltage (120 Hz) can be assumed to be in steady state because
pacitor in SAM.
of the high current loop control bandwidth. Hence, (3) and
From Figs. 46, it can be seen that for all the different op-
(5) can be perturbed as usual for all operating points, and the
erating modes and conditions, SAM at light load condition is
control-to-current transfer function is then derived as below.
the worst case of current loop (the lowest phase-margin and the
The detailed derivation can be found in [17].
highest resonant frequency). Consequently, if the current loop
controller is designed to achieve a very high bandwidth higher
(10)
than the resonant frequency under the worst case, the current
96
Fig. 5. Bode plot of control-to-current transfer function for three operating
modes with different load levels for the rectifier mode.
Fig. 6. Bode plot of control-to-current transfer function for three modes with
different duty cycles in rectifier mode.
regulator can cover all possible modes of operation with the de-
sired control bandwidth and phase margin in the mid to high
frequency range (up to the Nyquist frequency).
The current loop compensator is designed under SAM light
load conditions based on (9). The current PID compensator has
the following structure in (11) to compensate the current loop
gain in (12).
(11)
(12)
The zeros in (11) are placed around the resonant frequency
to compensate the drop in phase, and two poles are used to at-
tenuate the high frequency resonance from grid impedance. The
gain, , is used to achieve the desired loop-gain and bandwidth
for the inner current loop.
Finally, the compensated open-loop-gain of the current-loop
is shown in Fig. 7 for the three different operating modes
under light load condition. The designed current loop bandwidth
is around 2 kHz. As seen, by using a generic current controller
one control system can be used for different modes of operation,
as shown in Fig. 8. Per (8)(10), a feed-forward loop is also
applied to measure the dc-link voltage (Fig. 8) and decouple the
dc gain from . [17] for detailed derivation. If a resistive load is connected, the
IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012
Fig. 7. Compensated inner current loop in all modes.
Fig. 8. Multi-functional converter control system.
IV. OUTER LOOP CONTROLLER DESIGN
A. Stand-Alone Inverter Mode
The outer loop in this case is an ac voltage loop; as such,
the ac-current to ac-voltage transfer function is given by (13)
assuming a resistive load.
(13)
The open-loop gain to design the outer voltage compensator
is shown in (14), where and are the closed-loop current
transfer-function, and ac-current to ac-voltage transfer function,
respectively.
(14)
B. Rectifier Mode
Dc-link voltage loop controller is designed under the assump-
tion of the previously designed high-bandwidth current loop.
Since the dc-link voltage loop bandwidth must be much lower
than the frequency of the dc-link voltage ripple (120 Hz). Thus,
taking the rms value of as the steady-state operating point,
the power balance between the ac and dc side of the converter
is used to model the voltage loop, which can be found in [16],
DONG et al.: MODES OF OPERATION AND SYSTEM-LEVEL CONTROL OF SINGLE-PHASE BIDIRECTIONAL PWM CONVERTER 97

Fig. 9. No load to full load at stand-alone inverter mode. Ac current

, ac voltage . Fig. 10. No load to full load at rectifier mode. Ac current and dc load
current , ac voltage , dc-link voltage
.
outer loop transfer function becomes (15), where is the scaling
factor of the PLL.

(15)

The outer loop compensators of stand-alone mode and recti-

fier mode are shown in (16) and (17), respectively.

(16)

(17)

The design criteria of (16) is similar as the current loop de-

sign, In (17), zeros is placed specifically to cancel the pole in
(15), while another pole is placed after the crossover frequency
to attenuate the loop gain at 120 Hz.
An experimental evaluation was conducted using a 6 kW,
single-phase, PWM converter controlled with a DSP-FPGA dig- Fig. 11. Mode transition from charging mode to inverter mode. Ac current
and dc battery current , AC voltage and dc-link voltage
ital control system. Figs. 912 show the results obtained for the .
various modes and submodes of operation. A 300 V NiMH bat-
tery pack was connected to the dc-side as a dc DG source to
verify the GCM inverter mode. The waveform variables in these
figures can be found in Fig. 2.
Fig. 9 shows the transient response from the no load to the 6
kW load conditions under SAM. As seen, the output voltage is
regulated well at 120 V rms and the transient response is fast and
without oscillations. Fig. 10 shows the load transient between
no-load and 4.5 kW load under GCM rectifier mode. The load
step was applied using a solid-state switch on the dc side to
connect and disconnect a resistive load. As observed, the dc-link
voltage was regulated at 300 V without significant transients
under different loads while also handling large load transitions.
A small dc-error is observed at 4.5 kW load due to the voltage
drop on the dc cables between load and dc-link capacitor.
Figs. 11 and 12 show the transitions when the ac power
reverses the direction at GCM inverter mode and from unity
power factor GCM inverter mode to 90 power factor GCM
Fig. 12. Mode transition from leading power factor inverter mode to
inverter mode, respectively. These results show how the reac-
unity power factor inverter mode. Ac current and dc battery current
tive power compensation can be easily achieved by this type of , AC voltage and DC-link voltage .
98
Fig. 13. Procedures for transition between different modes.
controller. The dc current flowing from the dc battery pack
is also shown in Figs. 11 and 12.
The state-machine and procedures for mode transitions are
shown in Fig. 13. Between any two modes of operation the
system should always first be routed to the GCM inverter mode
to minimize transients. Because the ac current loop is always ac-
tive, when a mode change is requested, the control freezes the
last ac current reference from the present mode, and uses that as
the new initial reference point during the transition for the new
mode of operation. Functionally, the mode transition event will
look like a step response to the inner loop. However, the modes
transition between GCM and SAM is hard to achieve since both
islanding detection and resynchronization at the local converter
should be embedded in its control system to detect the loss of
grid and also to reconnect to the grid.
V. SYSTEM LEVEL OPERATION: SINGLE-PHASE PLL SYSTEM
To meet the standard IEEE 1547 for modes transition be-
tween GCM and SAM and the grid fault detection, fast and
accurate estimation of the phase angles of grid system is para-
mount, hence requiring as near an ideal PLL as possible. The
digitally implemented PLL consists of a phase-detector (PD),
loop-filter (LF) and digitally controlled oscillator (DCO) [18],
[19]. Typical mixer-type PLL systems, as shown in Fig. 14,
employ sinusoidal multiplier phase detectors (PD) that generate
an error voltage, , and a loop filter (LF), which in turn gen-
erates . These are commonly known as mixer systems [20].
Implementing this standard PLL, the PD output, , in (18) ex-
plicitly shows the steady-state oscillation error as tracks
.
(18)
As the PLL drives its output angle to track the input angle
of the grid voltage, the second-term in the right-hand side
in (18) goes to zero. However, the first term remains, creating
a steady-state, sinusoidal error oscillating at (assuming
IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012
Fig. 14. Conventional single-phase PLL.
Fig. 15. Proposed quasi-synchronous frame PLL.
). The size of this ripple depends on two quantities,
the LF bandwidth, and the input signal magnitude mismatch
(which corresponds to the per unit value of the
systems ac voltage). Past methods to minimize this ripple
effect have focused on adding low bandwidth low-pass filters
(LPFs), before and/or after the LF that attenuates the term
[21], [23]. These solutions generally cause the PLL loop band-
width, and/or phase-margin, to decrease leading to increased
transient responses and settling times to input disturbances and
slower overall synchronization speeds, which is an essential
downfall for mode transition between GCM and SAM.
Different methods have consequently been proposed to ad-
dress this without affecting the PLL dynamics. In [24][26],
an additional trigonometric term was added to the PD feedback
loop to cancel the ripple in question, but did not fully address the
voltage mismatch issue within the context of that work. A syn-
chronous frame based PLL was proposed in [24][27],
achieving zero steady-state error and the capability to detect
. For single-phase case, however, the frame based PLL
requires the accurate generation of -axis orthogonal compo-
nent for transformation [30].
Drawbacks exist in many orthogonal signal generation
methods presented in [24][29] due to the phase delay, noise
amplification, sensitivity to the dc offset, and complicated
design and implementation effort. To resolve this, forcing the
-axis component of the controller to zero, a novel quasi-syn-
chronous frame, PLL for single-phase systems is proposed
by authors in [30]. As shown in Fig. 15, in this implementation
only the -axis information is required, and is defined as
zero to simplify the implementation.
The PD output signal of the proposed PLL is shown in (19)
(19)
DONG et al.: MODES OF OPERATION AND SYSTEM-LEVEL CONTROL OF SINGLE-PHASE BIDIRECTIONAL PWM CONVERTER 99

The original mixer-type PLL and the proposed frame

PLL is also shown in Figs. 17 and 18. Fig. 17 shows the response
to a 2 Hz step; while Fig. 18 shows the response to a 90 phase
step. It can be shown that, by implementing the proposed PLL,
Fig. 16. Peak voltage detection block. the steady-state error can be reduced significantly, while still
keeping the same transient dynamics of the original system.

VI. SYSTEM LEVEL OPERATION: MODES TRANSITION,

ISLANDING DETECTION AND RESYNCHRONIZATION
Under the normal operating conditions, PLL is already in
steady-state and the peak voltage has been tracked; therefore,
this leads to an equivalent PLL as shown below in Fig. 19. En-
closed with the proposed PLL, the complete control system is
then finalized based on the control structure presented in Fig. 8.
In order to observe the PLL performance for islanding detec-
tion, both power cable and grid impedance ( , )
are considered. A relay at the point of common coupling (PCC)
is presented for manually turning on/off the grid to mimic its
Fig. 17. Experimental evaluation of PLL operating at 60 Hz grid voltage: 2
Hz step transient response of stationary frame PLL and proposed quasi-syn-
loss or fault condition.
chronous frame PLL from D/A converter. A well designed islanding detection algorithm is required to
detect islanding conditions within specified clearing times indi-
cated in [9], and also for mode transitions from GCM to SAM.
Re-synchronization method(s) also need to be implemented for
the grid to reconnect and reenergize the local system when it is
back within nominal operating ranges.
Most islanding detection algorithms developed over the last
decade can be classified into two categories. The first are passive
detection schemes [31][33], which passively search for distur-
bances upon the grid through sensed and calculated system pa-
rameters. The main drawback is the NDZ issue [8]. The second
ones are active detection schemes [34][37], which are incorpo-
rated into the system level control loops of a converter system.
Active schemes can drive the system voltage and/or frequency
away from the normal value and out of NDZs; however, these
Fig. 18. Experimental evaluation of PLL operating at 60 Hz grid voltage: 90 schemes degrade the converter power quality and their contin-
degree step transient response of stationary frame PLL and proposed quasi-syn- uous perturbation may cause the system-wide instability.
chronous frame PLL from D/A converter. The single-phase islanding detection technique is proposed
based upon the aforementioned PLL system to actively detect
the presence of the grid. The PLL LF can be designed marginally
A simple PI regulator can then be used in LF to eliminate the stable to incorporate a quasi-active islanding detection scheme
dc error, which in turn will force the component to zero that causes the estimated frequency to oscillate in an un-damped
when approaches unity and tracks the input grid angle, manner during the initial transients of an islanding event. The
all while achieving the zero steady-state error. detailed demonstration can be found in [38], while the key ex-
The peak voltage detection block is shown in Fig. 16 by using pressions are shown below. The output of the PLL PD is shown
the same transformation method. The output , of in (22), where is the measurement of local ac voltage.
the parks transformation are shown in (20) containing dc com-
ponents , , and the oscillation components , .
A low-pass filter (LPF) can be used to attenuate this second har- (22)
monic term in (20) to provide the grid peak voltage as shown in
(21).
Through KVL and KCL, the following (23)(26) can be iden-
tified. The current magnitude reference and load power
factor are supplied from higher level controller(s), or are static
for constant current control, and for this study are assumed to
(20) be such as to supply the entire load demand of ; therefore
the grid current, , is ideally zero. The term in (25) and (26)
(21) represents the Laplace transformation. If the grid is connected
100 IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012

Fig. 19. Control system included with PLL. Fig. 22. Simulation result of PLL output frequency for islanding detection with
.

Fig. 23. Grid-side system setup.

(GCM), and are shown in (27) and (28); while if the grid
is disconnected (GDM) they would be (29)

(23)
(24)
(25)
(26)

Fig. 20. with for grid-tied mode and grid-discon-

nected mode.

(27)

(28)

(29)

The small-signal model linearization about of (25)(26)

gives (30)(31)

(30)
(31)

Linearizing of (22) for its extraction from the trigonometric

Fig. 21. Simulation result of PLL output frequency for islanding detection with
. functions in , in order to design LF. To find , is
DONG et al.: MODES OF OPERATION AND SYSTEM-LEVEL CONTROL OF SINGLE-PHASE BIDIRECTIONAL PWM CONVERTER
Fig. 24. Resynchronization routine.
simply converted to via (32), which yields the result in (33)
by combining (22)(29)
(32)
(33)
is the phase mismatch between the PLL output and the real
phase of grid. Under steady-state case, is close to zero. As
such, the bode plots of (33) GCM and GDM are shown below
in Fig. 20 for resistive and parallel RLC load cases (RLC load
is tuned to 60 Hz resonance) in Table I.
The can be regarded as unity, since the interested
frequency range in Fig. 20 should be from dc up to the PLL
bandwidth, which is much lower than the current-loop band-
width. As such, one resonant pole/zero combinations in (34)
and (35) are found from (33) in GCM under resistive load con-
dition. The shift of this pole and generation of low- (at 60 Hz)
and higher-frequency pole are observed under parallel RLC load
case due to the resonance of load itself and the interaction be-
tween load and line impedances.
(34)
(35)
In (35), this is a floating zero dependent on . It is noticed that
as the PLL synchronizes, this zero moves to the origin, while
when the PLL approaches 90 of phase mismatch, the zero
approaches and cancel out the resonant pole in (35). The
bode-plot of GDM in Fig. 20 is somewhat similar as the GCM
when approaches . Figs. 26 and 27 show that the PLL takes about four to five
For the GDM in Fig. 20, it is also seen that the (33) reverts to
what is essentially a negative integrator resulting in additional
phase drop (with resonances at higher frequencies due to (34)
and (35)). This trait is used to produce a simple, yet effective,
islanding detection scheme covered in the following sections.
As seen, the PLL during GCM could be designed stable for
a simple PI for the LF; however, for any GDM case as seen in
Fig. 20, the maximum phase margin that can be achieved is neg-
ative 90 for PI LF types. Therefore, with the open-loop system
always unstable in the GDM, the frequency will oscillate and
101
drift away from the nominal value. Through this mechanism,
a standard over/under frequency protection (OFP/UFP) scheme
can then be used to help detect islanding events.
The time-domain simulation in Figs. 21 and 22 give a clear
understanding of how the islanding detection based on PLL sta-
bility works. The PLL by using the PI parameters shown in (36)
is stable and tracks the grid under steady-state conditions be-
fore the PCC relay opens, representing a grid-disconnected grid
fault as the islanding event. From this it is seen how the fre-
quency goes unstable for such an islanding condition.
(36)
The frequency responses to entering the GDM are seen in
Fig. 21 (detection within 0.0595s, line-cycles) for
and Fig. 22 (detection within 0.0759s, line-cycles) for
, . From simulation, the drift rate for
frequency oscillations varies with .
The resynchronization method as energized reclosure one can
be achieved by using the same PLL within the control system.
The system setup is shown in Fig. 23. The voltages on both sides
of the PCC relay are measured for resynchronization.
The control system first employs the PLL peak voltage de-
tection block to tune the magnitude of voltage reference to ap-
proach to grid voltage peak value. Then, it tunes the frequency
and phase to compare with the grid. As long as the phase error
drops into an acceptable range for approximately several line
cycles through implementing the routine as shown in Fig. 24,
the PCC relay then closes and the control system changes into
a GCM to complete the transition from SAM to GCM.
The and as the ac load are
used in the experimental cases for mode transition from GCM to
SAM. The result seen in Fig. 25 depicts the moment the system
enters GDM and the PLLs frequency starts to oscillate in re-
sponse to such a transition.
line cycles to detect the loss of grid and switches the controller
from GCM mode to SAM mode, performing both voltage and
frequency regulation under two ac loading conditions. At the
moment of transition into the SAM, it is seen that there is a slight
voltage distortion and current spike. Despite this, the transition
is still relatively smooth.
Fig. 28 shows that the SAM voltage tracks and synchronizes
with the grid voltage. Once synchronization is met, the voltage
holds and continues to track the grid voltage, waiting for reclo-
sure process to occur.
102
Fig. 25. PLL output at the islanding condition,
Ac current , ac voltage , PLL output signal
, Relay signal PCC relay.
Fig. 26. Hardware detection response when
Ac current , ac voltage , Islanding detection
signal Isl. Det., Relay signal PCC relay.
VII. CONCLUSION
This paper proposed a complete modeling and control
system for a bidirectional, single-phase, multifunctional PWM
converter for residential power level distributed renewable
energy and grid connected microgrid system applications. A
simple control structure was used to cover all of the required
operating modes, including stand-alone (SAM), grid-connected
(GCM) inverter, and rectifier mode. A new single-phase PLL
and active islanding detection algorithm was also proposed for
system-level operation in order to meet IEEE standard 1547.
The resulting control structure is very simple and presents
robust, low transient responses even for extreme load steps
between no-load and heavy-load conditions. The transition
between modes was also seamlessly achieved, as predicted,
due to the common inner current-loop that all operating modes
have. The proposed control system was exhaustively tested and
verified experimentally using a 6 kW laboratory prototype.
IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012
.
Fig. 27. Hardware detection response when . Ac current
, ac voltage , Islanding detection signal Isl.
Det., Relay signal PCC relay.
Fig. 28. Resynchronization for mode transition stand-alone mode to grid-tied
. mode. Ac current , grid voltage , ac regulation
voltage , Reclosure signal Rec.
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Dong Dong (S09) received his B.S. degree from
Tsinghua University, Beijing, China, in 2007, and
the M.S. degree from Virginia Polytechnic Institute
and State University (Virginia Tech), Blacksburg, in
2009, both in electrical engineering. Currently, he is
working toward the Ph.D. degree in the Center for
Power Electronics Systems (CPES) at Virginia Tech.
His research interests include modeling and real-
time control of multiphase power converters, utility-
interactive power converter design, passive filter de-
sign, and system integration for the renewable energy
systems, dc power distribution systems applications.
Timothy Thacker (S00M09) received the B.S.
degree in electrical engineering and the M.S. and
Ph.D. degrees from Virginia Polytechnic Institute
and State University (Virginia Tech), Blacksburg, in
2003, 2005 and 2009, respectively.
In 2009, he joined PowerHub Systems, Blacks-
burg, where he is currently the Senior Engineer of
Research and Product Development. His research
interests include single and multiphase converter
modeling and control, grid-interfaced converters,
distributed and renewable energy systems, islanding
detection algorithms, and smart grid technologies.
Igor Cvetkovic (S10) received the Dipl. Ing. degree
in power systems from the University of Belgrade,
Serbia, in 2004 and the M.S. degree from the Center
for Power Electronics Systems (CPES), Virginia
Polytechnic Institute and State University (Virginia
Tech), Blacksburg, in 2010. He is currently working
toward the Ph.D. degree at Virginia Tech.
His research interests include dc-electronic power
distribution systems stability and design, as well as
power electronics systems modeling and control.
104
Rolando Burgos (S96M03) received the B.S. de-
gree in electronics engineering, the Electronics Engi-
neering Professional Degree, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Concepcin, Chile, in 1995, 1997, 1999, and 2002
respectively.
In 2002 he joined as Postdoctoral Fellow the
Center for Power Electronics Systems (CPES) at
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, becoming Research
Scientist in 2003, and Research Assistant Professor
in 2005. In 2009 he joined, as Scientist, ABB Corporate Research, Raleigh,
NC, where since 2010 he has been Principal Scientist. In 2010 he was also
appointed Adjunct Associate Professor in the Electrical and Computer Engi-
neering Department at North Carolina State University (NCSU), Raleigh. His
research interests include multiphase multilevel power conversion, stability of
ac and dc power electronics systems, hierarchical modeling, control theory and
applications, and the synthesis of power electronics conversion systems.
Dr. Burgos is Member of the IEEE Power Electronics Society, where he cur-
rently serves as Secretary of the Committee on Simulation, Modeling and Con-
trol, and as Associate Editor for the IEEE POWER ELECTRONICS LETTERS, and
the IEEE TRANSACTIONS ON POWER ELECTRONICS.
Dushan Boroyevich (S81M86SM03F06)
received the Dipl. Ing. degree from the University of
Belgrade, Yugoslavia, in 1976 and the M.S. degree
from the University of Novi Sad, Yugoslavia, in
1982, and the Ph.D. degree from Virginia Poly-
technic Institute and State University (Virginia
Tech), Blacksburg, in 1986.
From 1986 to 1990, he was an assistant professor
and director of the Power and Industrial Electronics
Research Program in the Institute for Power and Elec-
tronic Engineering, at the University of Novi Sad, and
later, acting head of the Institute. He then joined the Bradley Department of
Electrical and Computer Engineering at Virginia Tech as Associate Professor.
He is now the American Electric Power Professor oh the department and co-di-
rector of the Center for Power Electronics Systems (CPES). His research in-
terests include multiphase power conversion, electronic power distribution sys-
tems, power electronics systems modeling and control, and multidisciplinary
design optimization.
Dr. Boroyevich is recipient of the IEEE William E. Newell Power Electronics
Technical Field Award. He is 20112012 President of IEEE Power Electronics
Society.
IEEE TRANSACTIONS ON SMART GRID, VOL. 3, NO. 1, MARCH 2012
Fred Wang (S85M91SM99F10) received the
B.S. degree from Xian Jiaotong University, Xian,
China, and the M.S. and Ph.D. degrees from the Uni-
versity of Southern California, Los Angeles, in 1982,
1985, and 1990, respectively, all in electrical engi-
neering.
He was a Research Scientist in the Electric Power
Lab, University of Southern California, from 1990 to
1992. He joined the GE Power Systems Engineering
Department, Schenectady, NY, as an Application En-
gineer in 1992. From 1994 to 2000, he was a Se-
nior Product Development Engineer with GE Industrial Systems, Salem, VA.
During 2000 to 2001, he was the Manager of Electronic & Photonic Systems
Technology Lab, GE Global Research Center, Schenectady, NY, and Shanghai,
China. In 2001, he joined the Center for Power Electronics Systems (CPES) at
Virginia Tech, Blacksburg, VA as a Research Associate Professor and became
an Associate Professor in 2004. From 2003, he also served as the CPES Tech-
nical Director. Since 2009, he has been with the University of Tennessee and
Oak Ridge National Lab, Knoxville, as a Professor and Condra Chair of Ex-
cellence in Power Electronics. His research interests include power electronics,
power systems, controls, electric machines, and motor drives.
Glenn Skutt (S85M88) received the B.S. degree
from Virginia Polytechnic Institute and State Univer-
sity (Virginia Tech), Blacksburg, in 1986, the M.S.
degree from Duke University, Durham, NC, in 1988,
and the Ph.D. degree from Virginia Tech, Blacksburg,
in 1996.
Currently, he is the President and Chief Tech-
nology Officer of PowerHub Systems, Blacksburg.
He has over 20 years experience in power elec-
tronics, dc-dc converter design, and power converter
manufacturing. He has worked as a computer power
supply and magnetic component engineer at Digital Equipment Corporation
and as high-reliability dc-dc power supply designer in the aerospace and space
markets at VPT, Inc for 12 years. He holds multiple patents and has published
over 25 technical articles in power electronics. He is an active member of
NISTs Smart Grid Priority Action Plan team in the area of energy storage
(PAP7) and is actively involved with EPRIs efforts to define uniform standards
for communication and control of grid-connected distributed energy resource
power inverters.