Impact Evaluation of Series DC Arc Faults in DC
Microgrids
Xiu Yao, Luis Herrera, and Jin Wang
Department of Electrical and Computer Engineering
The Ohio State University
Columbus, OH 43210
Email: yao.110@osu.edu
AbstractThis paper evaluates possible impacts of series dc
arc faults to dc microgrids. Series dc arc can happen at various
locations of a dc microgrid and is associated with high impedance
and low fault current level, which adds difficulty to detection and
protection. This paper firstly presents dc arc fault modeling of
both dc component and high frequency noise component. With
the dc arc model, the impact of dc arc faults at various locations
of a dc microgrid are then studied. Two different controllers
are adopted to study the interaction between dc arc faults and
microgrid controllers. It is found that current and voltage control
strategies can have adverse impact to dc arc faults and dc arc
faults at certain locations can be very difficult to detect with
existing dc microgrid protection strategies. Additional dc arc fault
detectors are of necessity to improve the overall safety of the
microgrid.
I. I NTRODUCTION
DC microgrid has better efficiency and reliability due to
the absence of skin effect and fewer conversion stages and is
therefore gaining significant popularity in many applications,
such as data center, more electric aircraft (MEA) [1]-[4].
With the development of renewable energy technology and
power electronics, researchers are also exploring dc distri-
bution networks extensively due to the dc nature of some
renewable energy resources like photovoltaic (PV). While dc
microgrids offer many advantages, challenges still remain. One
major challenge is the microgrid protection. The strategies and
devices for dc protection is quite different from ac protection,
therefore only very limited experiences can be used in dc
systems. Researchers have studied faults in dc microgrid
and proposed fault protection stategies [5]-[7]. However, the
previous studies on dc protection have been limited to short
circuit faults with excessive high fault current. One particular
fault which has been overlooked is dc arc fault.
Series dc arc fault can occur at arbitrary locations of any
dc system with high voltage dc bus [8]-[10]. Different from
short circuit faults, the arc channel is associated with high
impedance and therefore causes lower fault current than nom-
inal current. This adds significant difficulties to traditional arc
fault interrupter and majority of the dc protection strategies.
It is already known that dc arc faults, if not detected and
extinguished on time, will cause fire hazards and endanger
the whole system. References [9]-[10] has studied the char-
acteristics and detection of dc arc, while [8] has treated the
transient dc arc model. However, the impact of dc arc faults
978-1-4799-6735-3/15/$31.00 2015 IEEE 2953
in a system level scale such as a microgrid still needs to be
investigated.
In this paper, a steady state dc arc model to be used for
system level simulation study is firstly derived. This model
is comprised of not only the dc impedance but also the high
frequency arc noise to facilitate frequency domain detection
study. Then the impact of dc arc faults at various locations
of a ring type dc microgrid is investigated. Considering that
advanced control strategies including power flow control and
converter modulation are commonly adopted in modern dc
microgrid, which may pose extra challenges to fault protection,
two different droop control strategies are selected to investigate
the influence of system control to dc arc fault detection.
Finally, the indications for microgrid dc arc fault detection
and localization are discussed.
II. DC A RC FAULT M ODEL
In this section, the modeling of dc arc is studied. The goal
is to describe dc arc fault with a set of simple equations to
represent its electrical behavior. These equations will facilitate
system level simulations to study fault responses and protec-
tion strategies. It is noteworthy that only steady state arcing
is studied, which means the arc is burning stably and the arc
gap length and arc current has already settled. Transients at
the initial stage of arc development are not considered.
A. Arc Impedance Modeling
To describe the external characteristics and represent the
electrical behavior of arc, a macroscopic V-I equation is
adopted. In this case, arc can be seen as a non-linear resistor.
This method is useful for understanding arc behavior as part
of an electrical system which suits the purpose of this paper.
It requires large number of experiments to extract the proper
V-I equation in a statistical way.
DC arc V-I equation has been studied by the authors in
[9]. A test setup was established to accumulate arc data.
Experiments of the combination of 5 dc source voltage levels
(75 V, 120 V, 175 V, 240 V, and 300 V), 4 load current levels
(3 A, 6 A, 15 A, and 25 A), and 5 arc lengths (0.04 in, 0.06
in, 0.08 in, 0.10 in, and 0.12 in) were carried out in order to
examine their influence to arc characteristics. These values are
chosen to cover the ratings of most common LV dc systems.
The arc generating unit and a free burning arc is shown in
Fig. 1.

Fig. 1: Arc generating unit. (a) Probability density function and normal fitting.

Through analyzing these 100 sets of data, it is found that arc

length influences V-I pattern, and the following V-I equation
has been proposed with satisfactory fitting results [9]:
20.19 + 526.2L
Varc = 0.1174+1.888L
(1)
Iarc
where Varc and Iarc are arc voltage and current respectively,
and L is the gap length as an estimation of arc length. Details
of the derivation is available in [9]. This equation is used in
this paper to decide dc arc resistance with a given gap length.

B. Arc Noise Modeling (b) Normal fitting of different arc current level.

While V-I equation models the dc component, arc random-

ness is studied in this subsection. In [11], zero-mean Gaussian
noise function was used to describe the voltage fluctuation
of arc, while [8] added a randomly generated value to the
arc resistance equation. The rest of this subsection studies the
noise in arc current more closely with quatitative analysis.
Fig. 2 shows the Gaussian (Normal) distribution fitting of
filtered arc current using a 1.5 kHz - 45 kHz bandpass filter.
Fig. 2a represents the probability density function of filtered
arc current with its Gaussian distribution curve, showing good
agreement. The fitted Normal distribution function is given by:
1 (x)2 (c) Comparison of arc current and no arc current.
fx = e 22 (2)
2 Fig. 2: Normal distribution fittings.
where is the mean value and is the standard deviation. For
a zero-mean Gaussian distribution, equals to zero. There is
a small offset shown in Fig. 2a caused by the measurement C. Comprehensive Arc Model for Simulation Study
system. As Fig. 2a is an example of 15 A arc current, Fig. In the simulation in the following Section III, dc arc fault is
2b shows the Normal distribution fitting for all four different represented as a 10 resistor in parallel with a controlled cur-
current levels: 3A, 6 A, 15 A, and 25 A. It shows a clear rent source generating Gaussian distribution noise, as shown in
quatitative relationship between dc current level and . The Fig. 3. A 10 is chosen to simulate an arc fault of around 0.1
comparison of current without arc and with arc is presented in under the rated current of the microgrid studied in Section
in Fig. 2c. The noise from current without arc data is mainly III based on (1). The noise variance is approximated with 0.02
from measurement noise and can also be described with a based on preliminary results of Gaussian distribution fitting.
Gaussian distribution with a much smaller standard deviation.
III. I MPACT OF DC A RC FAULTS TO DC M ICROGRID
The impact of measurement error can be subtracted from the
arc current data. A. DC Microgrid System
With the 100 sets of data, the stand deviation of arc noise In this section, the impact of dc arc faults at various
is calculated for each different current level and arc length. locations of dc microgrid is studied. A MATLAB/Simulink
Thus, with a given arc length and current level, the arc noise model is established with a ring type dc microgrid consisting
level is obtained. of four buck converter sources and three resistive loads, as

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 Fig. 3: DC arc model for Matlab/Simulink simulation.

shown in Fig. 4a. Although a practical dc microgrid can be

more complicated with variable renewable sources and energy
storage units, this system is adopted as a generic example to
analyze dc arc fault impact [12][13]. The system parameters
are listed in Table I.
TABLE I: Simulation Parameters
(a) DC microgrid structure.
Parameter Symbol Values
DC bus reference voltage Vref 380 V
Load resistance Rload 192
Nominal current of source 1, 4 Irated,1 4A
Nominal current of source 2, 3 Irated,2 2A (b) Conventional droop controller.
Line impedance Z12 , Z45 , Z56 0.5 , 50 uH
Line impedance Z23 , Z34 , Z67 , Z71 1 , 100 uH

In order to study the interaction between microgrid con-

troller and dc arc faults, a conventional voltage droop con-
troller (CVD) and an adaptive voltage droop controller (AVD)
are applied for comparison, although there are many other
control strategies available [13]-[15]. The controller diagrams
are shown in Fig. 4b and Fig. 4c. The main difference of AVD
comes from the terms vi which is the locally averaged dc bus
voltage and r which is the output of the current regulator.
The equations for these two terms are shown below [13].
Z t X input stage or output stage of Source 1, dc bus Z71 , and
vi (t) = aij (vj ( ) vi ( ))d + vi (t);
0 jN
i
Z
X 8 Waveforms of the faulted sections are indicated by solid
i = bij (ipu
j ipu
i ); r = kp i + ki
jNi
where Ni is the set of all neighbors of converter i, aij and bij
are from the Adjacency matrix, and ipu i is the per unit current
Idc,i
value of converter i, equals to Irated,i .
The droop gain of each source converter with CVD control
is proportional to its current rating, to realize proportional
current sharing. However, line impedance on the dc bus causes
current sharing error in CVD. Therefore, current regulator is
introduced in AVD to guarantee that the current sharing is
accurately proportional to current rating of each converter.
Moreover, the voltage reference of CVD is always lower than
the rated value due to the droop gain. The AVD controller is
able to correct this bias and make sure the average voltage
value of all the nodes on dc bus is equal to the rated voltage
level.
(c) Adaptve droop controller.
Fig. 4: DC microgrid and controllers.
B. DC Arc Faults in Microgrid
With the above microgrid model, dc arc faults at various
locations are studied. The fault locations considered include:
(3) Load 7, as indicated in Fig. 4a. For all cases, dc arc fault
is initiated at 2 s. Simulation results are shown in Figs. 5-
i (4)
black curves to be distinguished from other dashed lines. Two
aspects are examined with the occurrence of dc arc fault: the
dc current and voltage values on feeders and buses, as well as
the traveling of high frequency arc noise across the microgrid.
1) Arc at input side of voltage source converter: For dc
arc faults inside a source converter, the controlled converter
output voltage Vdc,1 is measured at the common coupling
point, therefore the microgrid operation point does not change.
However when arc occurs at the input stage, input current is
elevated as can be seen from Fig. 5, which shows that CVD
controller made arc fault even worse with increased current.
AVD waveforms show a similar trend.
With an arc fault at the input side, the output voltage and
current remain the same, which indicates that arc protection
installed on the feeder or bus will not be able to protect the
input side of the converter.

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 reduces, and therefore weakens the dc arc fault. Moreover,
due to the voltage droop gain, Vdc,1 increases with reduced
current. Hence the controllers do not worsen the arc fault when
it occurs on the dc bus.
The case for AVD is more complicated. From Fig. 7b we
can see that the current sharing control is not functioning well.
However by adjusting the parameters of the current sharing
PI controllers, current sharing can be restored with the cost
of larger current ripples and longer stabilization time during
transients and after dc arc fault. This phenomenon arises
an interesting prospect of the relationship between microgrid
controller design and fault protection. On one hand, a robust
Fig. 5: Arc fault at Converter input(CVD). microgrid controller should be able to cope with a wide range
of operation conditions without compromising the current
2) Arc at output side of voltage source converter: Fig. 6 sharing capability. On the other hand, the unbalanced source
shows the system response when arc happens at the output currents in Fig. 7b could be promising dc arc fault indicators
side of Source 1. AVD controller is able to correct the error for detection purposes.
from CVD control. Both controllers can recover the system
operation to the same ratings as before arcing. Although
inserting a series dc arc impedance, arc current equals to Idc,1 ,
which is maintained the same as before arc. Both controllers
can be considered to be robust towards arc faults but have
adverse effect to the fault.
It is not possible to detect this fault based on dc value of
the voltage and current only. However it can be seen from
Fig. 6 that high frequency noise appear at Source 1 output
voltage and current, as well as the load current from adjacent
load feeder, as indicated by solid black curves. These high
frequency noise presents potential for efficient dc arc fault
detection using frequency domain signatures.

(a) Arc at dc bus (CVD) (b) Arc at dc bus (AVD)

Fig. 7: DC arc faults at dc bus.

4) Arc at load: Fig. 8 shows simulation results when a dc

(a) CVD control.
arc fault is introduced in series with Load 7. Both controllers
are able to function well during arc fault with only the faulted
load current dropping upon arc fault. This fault location has
the least impact to other parts of the system.
(b) AVD control.

Fig. 6: DC arc faults at output side of Source 1.

3) Arc at dc bus: Fig. 7 shows the system response when

arc happens on the dc bus in series with impedance Z71 .
It is equivalent to increasing line impedance. Due to the
unbalance of the bus impedance across the microgrid, the (a) Arc at load (CVD). (b) Arc at load (AVD).
current sharing error increases dramatically. The arc fault
causes more impact to the neighboring nodes. Due to increased Fig. 8: Simulation results of dc arc faults at Load 7.
impedance on line Z71 , the current drawn from Source 1

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 IV. DC A RC FAULT D ETECTION AND L OCALIZATION IN
DC M ICROGRIDS
Based on the system response of dc arc faults, detection
and microgrid protection are discussed in this section. The
response patterns under different fault locations are sum-
marized in Table II, where Y es means there is noticeable
change in either dc current value or high frequency component
that can be used for detection, and N o means neither dc
nor high frequency component in measured currents shows
abnormalities.
B. Proposed Solutions
Based on the fault responses from Section III and Table II,
a fault detection and localization method is proposed. Fault at
input side of converter is not considered in this case. Therefore,
fault localization is conducted among the remaining three
locations: arc at output side of voltage source, arc on dc bus,
and arc at load. The proposed protection strategy utilizes one
local detector at each feeder and one master detector for more
accurate fault localization. The functional flowcharts for local
detectors and master detector are shown in Figs. 9-11.

TABLE II: Current Change After DC Arc Fault

Fault location Local feeder Neighboring feeders DC bus
Converter input No No No
Converter output No Yes No
DC bus N/A Yes Yes
Load Yes No No

A. Challenges of DC Arc Fault Detection in Microgrids

Generally, arc fault detection is achieved through time-
domain and/or frequency domain change in fault current. Time
domain information has the advantages of simple calculation
and easy implementation, but is subject to false trip under nor-
mal operation changes. Frequency domain or time-frequency
domain detection usually has better efficiency but requires
more sophisticated hardware installation. The combination of
both time domain and time-frequency domain information Fig. 9: Flowchart of local detector at sources.
have been proposed by the authors to improve the overall
detection performance [9]. However, in the context of a dc
microgrid rather than a single loop circuit, the efficiency of
previous detection techniques are limited by two factors: mi-
crogrid control strategies and high frequency noise traveling.
These factors should be taken into account when planning the
protection system of a dc microgrid.
For example, when dc arc fault occurs at the output side of
a source converter, the local output current is controlled to be
the same as prior to arc, which is not good for fault detection.
What makes the situation worse is that the high frequency
noise from arc will travel to the neighboring load, as can be
seen from Fig. 6. This could easily cause mis-trigger from
the neighboring unfaulted load while leaving the fault in the
voltage source unattended.
A similar challenge is posed by arc fault on dc buses.
Neighboring load units observe current change in both dc
and high frequency components. Therefore by looking at load
currents only, it is very easy to confuse fault on bus with
fault at load. However, if the bus current is also considered, Fig. 10: Flowchart of local detector at loads.
the differentiation becomes easier: fault on dc bus will cause
current change in most bus currents, but all other types of The parameters used in the flowcharts are defined as fol-
fault will not influence bus currents. An alternative option is lows:
to examine all load currents together due to the fact that arc VS,i,DW T , IL,j,DW T : rms value of coefficients from two
at load will affect only that single load unit while fault on bus level discrete wavelet decomposition (DWT) of output
would impact multiple adjacent loads. voltage of source i, or load j current, respectively.

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Fig. 11: Flowchart of master detector.
IL,j,avg : change of average value (dc component) of
Load j current.
VS,i th , IL,j,dwt th , IL,j,avg th : threshold values.
Si,DW T , Lj,DW T , Lj,avg : arc event flags for DWT
detection of source i, DWT detection of load j, or average
value detection of load j, respectively. 1 means there is
an arc event, 0 means otherwise.
Local feeder detector has two main functions: monitor
feeder voltage and current, and local detection algorithm
calculation including average value step change and high fre-
quency noise DWT coefficient. Detailed calculation procedure
of DWT can be found in [9]. Local feeders also compare
calculated values with threshold and then send fault indicators
Si,DW T , Lj,DW T , Lj,avg to the master detector. Arc event
indicators show if the local feeder is experiencing abnormal
high frequency noise or step change, but local detectors cannot
decide if it is a local fault or it is influenced by fault at nearby
locations.
Master detector provides final decision on fault location by
considering fault indicators from all local detectors. For arc at
output side of source converter, the local detector is sufficient
to make decisions. If only one load reports high frequency
noise increase or step change, the fault is at load. Changes at
multiple loads indicate arc fault on dc bus. For arc fault at bus,
the load unit closest to the faulted bus experiences the highest
increase in high frequency noise. By finding the maximum
DWT coefficient from all loads, it is possible to locate the
load where the faulted bus is the closest to.
The proposed arc fault detection and localization strategy
provides general guidelines and framework of planning com-
prehensive dc arc fault protection in a microgrid. Details like
selecting threshold values and mis-trigger issues still need to
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be solved for real implementation. Means to differentiate series
dc arc fault from normal load step change should be included
when using time domain detection techniques.
V. C ONCLUSION
A dc arc model is proposed and utilized to study arc
fault impact to dc microgrid. The system response of dc
arc fault at different locations are studied in details. It is
found that at certain locations of the microgrid, dc arc fault
can either cause current sharing problem or become worse
due to controllers. Challenges of detecting and localizing dc
arc fault in a microgrid caused by microgrid controllers and
traveling of high frequency noise from arc current are then
discussed. Extrapolating these analysis, an arc fault detection
and localization strategy is proposed which provides a method
to coordinate fault detection at various locations.
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